KR100580402B1 - Methods for manufacturing thin film transistor array panels - Google Patents

Abstract

A gate wiring including a gate line and a gate electrode connected thereto is formed on an insulating substrate. Subsequently, a gate insulating film, a semiconductor layer, a contact layer, and a conductor layer covering the gate wirings are successively deposited on the substrate, and a photosensitive film pattern having a medium thickness is formed on the conductor layer. The silicon oxide layer is formed as an etch stop layer on the photoresist pattern through silylation) and an oxygen plasma process. Next, the conductor layer, the contact layer, and the semiconductor layer not covered by the photoresist pattern are etched to form a source / drain conductor pattern, an intermediate layer pattern, and a semiconductor pattern. In this process, an etch stop layer may be disposed on the upper portion of the photoresist pattern, thereby minimizing the etching of the photoresist pattern. In particular, the lower layer of the portion having an intermediate thickness may be prevented from being exposed or etched. Next, the etch stop layer is removed and the first portion of the photoresist pattern is removed using an oxygen plasma process. Next, a data line including a data line, a source electrode connected to the data line, a source electrode connected to the data line, a source electrode connected to the data line, and a drain electrode separated from the source electrode are etched by etching the intermediate layer. To form. Next, a protective insulating film is formed and a pixel electrode electrically connected to the drain electrode is formed on the protective insulating film.

Silicide, HMDS, TMDS, resin, photoresist, oxygen plasma

Description

METHODS FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY PANELS

1 is a layout view schematically illustrating a structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

2 and 3 are cross-sectional views of the thin film transistor substrate illustrated in FIG. 1 taken along lines II-II 'and III-III';

4A is a layout view of a thin film transistor substrate in a first step of manufacturing in accordance with an embodiment of the invention,

4B and 4C are cross-sectional views taken along the lines IVb-IVb 'and IVc-IVc' in FIG. 4A, respectively.

5A and 5B are cross-sectional views taken along the IVb-IVb 'line and the IVc-IVc' line in FIG. 4A, respectively, and are cross-sectional views of the next steps of FIGS. 4B and 4C.

6A is a layout view of a thin film transistor substrate in the next steps of FIGS. 5A and 5B;

6B and 6C are cross-sectional views taken along lines VIb-VIb 'and VIc-VIc' in FIG. 6A, respectively.

7A, 9A, 10A, and 7B, 9B, and 10B are cross-sectional views taken along lines VIb-VIb 'and VIc-VIc' in FIG. 6A, respectively, illustrating the following steps in the order of the process. ,

8 is a reaction scheme for a resin having an OH group according to a sillation and an oxygen plasma process in a manufacturing method according to an embodiment of the present invention,

11A is a layout view of a thin film transistor substrate in FIGS. 10A and 10B next steps;

11B and 11C are cross-sectional views taken along the lines XIb-XIb 'and XIc-XIc' in FIG. 11A, respectively.

The present invention relates to a method of manufacturing a thin film transistor array substrate.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. By controlling the amount of light transmitted.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on each of two substrates and switching a voltage applied to the electrode is generally used. The thin film transistor is generally formed on one of two substrates.

The substrate on which the thin film transistor is formed is generally manufactured through a photolithography process using a mask. At this time, in order to reduce the production cost, it is preferable to reduce the number of masks, and five or six masks are currently used. Of course, a method of manufacturing a thin film transistor substrate using four masks has been disclosed, but there is a problem in that it is very difficult to apply them.

An object of the present invention is to simplify the manufacturing method of a thin film transistor substrate for a liquid crystal display device.

Another object of the present invention is to provide a method of manufacturing a thin film transistor substrate for a liquid crystal display device, which facilitates process management and has reproducibility.

In order to achieve this problem, the lower layer is etched by using a photosensitive film pattern having an intermediate thickness thinner than other portions as an etching mask. In this case, when the lower layer of the photoresist pattern is etched, a portion having an intermediate thickness is etched to form an etch stop layer on the upper portion of the photoresist pattern to protect the lower layer from being etched.

In the method for manufacturing a thin film transistor substrate for a liquid crystal display according to the present invention, a gate wiring including a gate line and a gate electrode connected thereto is formed on an insulating substrate, and a gate insulating film, a semiconductor layer, a contact layer, and a conductive layer are covered on the substrate. The body layer is deposited successively. Subsequently, a photoresist pattern is formed on the conductor layer including a first part having a first thickness, a second part having a second thickness thicker than the first couple, and a third part having no thickness and excluding the first and second parts. An etch stop layer is formed to cover the photoresist pattern. Next, the conductor layer, the contact layer, and the semiconductor layer not covered by the photoresist pattern are etched to form a source / drain conductor pattern, an intermediate layer pattern, and a semiconductor pattern, and the etch stop layer is removed. Next, the first portion of the photoresist pattern is removed, and the source / drain conductor pattern not covered by the photoresist pattern and the intermediate layer are etched to include a data line, a source electrode connected to the data line, and a drain electrode separated from the source electrode. The data line and the contact layer pattern below it are formed. Next, a protective insulating film is formed and a pixel electrode electrically connected to the drain electrode is formed on the protective insulating film.

Here, the etch stop layer may be formed of a silicon oxide film, the photosensitive film pattern preferably comprises a resin having an OH group. In this case, the silicon oxide film may be formed through a sillation and an oxygen plasma process, and the silicide uses a sample of HMDS or TMDS containing Si.

In addition, it is preferable to use an ashing process using an oxygen plasma as a method of removing the first portion.

Then, a method of manufacturing a thin film transistor array substrate and a method of measuring a residual photoresist film according to an embodiment of the present invention with reference to the accompanying drawings can be easily carried out by those skilled in the art. It will be explained in detail.

First, a structure of a thin film transistor array substrate according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 1.

First, a unit pixel structure of a thin film transistor substrate for a liquid crystal display device completed through the manufacturing method according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2 to 3.

FIG. 1 is a layout view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 2 and 3 are along the II-II 'line and the III-III' line of the thin film transistor substrate shown in FIG. It is sectional drawing cut out.

First, a gate made of a metal or a conductor such as aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta) or the like on the insulating substrate 10. Wiring is formed. The gate wiring is connected to the scan signal line or the gate line 22 extending in the horizontal direction and the gate line 22 and the gate pad 24 and the gate which receive the scan signal from the outside and transmit the scan signal to the gate line 22. A gate electrode 26 of the thin film transistor that is part of the line 22, and a sustain electrode 28 that is parallel to the gate line 22 and receives a voltage such as a common electrode voltage input to the common electrode of the upper plate from the outside. . The storage electrode 28 overlaps with the conductive capacitor conductor 68 for the storage capacitor connected to the pixel electrode 82, which will be described later, to form a storage capacitor which improves the charge retention capability of the pixel. The pixel electrode 82 and the gate line, which will be described later, If the holding capacity generated by the overlap of (22) is sufficient, it may not be formed.

The gate wirings 22, 24, 26, and 28 may be formed as a single layer, but may be formed as a double layer or a triple layer. In the case of forming more than two layers, it is preferable that one layer is formed of a material having a low resistance and the other layer is formed of a material having good contact properties with other materials, and a double layer of Cr / Al (or Al alloy) or Al / Mo Bilayers are an example.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate wirings 22, 24, 26, and 28 to cover the gate wirings 22, 24, 26, and 28.

Semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed on the gate insulating layer 30, and high concentrations of n-type impurities such as phosphorus (P) are formed on the semiconductor patterns 42 and 48. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon doped with is formed.

On the contact layer patterns 55, 56, and 58, a data line made of a conductive material such as Mo or MoW alloy, Cr, Al or Al alloy, and Ta is formed. The data line is a thin film transistor which is a branch of the data line 62 formed in the vertical direction, the data pad 64 connected to one end of the data line 62 to receive an image signal from the outside, and the data line 62. And a data line portion of the source electrode 65 of the source electrode 65, separated from the data line portions 62, 64, and 65, of the source electrode 65 with respect to the gate electrode 26 or the channel portion C of the thin film transistor. It also includes a conductive capacitor conductor 68 for the storage capacitor located on the drain electrode 66 and the storage electrode 28 of the thin film transistor located on the opposite side. When the sustain electrode 28 is not formed, the conductor pattern 68 for the storage capacitor is also not formed.

The data lines 62, 64, 65, 66, 68 may also be formed in a single layer like the gate lines 22, 24, 26, 28, but may be formed in a double layer or a triple layer. Of course, when forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials.

The contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has exactly the same form as (62, 64, 65, 66, 68). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 64 and 65, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor pattern 68 for holding capacitors.

The semiconductor patterns 42 and 48 have the same shapes as the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 57 except for the channel portion C of the thin film transistor. have. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor pattern 68 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the semiconductor pattern 42 for the thin film transistor has data wiring and contact. Slightly different from the rest of the layer pattern. That is, the data line parts 62, 64, 65, in particular, the source electrode 65 and the drain electrode 66 are separated from the channel portion C of the thin film transistor, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode is separated. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor.

The passivation layer 70 is formed on the data wires 62, 64, 65, 66, and 68, and the passivation layer 70 forms the drain electrode 66, the data pad 64, and the conductive pattern 68 for the storage capacitor. The contact holes 71, 73, and 74 are exposed, and the contact holes 72 are exposed to expose the gate pad 24 together with the gate insulating film 30. As shown in FIG. The passivation layer 70 may be made of an organic insulating material such as silicon nitride or acrylic.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as indium tin oxide (ITO), and is physically and electrically connected to the drain electrode 66 through the contact hole 71 to receive an image signal. The pixel electrode 82 also overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. In addition, the pixel electrode 82 is also connected to the storage capacitor conductor pattern 68 through the contact hole 74 to transmit an image signal to the conductor pattern 68. On the other hand, an auxiliary gate pad 84 and an auxiliary data pad 86 connected to the gate pad 24 and the data pad 64 through the contact holes 72 and 73, respectively, are formed. , 64) and to protect the pads and the adhesion of the external circuit device, it is not essential, and their application is optional.

Although transparent ITO has been used as an example of the material of the pixel electrode 82, an opaque conductive material may be used for the reflective liquid crystal display device.

Next, a method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 5A to 11C and FIGS. 1 to 3. At this time

First, as illustrated in FIGS. 4A to 4C, a conductive layer such as a metal is deposited to a thickness of 1,000 kPa to 3,000 kPa by a sputtering method, and first, dry or wet etch using a mask to form a gate on the substrate 10. A gate wiring including a line 22, a gate pad 24, a gate electrode 26, and a sustain electrode 28 is formed.

Next, as shown in FIGS. 5A and 5B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 are respectively 1,500 kV to 5,000 kV, 500 kV to 2,000 kV, and 300 kV using chemical vapor deposition. Continuously deposited to a thickness of 600 to 600 kPa, and then depositing a conductor layer 60 such as a metal to a thickness of 1,500 kPa to 3,000 kPa by sputtering or the like, and then depositing a photoresist film 110 thereon at a thickness of 1 μm to 2 μm. Apply with

Thereafter, the photoresist film 110 is irradiated with light through a second mask and then developed to form photoresist patterns 112 and 114 as illustrated in FIGS. 7B and 7C. In this case, among the photoresist patterns 112 and 114, the channel portion C of the thin film transistor, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, is the data wiring portion A, that is, the data. The thickness of the wirings 62, 64, 65, 66, and 68 is smaller than that of the second portion 112 positioned at the portion where the wirings 62, 64, 65, 66, and 68 are to be formed, and all the photoresist of the other portion B is removed. At this time, the ratio of the thickness of the photoresist film 114 remaining in the channel portion C to the thickness of the photoresist film 112 remaining in the data wiring portion A should be different depending on the process conditions in the etching process described later. It is preferable to make the thickness of the 1st part 114 into 1/2 or less of the thickness of the 2nd part 112, for example, it is good that it is 4,000 Pa or less.

As such, there may be various ways of varying the thickness of the photoresist film according to the position, and in order to control the amount of light transmission, a slit or grid pattern may be formed or a translucent film may be used.

At this time, the line width of the pattern located between the slits or the interval between the patterns, that is, the width of the slits is preferably smaller than the resolution of the exposure machine used during exposure, and in the case of using a semi-transparent film, in order to control the transmittance used when manufacturing the mask A thin film having a transmittance may be used or a thin film having a different thickness may be used.

When such light is irradiated onto the photoresist film, the polymers are completely decomposed at the part directly exposed through the first area that completely transmits the light, and at the part corresponding to the second area where the slit pattern or translucent film is formed. Due to the low irradiation dose, the polymers are not completely decomposed, and the polymers are hardly decomposed at the part corresponding to the third region covered by the light shielding film. The longer exposure time decomposes all the molecules, so it should be avoided. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light.

Such a thin photoresist film is exposed to a photoresist film made of a reflowable material with a conventional mask divided into a part that can completely transmit light and a part that can not completely transmit light, and then developed and reflowed so that the photoresist film remains. The photosensitive film 114 having an intermediate thickness can be formed by flowing a portion of the photosensitive film to a portion not to be formed.

Subsequently, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40. In this case, the data line and the lower layer of the data line remain in the data wiring portion A, and only the semiconductor layer should remain in the channel portion C, and the upper three layers 60, 50, 40 must be removed to expose the gate insulating film 30.

First, as shown in FIGS. 9A and 9B, the exposed conductor layer 60 of the other portion B, the intermediate layer 50 and the semiconductor layer 40 underneath are removed to remove the gate insulating film 30 thereunder. Expose

In this case, in the process of etching the conductor layer 60, the intermediate layer 50 and the semiconductor layer 40 below, either a dry etching method or a wet etching method may be used. In this case, the conductor layer 60 and the intermediate layer 50 may be used. And the semiconductor layer 40 is etched and the photoresist patterns 112 and 114 are hardly etched. In particular, in the case of dry etching, only the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40 are etched, respectively, and the photoresist patterns 112 and 114 are difficult to find. In addition, the process is performed under the conditions etched together. In this process, it is preferable to thicken the first portion 114 so that the first portion 114 is removed so that the lower conductive layer 60 is not exposed. However, when the first portion 114 is not formed to have a uniform thickness with respect to the entire substrate, the first portion 114 may be etched to expose or etch the conductive layer 60 thereunder. Since the channel portion C is not uniformly formed over the entire substrate, a problem arises in that the specificity of the thin film transistor is lowered, resulting in a decrease in process yield and a process having reproducibility. In order to solve this problem, in the manufacturing method according to the embodiment of the present invention, as shown in FIGS. 7A and 7B, the etch stop layer 200 is formed on the surface of the photoresist patterns 112 and 114 to form the first portion ( 114) to minimize the etching. In this case, the etch stop layer 200 may be formed of a silicon oxide (SiO _X ) film, and the silicon oxide film 200 may be formed as HMDS (Hexa-Methyl-Disiloxane) or TMDS (Tetra-Methyl-Disilxane). It is formed through a silicide and an oxygen (O ₂ ) plasma process using a sample containing Si. In the siliation process, as a first step of FIG. 8, a sample such as HMDS or TMDS is added to the photoresist films 112 and 114 including a resin having an OH group, and the OH group is added to O-Si-R such as OSi (CH ₃ ) ₃ . Substituting the form, the surface treatment using an oxygen plasma process as a second step of FIG. 8 causes OSi (CH ₃ ) ₃ to be changed to OSiO _X so that SiO _{2 is} formed on top of the photoresist films 112 and 114. The film 200 is formed.

As shown in FIGS. 7A and 7B, the etch stop layer 200 is formed, and then the conductor layer 60 having the photoresist patterns 112 and 114 exposed as an etch mask, the intermediate layer 50 and the semiconductor layer below Each of the portions 40) is etched, and as shown in Figs. 9A and 9B, the conductor layer of the channel portion C and the data wiring portion A, that is, the conductor pattern 67 for the source / drain and the conductor pattern for the storage capacitor, respectively. Only the 68 remains, and the conductor layer 60 of the other portion B, the intermediate layer 50 and the semiconductor layer 40 below it are all removed to reveal the gate insulating film 30 thereunder. In this case, the etch stop layer 200 is formed on the photoresist patterns 112 and 114, and in particular, even if the thickness of the photoresist pattern 114 is not uniformly formed over the entire substrate, the photoresist patterns 112 and 114 are formed. When the three layer films 60, 50, and 40 are etched using the mask, the photoresist patterns 112 and 114 may be minimized to expose the lower layers 60, 50, and 40 of the photoresist pattern 114. Etching can be prevented uniformly with respect to the whole board | substrate.

9A and 9B, the etch stop layer 200 is removed and an ashing process using an oxygen plasma is performed to remove only the photoresist pattern 114.

Here, the remaining conductor patterns 67 and 68 are the same as those of the data lines 62, 64, 65, 66 and 68 except that the source and drain electrodes 65 and 66 are connected without being separated. .

This removes the first portion 114 of the channel portion C, revealing the source / drain conductor pattern 67, as shown in FIGS. 9A and 9B, and the intermediate layer 50 of the other portion B. And the semiconductor layer 40 is removed to expose the gate insulating layer 30 thereunder. At this time, as described above, when etching the three-layer film (60, 50, 40) in the other portion (B), by placing the etch stop layer 200, the lower layer (60, 50, 40) of the photosensitive film pattern 114 By preventing the etching, the conductor pattern 67 for the source / drain may be uniformly exposed to the entire substrate, and the channel portion C of the thin film transistor may be uniformly formed in a subsequent process. Even if the photosensitive film 114 is formed nonuniformly, process management having reproducibility can be easily performed.

Meanwhile, at this time, since the second portion 112 of the data line part A is also etched, the thickness becomes thin. In this step, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 indicate the intermediate layer pattern under the source / drain conductor pattern 67 and the intermediate layer pattern under the storage capacitor conductor pattern 68, respectively.

Next, as shown in FIGS. 10A and 10B, the source / drain conductor pattern 67 of the channel part C and the source / drain interlayer pattern 57 below are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 67 and the intermediate layer pattern 57. The etching may be performed by wet etching on the source / drain conductor pattern 67. 57 may be performed by dry etching. In the former case, it is preferable to perform etching under a condition in which the etching selectivity of the source / drain conductor pattern 67 and the interlayer pattern 57 is large, which is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 42 remaining in the " For example, those of etching the SF ₆ and O ₂ by using the mixed gas of the source / drain conductive pattern 67. In the latter case of alternating between wet etching and dry etching, the side surface of the conductive pattern 67 for wet etching of the source / drain is etched, but the intermediate layer pattern 57 which is dry etched is hardly etched, thus making a step shape. Examples of the etching gas used to etch the intermediate layer pattern 57 and the semiconductor pattern 42 include the aforementioned mixed gas of CF ₄ and HCl or mixed gas of CF ₄ and O ₂ , and CF ₄ and O _{Using 2} can leave the semiconductor pattern 42 in a uniform thickness. In this case, as shown in FIG. 10B, a portion of the semiconductor pattern 42 may be removed to reduce the thickness, and the second portion 112 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching must be performed under the condition that the gate insulating film 30 is not etched, and the photoresist film is not exposed so that the second portion 112 is etched so that the data lines 62, 64, 65, 66, and 68 underneath are not exposed. It is a matter of course that the pattern is thick.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 under the data lines.

Finally, the second photoresist layer 112 remaining in the data wiring portion A is removed. However, the removal of the second portion 112 may be made after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 57 thereunder.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

After the data wirings 62, 64, 65, 66, and 68 are formed in this manner, as shown in FIGS. 11A to 11C, silicon nitride is deposited by CVD or spin-coated an organic insulating material to have a thickness of 3,000 Å or more. The protective film 70 is formed. Subsequently, the passivation layer 70 is etched together with the gate insulating layer 30 by using a third mask to form the drain electrode 66, the gate pad 24, the data pad 64, and the conductive pattern 68 for the storage capacitor, respectively. The exposed contact holes 71, 72, 73, 74 are formed.

Finally, as shown in FIGS. 2 to 4, an ITO layer having a thickness of 400 μs to 500 μs is deposited and etched using a fourth mask to form the pixel electrode 82, the auxiliary gate pad 84, and the auxiliary data pad. Form 86.

As described above, in the present exemplary embodiment, the data lines 62, 64, 65, 66, 68, the contact layer patterns 55, 56, 58, and the semiconductor patterns 42, 48 below them are formed using one mask. In this process, the source electrode 65 and the drain electrode 66 may be separated to simplify the manufacturing process. In addition, the etching stop layer 200 may be formed to minimize the etching of the photoresist pattern 114 having an intermediate thickness to prevent the lower layer from being etched, thereby uniformly improving the characteristics of the thin film transistor over the entire substrate. Process control with reproducibility can be carried out.

As described above, according to the present invention, in order to effectively reduce the number of masks when manufacturing a thin film transistor substrate for a liquid crystal display device, a photoresist pattern having a partially different thickness is formed and the photoresist pattern is etched when the lower layer is etched by the etching mask. By forming an etch stop layer on top of the photoresist pattern to minimize it, the characteristics of the thin film transistor may be uniformly improved over the entire substrate, and process management having reproducibility may be easily performed.

Claims (12)

Forming a gate wiring including a gate line and a gate electrode on the substrate, Continuously depositing a gate insulating film, a semiconductor layer, a contact layer, and a conductor layer covering the gate wiring on the substrate; Forming a photoresist pattern on the conductor layer including a first portion having a first thickness, a second portion having a second thickness thicker than the first couple, and a third portion having no thickness and excluding the first and second portions; step, Forming an etch stop layer covering the photoresist pattern, Etching the conductor layer, the contact layer, and the semiconductor layer not covered by the photoresist pattern to form a source / drain conductor pattern, an intermediate layer pattern, and a semiconductor pattern; Removing the etch stop layer, Removing the first portion of the photoresist pattern, Contacting a data line including a data line, a source electrode connected to the data line, and a drain electrode separated from the source electrode by etching the source / drain conductor pattern and the intermediate layer not covered by the photoresist pattern Forming a layer pattern, Depositing a protective insulating film, Forming a pixel electrode electrically connected to the drain electrode on the protective insulating layer Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. In claim 1, The etch stop layer is a silicon oxide film, a method of manufacturing a thin film transistor substrate for a liquid crystal display device. In claim 1, The said photosensitive film pattern is a manufacturing method of the thin film transistor substrate for liquid crystal display devices containing resin which has OH group. The method of claim 2 or 3, The silicon oxide film is formed by a silicide and an oxygen plasma process. In claim 4, The said silicide is a manufacturing method of the thin film transistor substrate for liquid crystal display devices using the sample containing Si. In claim 5, The sample is a method for manufacturing a thin film transistor substrate for a liquid crystal display device using HMDS or TMDS. In claim 1, The method of claim 1, wherein the removing of the first portion comprises an ashing process using oxygen plasma. In claim 1, The photoresist pattern may be formed by a photo process using a mask having a partially different transmittance of light, and the mask may include a first part through which only part of the light may be transmitted, a second part through which light cannot be transmitted completely, and light through And a third portion, wherein the photoresist pattern is a positive photoresist, and the first, second, and third portions of the mask are aligned to correspond to the first, second, and third portions of the photoresist pattern, respectively, during the exposure process of the photolithography process. The manufacturing method of the thin film transistor substrate for liquid crystal display devices used. In claim 8, And a first portion of the mask comprises a translucent film. In claim 8, And a first portion of the mask comprises a pattern smaller in size than the resolution of the light source used in the exposing step. In claim 1, And a first portion of the photoresist pattern is formed through reflow. In claim 1, The gate line further includes a gate pad connected to the gate line to receive a signal from the outside, and the data line further includes a data pad connected to the data line to receive a signal from the outside, And forming an auxiliary gate pad and an auxiliary data pad on the passivation layer, wherein the auxiliary gate pad and the auxiliary data pad are respectively connected to the gate pad and the data pad and formed on the same layer as the pixel electrode.

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