KR100309925B1 - Thin film transistor array panel for liquid crystal display and manufacturing method thereof, and photomasks used thereto - Google Patents

Abstract

A gate wiring is formed on the insulating substrate, and a gate insulating film, a doped amorphous silicon layer, an amorphous silicon layer, and a data metal layer are sequentially stacked and patterned on the gate wiring to form a data wiring and a contact layer pattern thereunder, and a protective film is formed thereon. Laminated. A thin film transistor substrate for a liquid crystal display device is manufactured by forming a photoresist pattern having a different thickness on a portion of the protective film, and etching the protective film, semiconductor layer, and gate insulating film below the photoresist pattern as a mask. At this time, a photosensitive film pattern having a different thickness is formed of a transparent substrate, a light having a transmittance control film having a portion removed thereon and a slit pattern formed at another portion and an opaque film formed at a predetermined portion on the transmittance control film. Form using a mask. In this way, the yield can be increased while simplifying the manufacturing process of the thin film transistor substrate for liquid crystal display devices.

Description

Thin film transistor array panel for liquid crystal display and manufacturing method thereof and photomask used in the same

The present invention relates to a method of manufacturing a thin film transistor substrate for a liquid crystal display device and an optical mask used therein.

In general, a liquid crystal display device injects a liquid crystal material between an upper substrate on which a common electrode and a color filter are formed, and a lower substrate on which a thin film transistor and a pixel electrode are formed. By applying a different potential to form an electric field to change the arrangement of the liquid crystal molecules, and through this to control the light transmittance is a device that represents the image.

Among the two substrates, the thin film transistor substrate for a liquid crystal display device has a basic structure of a thin film transistor formed on the substrate and a pixel electrode controlled thereby, as in the present inventors patent application No. 95-189.

As in this patent application, a thin film transistor substrate is manufactured through film formation and photolithography processes of a thin film over several layers, and photolithography recovery represents a number of manufacturing processes. Therefore, how stable a device is formed through a small number of photolithography processes is an important factor in determining the manufacturing cost, as also shown in the aforementioned No. 95-189.

However, in the conventional general photolithography process, as shown in No. 95-189, the photoresist film is divided into two parts, that is, a part exposed to light and an exposed part, and then exposed to light, so that the photoresist film is completely absent or has a constant thickness. Present, and therefore the etching depth is constant.

Meanwhile, as another conventional technology, A TFT Manufactured by 4 Masks Process with New Photolithography (Chang Wook Han et al., Proceedings of The 18th International Display Research Conference Asia Display 98, p. 1109-1112, 1998. 9.28-10.1) Asian Display ') describes a method of manufacturing a thin film transistor using four masks. In this technique, by exposing a positive photoresist film using a mask with a grid on only a specific part, the amount of light irradiated to the grid part is reduced to form a photoresist pattern with a part thinner than other parts, and the photolithography is used. It is to reduce the number of times. However, in this case, since the area that can be processed with the grid mask is limited, it is difficult to process a wide range of areas, or even if it is possible, it is difficult to process to have a uniform etching depth as a whole.

In addition, when forming a photosensitive film having a different thickness depending on the part by varying the exposure amount, it is necessary to precisely adjust the exposure amount. When the pattern formed of a metal or the like, which is a material that reflects light well, is formed on the part Since the silver receives the reflected light and receives more light than other portions, it is difficult to control the exposure amount, and thus there is a problem in that the thickness of the photoresist film cannot be adjusted.

An object of the present invention is to simplify the method of manufacturing a thin film transistor substrate for a liquid crystal display device.

Another technical problem to be achieved by the present invention is to enable to precisely adjust the exposure amount of the photomask according to the part.

1 is a cross-sectional view of an optical mask according to an embodiment of the present invention,

2 is a layout view of a thin film transistor substrate for a liquid crystal display device manufactured according to an embodiment of the present invention;

3 and 4 are cross-sectional views taken along line III-III 'and IV-IV' of FIG. 2, respectively.

5A is a layout view of a substrate in an intermediate process of manufacturing a thin film transistor substrate according to an embodiment of the present invention;

5B and 5C are cross-sectional views taken along lines Vb-Vb 'and Vc-Vc' of FIG. 5A, respectively.

6A is a layout view of a substrate in a next step of FIGS. 5A to 5C during a process of manufacturing a thin film transistor substrate according to an embodiment of the present invention;

6B and 6C are cross-sectional views taken along lines VIb-VIb 'and VIc-VIc' of FIG. 6A, respectively.

7A is a layout view of a substrate in a next step of FIGS. 6A to 6C during a process of manufacturing a thin film transistor substrate according to an embodiment of the present invention;

7B and 7C are cross-sectional views of lines VIIb-VIIb 'and VIIc-VIIc' of FIG. 7A, respectively, and also show an optical mask used at this time.

FIG. 8 is a layout view of an optical mask used in the steps of FIGS. 7A to 7C;

9A and 9B are cross-sectional views of lines VIIb-VIIb 'and VIIc-VIIc' of FIG. 7A, respectively, and are cross-sectional views of the next steps of FIGS. 7B and 7C;

10A and 10B are cross-sectional views of lines VIIb-VIIb 'and VIIc-VIIc' of FIG. 7A, respectively, and are cross-sectional views at the next steps of FIGS. 9A and 9B, and

11A and 11B are cross-sectional views taken along lines VIIb-VIIb 'and VIIc-VIIc' of FIG. 7A, respectively, and are cross-sectional views at the next steps of FIGS. 9A and 9B;

12A and 12B are cross-sectional views taken along lines VIIb-VIIb 'and VIIc-VIIc' of FIG. 7A, respectively, and are cross-sectional views at the next steps of FIGS. 11A and 11B;

13A and 13B are cross-sectional views taken along the lines VIIb-VIIb 'and VIIc-VIIc' of FIG. 7A, respectively, and are cross-sectional views at the next steps of FIGS. 12A and 12B;

14A and 14B are cross-sectional views taken along the lines VIIb-VIIb 'and VIIc-VIIc' of FIG. 7A, respectively, and are cross-sectional views at the next steps of FIGS. 13A and 13B.

In order to solve this problem, in the present invention, two films having different light transmittances are formed on a transparent substrate, and the light transmittance is subdivided by forming a transmittance control pattern on at least one of them.

Specifically, in the optical mask formed on the transparent substrate by forming a first film having a lower light transmittance than the substrate and a second film having a light transmittance different from the first film and the substrate, the substrate is formed. A first part completely covered with the first film, a second part in which the transmittance adjustment pattern is formed in the first film, and a third part in which the first film is removed, are formed in a specific part of the substrate.

In this case, the second film may be formed only on a specific portion of the first portion, the substrate may have a light transmittance of 90% or more with respect to the exposure light, the second film may have a light transmittance of 3% or less with respect to the exposure light, and the second film may have a It may have a light transmittance of% to 40%. In addition, the transmittance adjustment pattern may be a slit pattern, a transmittance adjustment pattern may also be formed on the second layer, and the second layer may be formed only on a portion of the first portion.

A method of manufacturing a thin film transistor substrate for a liquid crystal display device using such a photomask includes forming a gate wiring, forming a gate insulating layer pattern, forming a semiconductor layer pattern, forming a contact layer pattern, and data. Forming a wiring, forming a protective insulating pattern having a first contact hole to expose the drain electrode, and forming a pixel electrode connected to the drain electrode through the first contact hole on the protective insulating film, wherein The gate insulating layer pattern may be formed using a photosensitive layer pattern having a different thickness depending on a portion thereof, and formed together with at least one of a semiconductor layer pattern, a contact layer pattern, a data line, a protective insulating layer pattern, and a pixel electrode in an etching process using the photosensitive layer pattern Here, the photoresist pattern having a different thickness depending on the part uses the photomask. To form.

At this time, in the process of forming a photoresist pattern having a different thickness depending on the portion, the photomask includes a portion where the second film is formed corresponding to the periphery of the thin film transistor substrate and the data wiring, and the second portion corresponds to the gate line. Three parts may be aligned to correspond to the gate pad and the data pad.

In addition, the photoresist pattern may have a first portion, a second portion thicker than the first portion, and a third portion thicker than the second portion, wherein the first portion is positioned above the gate pad and the second portion is positioned on the screen display. have. The photoresist pattern may be formed on the protective insulating layer, and the forming of the gate insulating layer pattern, the semiconductor layer pattern, and the protective insulating layer pattern may be performed by etching the protective insulating layer and the semiconductor layer under the first portion while etching the second layer. Etching the portion, removing the second portion through an ashing process to expose the protective insulating film under it, etching the protective insulating film and the gate insulating film using the photoresist pattern as a mask to expose the semiconductor layer under the second portion. And forming a second contact hole exposing the gate pad under the first portion, and removing the semiconductor layer from the second portion using the photoresist pattern as a mask.

Next, an optical mask according to an embodiment of the present invention will be described with reference to the drawings.

1 is a cross-sectional view of an optical mask according to an embodiment of the present invention.

The photomask according to the embodiment of the present invention includes a transparent substrate 510, a transmittance adjusting film 520 and an opaque film 530 formed thereon. In this case, the opaque film 530 preferably has a transmittance of 3% or less with respect to the G line, the H line or the I line among the wavelengths of light, and the transmittance adjusting film 520 is between 20% and 40%. Preferably, the transparent substrate 510 is preferably 90% or more. In this case, the light transmittance difference between the transmittance adjusting film 520 and the opaque film 530 may be formed by using different light transmittances of the material itself, or may be formed by using the same material but varying its thickness. have. In the latter example, the chromium is formed to a thickness of 100 kPa to 300 kPa to be used as the transmittance adjusting film 520, and the same chromium is formed to be thicker than the transmittance adjusting film 520 to be used as the opaque film 530. Can be mentioned.

The substrate 510 is divided into five parts according to the degree of light transmission. That is, part A which hardly transmits light, part B which transmits most of the light, part C where the light transmittance is between A and B, and part E where light transmittance is between B and C The part and the transmittance are divided into the F part which is halfway between the C part and the A part. Here, the transmittance adjusting film 520 and the opaque film 530 are both formed on the substrate 510 in the A portion, nothing is formed on the substrate 510 in the B portion, and the substrate 510 is formed in the C portion. Only the transmittance adjustment film 520 is formed thereon. In addition, the transmittance adjusting film 520 is formed on the substrate 510 in the E portion, but a plurality of slit patterns are formed on the transmittance adjusting film 520, and the transmittance adjusting film 520 and the opaque film 530 are formed in the F portion. ) Is formed, but a plurality of slit patterns are formed on the opaque film 530.

At this time, the slit pattern formed in the transmittance adjusting film 520 of the portion E and the opaque film 530 of the portion F must be narrower than the resolution of the light source used for exposure of the photosensitive film, which means that the light This is to allow diffraction in the passing process so that only a part of the incident light is transmitted. The pattern formed on the transmittance adjusting film 520 and the opaque film 530 is not necessarily a slit pattern, and may have any shape as long as it can cause diffraction of light. That is, a mosaic shape etc. can also be used.

In this way, the light transmittance can be decomposed into five stages in one optical mask formed of only two films having different substrates and light transmittances.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device using the photomask described above will be described.

First, a structure of a thin film transistor substrate for a liquid crystal display device manufactured according to an exemplary embodiment of the present invention will be described with reference to the drawings.

2 is a layout view of a thin film transistor substrate for a liquid crystal display device manufactured according to an exemplary embodiment of the present invention, and FIGS. 3 and 4 are cross-sectional views taken along lines III-III 'and IV-IV' of FIG. 2, respectively.

First, a gate made of a metal or a conductor such as aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta) or the like on the insulating substrate 10. Wiring is formed. The gate wiring is connected to the scan signal line or the gate line 22 extending in the horizontal direction, the gate pad 24 and the gate which receive the scan signal from the outside and transmit the scan signal to the gate line 22 from the outside. A gate electrode 26 of the thin film transistor that is part of the line 22.

The gate wirings 22, 24, and 26 may be formed in a single layer, but may also be formed in a double layer or a triple layer. In the case of forming more than two layers, it is preferable that one layer is formed of a material having a low resistance and the other layer is formed of a material having good contact properties with other materials, and a double layer of Cr / Al (or Al alloy) or Al / Mo Bilayers are an example.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate wirings 22, 24, and 26 to cover the gate wirings 22, 24, and 26.

Semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed on the gate insulating layer 30, and high concentrations of n-type impurities such as phosphorus (P) are formed on the semiconductor patterns 42 and 48. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon doped with is formed.

On the contact layer patterns 55, 56, and 58, a data line made of a conductive material such as Mo or MoW alloy, Cr, Al or Al alloy, and Ta is formed. The data line is a thin film transistor which is a branch of the data line 62 formed in the vertical direction, the data pad 64 connected to one end of the data line 62 to receive an image signal from the outside, and the data line 62. And a data line portion formed of a source electrode 65 of the.

The data lines 62, 64, 65, and 66 may be formed in a single layer like the gate lines 22, 24, and 26, but may also be formed in a double layer or a triple layer. Of course, when forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials.

The contact layer patterns 55 and 56 lower the contact resistance of the semiconductor pattern 42 below and the data lines 62, 64, 65, and 66 above it, and the data lines 62, 64, and 65. , 66). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 64, and 65, and the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66.

On the other hand, the semiconductor pattern 42 has a shape similar to that of the data lines 62, 64, 65, 66 and the contact layer patterns 55, 56, 57. Specifically, only the thin film transistor semiconductor pattern 42 differs from the rest of the data wiring and the contact layer pattern. That is, the data line parts 62, 64, 65, in particular, the source electrode 65 and the drain electrode 66 are separated from the channel portion C of the thin film transistor, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode is separated. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor.

The data line portions 62, 64, and 65, the drain electrode 66, and the semiconductor pattern 42 are covered by the passivation layer 70, and the passivation layer 70 exposes a contact window exposing the drain electrode 66 and the data pad 64. Has (71, 73). The passivation film 70 also has a contact window 72 exposing the gate pad 24 together with the gate insulating film 30 and the semiconductor pattern 42, and a portion of the gate line 22 overlapping the data line 62. Except for the rest of it is not covered. The passivation layer 70 may be formed of an organic insulating material such as silicon nitride or acrylic, and may cover and protect at least a channel portion of the semiconductor pattern 42 positioned between the source electrode 65 and the drain electrode 66.

The pixel electrode 82 is formed on the gate insulating film 30 in the region surrounded by the gate line 22 and the data line 62. The pixel electrode 82 is physically and electrically connected to the drain electrode 66 through the contact window 71 to receive an image signal from the thin film transistor to generate an electric field together with the electrode of the upper plate, and to form an indium tin oxide (ITO). Made of transparent conductive material On the other hand, an auxiliary gate pad 84 and an auxiliary data pad 86 connected to the gate pad 24 and the data pad 64 through the contact windows 72 and 73, respectively, are formed. , 64) and to protect the pads and the adhesion of the external circuit device, it is not essential, and their application is optional.

On the other hand, an opening 31 for exposing the substrate 10 is formed in the gate insulating film 30 between the pixel electrode 82 and the protective film 70 pattern covering the data line 62. The opening 31 is formed by the data line semiconductor pattern 42 remaining too wide around the data line 62 to be connected to the pixel electrode 82, thereby shorting the pixel electrode 82 and the data line 62. To prevent this. In addition, the opening 31 is formed to prevent the neighboring pixel electrode 82 from being short-circuited by the pixel electrode material such as ITO remaining during the formation of the pixel electrode 82. In other words, by forming a deep valley, even if ITO and the like remain, it can be disconnected from this part.

Although transparent ITO has been used as an example of the material of the pixel electrode 82, an opaque conductive material may be used for the reflective liquid crystal display device.

Now, a method of manufacturing a substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 5A to 14B and FIGS. 2 to 4.

First, as illustrated in FIGS. 5A to 5C, a conductive layer such as a metal is deposited to a thickness of 1,000 kPa to 3,000 kPa by a sputtering method, and first, dry or wet etch using a mask to form a gate on the substrate 10. A gate wiring including the line 22, the gate pad 24, and the gate electrode 26 is formed.

Next, as shown in FIGS. 6A and 6C, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 are respectively 1,500 kV to 5,000 kV, 500 kV to 4,500 kV, and 300 kV using chemical vapor deposition. To 600 kPa in thickness, and then the conductive layer 60 such as metal is deposited to a thickness of 1,500 kPa to 4,000 kPa by a method such as sputtering. Subsequently, the conductor layer 60 and the intermediate layer 50 below are patterned using a second mask to form data line portions such as data lines 62, data pads 64, and source electrodes 65 and lower data line portions. The intermediate layer pattern 55, the drain electrode 66, and the conductor pattern 56 for drain electrodes thereunder are formed.

As shown in FIGS. 7A, 10A, and 10B, silicon nitride is deposited by a CVD method or spin-coated an organic insulating material to form a protective film 70 having a thickness of 2,000 2,000 or more, and then, using a third mask, the protective film 70. ) And the semiconductor layer 40 and the gate insulating film 30 are patterned to form a pattern including the contact windows 71, 72, 73 and the opening 31. To this end, photoresist patterns having different thicknesses are formed according to portions, and dry etching of lower layers is performed using the photoresist layer as an etching mask, which will be described in detail with reference to FIGS. 7B to 9B.

First, a photoresist film PR, preferably a positive photoresist film, is applied on the protective film 70 to a thickness of 5,000 kPa to 30,000 kPa, and then exposed through the third masks 300, 410, and 420. The photosensitive film PR after exposure is different from the screen display portion D and the peripheral portion P as shown in FIGS. 7B and 7C. That is, in the photosensitive film PR of the screen display unit D, the C and E portions of the portions B, C, and E exposed to the light react with light only to a certain depth from the surface to decompose the polymer, and the polymer below the polymer. Remains as it is, but all of the B portion reacts to the light and the polymer is decomposed, and the photoresist film PR of the peripheral portion P is different from the portion B exposed to the light, The polymer is decomposed. Here, the portions C, E, and B exposed to the light in the screen display unit D or the peripheral portion P are portions where the passivation layer 70 is to be removed.

For this purpose, the optical masks are aligned and exposed as shown in Figs. 7B, 7C and 8. That is, the portions C and E of the portions B, C, and E exposed to light in the screen display unit D correspond to portions in which only the transmittance adjusting film 520 of the optical mask is formed, and the portion B corresponds to the transmittance adjusting film ( 520 also corresponds to a portion not formed, and the portion B exposed to light in the peripheral portion P corresponds to a portion where the transmittance adjusting film 520 is not formed, and the portion not exposed to the remaining light. (A) corresponds to a portion where both the transmittance adjusting film 520 and the opaque film 530 are formed.

At this time, the two portions C and E exposed to light in the screen display unit D should have the same thickness of the photoresist film PR after development, but the amount of light passing through the photomask is different. That is, the transmittance adjusting film 520 is intactly formed in the portion of the photomask corresponding to the portion C, but the slit pattern or the mosaic pattern is formed in the transmittance adjusting layer 520 in the portion of the photomask corresponding to the portion E. have.

This is to prevent the photosensitive film from being formed unevenly due to the influence of the reflected light and the flattening phenomenon of the photosensitive film. That is, since the gate wiring is formed of metal to generate reflected light, when light having the same intensity is incident through the photomask, the intensity of light irradiated to the photosensitive film (E portion) corresponding to the gate wiring is increased than that of the other portion (C portion). As a result, the photoresist pattern between the C part and the E part remains with an uneven thickness. In addition, since the planarization is performed when the photoresist film is applied, the thickness of the photoresist film becomes relatively thinner than other portions in the part with convex unevenness such as the gate wiring on the upper portion of the substrate. At this time, if the light intensity is uniformly irradiated and developed, the photoresist film remains thinner than other portions in the portion corresponding to the gate wiring. Therefore, in order to make the photoresist film thicknesses of the C portion and the E portion the same, a mask having a pattern or irregularities that can slightly increase the intensity of light incident on the E portion than the C portion corresponding to the gate wiring is used. .

In addition, a method of preventing variation in the dose of light due to the reflected light by using the colored photosensitive film may also be performed in parallel.

On the other hand, the portion (C) exposed to light in the upper portion of the drain electrode 66 may cause the polymer to be decomposed only to a certain depth as in the present embodiment, but as in the portion (B) exposed to the light in the peripheral portion (P) You can also respond to light. In addition, the portion B exposed to the light on the upper portion of the data pad 64 may also react to light as in the present embodiment, but the polymer decomposes only to a certain depth like the portion C exposed to the light on the screen display. You can also

In this embodiment, a positive photoresist film is used, but a negative photoresist film in which a portion exposed to light remains after development may be used.

After exposing the photoresist film PR in this manner, the photoresist film pattern PR is formed as shown in FIGS. 9A and 9B. That is, a photosensitive film is not formed on a portion of the gate pad 24 and the data pad 64, and the data line portion is formed on all peripheral portions P and the screen display portion D except the gate pad 24 and the data pad 64. A thick photoresist film A is formed on the top of the semiconductor layer 40 between the 62, 64, 65 and the drain electrode 66, and the left and right sides of the thick photoresist film A on the data line 62. A portion B in which the photoresist film is not formed exists, and a thin photoresist film C is formed on a part of the drain electrode 66 and in the other part of the screen display part D. FIG.

At this time, the thickness of the thin portion of the photoresist film PR may be about 1/4 to 1/7 level of the initial thickness, that is, 350 to 10,000 GPa, more preferably 1,000 to 6,000 GPa.

Subsequently, etching is performed on the photoresist pattern PR and the lower layers thereof, that is, the passivation layer 70, the semiconductor layer 40, and the gate insulating layer 30 by a dry etching method.

At this time, as mentioned above, part A of the photoresist pattern PR should remain without being completely removed, and the protective film 70, the semiconductor layer 40, and the gate insulating film 30 under the B part should be removed, and C Only the passivation layer 70 and the semiconductor layer 40 may be removed under the portion, and the gate insulating layer 30 may not be removed, and only the passivation layer 70 should be removed from the upper portion of the drain electrode 66 under the portion C.

To this end, it is preferable to use a dry etching method capable of simultaneously etching the photoresist pattern PR and the films below it. That is, using the dry etching method, as shown in FIGS. 10A and 10B, the thin film is formed in three layers and the C portion of the protective film 70, the semiconductor layer 40, and the gate insulating film 30 under the B portion without the photosensitive film. The three layers of the photosensitive film, the protective film 70 and the semiconductor layer 40 can be simultaneously etched. However, in the drain electrode 66 portion of the screen display portion D and the data pad 64 portion of the peripheral portion P, the condition that the conductor layer 60 is etch-selective is selected so that the conductor layer 60 is not removed. In this case, the portion A of the photoresist pattern PR is also etched to a certain thickness.

In addition, when three layers of the thin photosensitive film, the protective film 70 and the semiconductor layer 40 are simultaneously etched in the portion C, the thin photosensitive film remains unevenly thick and has a semiconductor layer (on the top of the gate insulating film 30). A portion of 40) may remain. In order to prevent this, the photoresist pattern PR and the lower layer may be etched in several steps. This will be described in detail.

First, as shown in FIGS. 11A and 11B, etching is performed on the passivation layer 70 and the underlying layers, that is, the semiconductor layer 40 and the gate insulating layer 30, which are not covered by the photoresist pattern PR by the dry etching method. To reveal the data pad 64. In this case, the amount of the photoresist film is controlled in the dry etching condition so that the protective layer 70 is not exposed in the screen display unit D except for the portion B. FIG. Here, a portion of the gate insulating film 30 may be left on the gate pad 24 as shown in FIG. 11A, and may be completely removed. Here, the dry etching gas is used SF ₆ + N ₂ or SF ₆ + HCl.

Next, an ashing process is performed to remove the photosensitive film remaining on the upper portion of the protective film 70 in the portion C as shown in FIGS. 12A and 12B. At this time, since the photoresist film remains in an uneven thickness in the C portion, the photoresist film may remain, so that the ashing process is sufficiently performed to completely remove the photoresist film in the C portion. With a gas to remove the photoresist in the ashing process is preferably used, such as the N ₆ + O ₂ or Ar + O _2. In this case, even if the thin photoresist film of FIG. 9A and FIG. 9B is formed to have an uneven thickness, the photoresist film can be completely removed from the C portion.

13A and 13B, the passivation layer 70 and the gate insulating layer 30 exposing the photoresist pattern PR as a mask by selecting conditions having an excellent etching selectivity with respect to the semiconductor layer 40 and the passivation layer 70. ) Is removed to expose the semiconductor layer 40 in the portion where the storage capacitor is formed and the screen display unit D, and at the same time, the drain electrode 66 and the gate pad 24 are exposed. It is preferable to include a large amount of O ₂ or CF ₄ in order to make the conditions excellent in the etching selectivity with respect to the semiconductor layer 40 and the protective film 70. As the dry etching gas, it is preferable to use SF ₆ + N ₂ , SF ₆ + O ₂ , CF ₄ + O ₂ , CF ₄ + CHF ₃ + O ₂ , and the like.

Next, as shown in FIGS. 14A and 14B, the semiconductor patterns 40 are etched by etching the exposed semiconductor layer 40 by selecting conditions for etching only the amorphous silicon layer to complete the semiconductor patterns 42 and 48. At this time, as a gas for etching the amorphous silicon layer, it is preferable to use Cl ₂ + O ₂ or SF ₆ + HCl + O ₂ + Ar and the like.

Finally, the remaining photoresist pattern of the A portion is removed, and as shown in FIGS. 2 to 4, an ITO layer having a thickness of 400 to 500 Å is deposited and etched using a fourth mask to etch the pixel electrode 82. The auxiliary gate pad 84 and the auxiliary data pad 86 are formed.

In the present exemplary embodiment, the protective film is used separately and the photosensitive film is patterned. However, the protective film may be formed by using a photo-definable organic insulating film. A protective layer pattern having a different height may be formed, and the lower layers may be patterned using the protective layer pattern.

As described above, according to the present invention, the light transmittance of the optical mask can be finely decomposed in five steps by using a transparent substrate and two films having different transmittances. Simplify and increase yield.

Claims (15)

Transparent substrate, A first film formed on the substrate and having a lower light transmittance than the substrate; A second film formed on the substrate so as to overlap with the first film and having a light transmittance different from that of the first film and the substrate; In the optical mask comprising a, The substrate includes a first part completely covered with the first film, a second part having a transmittance control pattern formed therein, and a third part having the first film removed therefrom, And the second film is formed only on a specific portion of the substrate. In claim 1, And the second film is formed only on a specific portion of the first portion. In claim 2, The substrate has a light transmittance of 90% or more with respect to the exposure light, the second film has a light transmittance of 3% or less with respect to the exposure light, and the first film has a light transmittance of 20% to 40% with respect to the exposure light. Photomask. In claim 1, The transmittance adjustment pattern is an optical mask that is a slit pattern. In claim 1, The second film is an optical mask including a portion where the transmittance adjustment pattern is formed. In claim 5, The second film is formed on only a part of the first portion of the photomask, In claim 5, The transmittance adjustment pattern is an optical mask that is a slit pattern. Forming a gate line including a gate line and a gate electrode of the screen display unit and a gate pad of the peripheral unit on an insulating substrate including a screen display unit and a peripheral unit; Forming a gate insulating layer pattern not covering at least a portion of the gate pad and covering the substrate and the gate wiring of the screen display unit; Forming a semiconductor layer pattern on the gate insulating layer pattern; Forming a contact layer pattern on the semiconductor layer pattern, Forming a data line on the contact layer pattern, the data line including a data line, a source electrode, a drain electrode, and a data pad of the peripheral part; Forming a protective insulating pattern having a first contact hole exposing the drain electrode on the data line; Forming a pixel electrode connected to the drain electrode through the first contact hole on the protective insulating layer Including; The gate insulating layer pattern may be formed using a photosensitive layer pattern having a different thickness according to a portion, and among the semiconductor layer pattern, the contact layer pattern, the data line, the protective insulating layer pattern, and the pixel electrode in an etching process using the photosensitive layer pattern. Formed with at least one, A method of manufacturing a thin film transistor substrate for a liquid crystal display device, wherein the photosensitive film patterns having different thicknesses are formed using the photomask of claim 2. In claim 8, In the process of forming the photoresist pattern, the photomask has a portion where the second layer is formed corresponding to the peripheral portion and the data line, the second portion corresponds to the gate line, and the third portion corresponds to the gate. And a pad, the data pad and the pixel electrode and the data line to be aligned to correspond to a predetermined portion. In claim 9, The substrate has a light transmittance of 90% or more with respect to the light for exposure, the second film has a light transmittance of 3% or less with respect to the light for exposure, and the first film has a light transmittance of 20% to 40% with respect to the light for exposure. Photomask. In claim 8, The transmittance adjustment pattern is an optical mask that is a slit pattern. In claim 8, The photoresist pattern has a first portion, a second portion thicker than the first portion, and a third portion thicker than the second portion, wherein the first portion is positioned above the gate pad, and the second portion is the screen display portion. The manufacturing method of the thin-film transistor board | substrate for liquid crystal display devices located in the. In claim 12, The photoresist pattern is formed on the protective insulating layer, Forming the gate insulating film pattern, the semiconductor layer pattern and the protective insulating film pattern Etching the second insulating portion while etching the protective insulating film and the semiconductor layer under the first portion through a single etching process; Removing the second portion through an ashing process to expose the protective insulating layer underneath; Etching the protective insulating layer and the gate insulating layer using the photoresist pattern as a mask to expose the semiconductor layer under the second portion and to form a second contact hole exposing the gate pad under the first portion; , Removing the semiconductor layer from the second portion using the photoresist pattern as a mask Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. Insulation board, A gate wiring including a gate pad, a gate electrode, and a gate line formed on the substrate; A gate insulating layer formed on the gate line and having a first contact hole exposing the gate pad and an opening exposing at least a portion of the substrate in the pixel region; A semiconductor layer pattern formed on the gate insulating film, A contact layer pattern formed on the semiconductor layer, A data line including a data line, a data pad, a source electrode, and a drain electrode having a shape substantially the same as that of the contact layer pattern; A protective film pattern having a shape substantially the same as that of the semiconductor layer pattern except for a second contact hole exposing the data pad and a third contact hole exposing the drain electrode; A pixel electrode electrically connected to the drain electrode through the third contact hole and formed in the pixel region in direct contact with at least a portion of the gate insulating layer pattern; An auxiliary data pad and an auxiliary gate pad in contact with the data pad and the gate pad, respectively. Thin film transistor substrate comprising a. The method of claim 14, And the opening exposes the substrate between the data line and the pixel electrode.