KR100623975B1 - Photolithographic etching method of a thin film and manufacturing methods of a thin film transistor array panel for a liquid crystal display using the same - Google Patents

Abstract

A method of manufacturing a liquid crystal display device which reduces the number of masks. On the substrate including the screen display unit and the periphery, a gate line including a gate line and a gate electrode of the screen display unit and a gate pad of the periphery is formed, and a gate insulating film, a semiconductor layer, an intermediate layer, and a conductor layer are successively deposited, and then the conductor layer and the intermediate layer. Patterning to form a data line including a data line and a source / drain electrode of the screen display unit and a data pad of the peripheral portion, and an intermediate layer pattern below the data line. A protective film made of a photosensitive organic insulating material is coated on the data line and the source / drain electrodes. Light is irradiated onto the passivation layer through at least one mask having a different transmittance of the screen display unit and a transmittance of the peripheral unit, and then developed to form a passivation layer pattern having a different thickness. Here, the protective film pattern of the screen display part is composed of a thin part and a thick part, and the protective film pattern of the peripheral part is composed of a thick part and a no part. The dry etching method removes a portion without a protective layer from the periphery, that is, a semiconductor layer on the gate pad, and at the same time between the source and drain electrodes and a portion covering the data wiring except a portion of the thicker layer, that is, the drain electrode, in the screen display part. The protective film of the portion covering the top layer is removed, and the thin protective film of the remaining portion and the semiconductor layer below it are removed. Finally, the pixel electrode, the auxiliary gate pad, and the auxiliary data pad are formed.

Liquid Crystal Display, Thin Film Transistor Board, Photosensitive Organic Insulator, Photo Etching, Mask

Description

Photolithographic etching method of thin film and manufacturing method of thin film transistor substrate for liquid crystal display device using the same.

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

2 and 3 are cross-sectional views of the thin film transistor substrate shown in FIG. 1 taken along lines II-II 'and III-III';

4A is a layout view of a thin film transistor substrate in a first step of manufacturing in accordance with an embodiment of the invention,

4B and 4C are cross-sectional views taken along the lines IVb-IVb 'and IVc-IVc' in FIG. 4A, respectively.

5A is a layout view of a thin film transistor substrate in the next step of FIGS. 4A to 4C;

5B and 5C are cross-sectional views taken along the lines Vb-Vb 'and Vc-Vc' in FIG. 5A, respectively.

6A is a layout view of a thin film transistor substrate in the next step of FIGS. 5A to 5C;

6B and 6C are cross-sectional views taken along lines VIb-VIb 'and VIc-VIc' in FIG. 6A, respectively.

7A and 7B, FIGS. 8A and 8B and 9 are cross-sectional views illustrating the structure of the photomask used in the steps of FIGS. 6A to 6C, respectively.

10A and 10B are cross-sectional views taken along the lines VIb-VIb 'and VIc-VIc' in FIG. 6A, respectively, and are cross-sectional views of the next steps of FIGS. 6B and 6C.

11A and 11B are cross-sectional views taken along the lines VIb-VIb 'and VIc-VIc' in FIG. 6A, respectively, and are cross-sectional views taken along the steps of FIGS. 10A and 10A.

The present invention relates to a method of etching a thin film and a method of manufacturing a thin film transistor substrate for a liquid crystal display device using the same.

In general, a liquid crystal display device is composed of two substrates, and two or more kinds of electrodes for generating an electric field are formed on one or both of the substrates to display an image by adjusting a voltage applied to the electrodes.

Among the two substrates, the thin film transistor substrate for a liquid crystal display device has a basic structure of a thin film transistor formed on the substrate and a pixel electrode controlled by the same, as in Korean Patent Application No. 95-189.

As in this patent application, a thin film transistor substrate is manufactured through film formation and photolithography processes of a thin film over several layers, and photolithography recovery represents a number of manufacturing processes. Therefore, how stable a device is formed through a small number of photolithography processes is an important factor in determining the manufacturing cost, as also shown in the aforementioned No. 95-189.

Here, referring to the conventional method of manufacturing a thin film transistor substrate, a gate wiring is formed by first depositing a gate metal on an insulating substrate and patterning using a first mask, and forming a gate insulating film, an amorphous silicon layer, and a doped amorphous silicon layer. After depositing successively and patterning the doped amorphous silicon layer and the amorphous silicon layer using a second mask at the same time to form a semiconductor pattern, the data metal is deposited and patterned using a third mask to form a data line. Subsequently, the resistive contact layer is formed by etching the doped amorphous silicon layer using the data wiring as an etch stop layer, and after the protective film is deposited, the pad electrode of the drain electrode, the gate line, and the data line is exposed to the protective film using a fourth mask. To form a contact hole. Finally, indium tin oxide (ITO) or the like is deposited and patterned using a fifth mask to form a pixel electrode.

As described above, in the conventional method of manufacturing a thin film transistor substrate, it is generally required to perform five photo etching processes. For the photo etching of a certain thin film, a photoresist pattern is formed on the thin film to be etched and the lower thin film is formed as an etch blocking layer. Etch Such a large number of photo etching times and complicated photo etching methods increase the production cost of the liquid crystal display.

The technical problem to be achieved by the present invention is to propose a new photolithography method of thin film.

Another object of the present invention is to simplify the manufacturing process of a thin film transistor substrate for a liquid crystal display device, thereby lowering the manufacturing cost and increasing the yield.

In order to solve this problem, in the present invention, the protective film is formed of a photosensitive material, and patterned to have a different thickness depending on the position through exposure and development, and the protective film and the film under the same are etched simultaneously.

Specifically, a gate wiring including a gate line and a gate electrode of the screen display portion and a gate pad of the peripheral portion is formed on a substrate including the screen display portion and the peripheral portion, and a gate insulating film, a semiconductor layer, a contact layer, and a conductor layer are formed on the gate wiring. Is deposited continuously. The conductor layer and the contact layer are photo-etched to form a data line including a data line, a source and drain electrode of the screen display unit, and a data pad of the peripheral portion, and a contact layer pattern under the contact layer pattern.

 A protective film made of a photosensitive organic insulator is stacked thereon, and the protective film is exposed and developed by using a first photomask for patterning the screen display unit and a second photomask for forming a peripheral portion having a different light transmittance from the first photomask. A protective film having a different thickness is formed. A first contact window for patterning the protective insulating layer and the semiconductor layer below the screen display unit through the etching process to form a protective layer pattern and a semiconductor layer pattern, and at the same time patterning the protective insulating layer, semiconductor layer and the gate insulating layer in the peripheral portion to expose the gate pad To form. Finally, a pixel electrode electrically connected to the drain electrode is formed.

The forming of the passivation layer, the semiconductor layer, and the first contact window by etching the passivation layer and the lower layer may include a first etching step of patterning the peripheral semiconductor layer and the gate insulating layer to expose the gate pad, and a passivation layer having a different thickness. It may include an ashing step of removing the portion thinner than the other portion of the second etching step and removing the semiconductor layer exposed through the ashing step.

At this time, the protective film can be formed of an organic insulator having positive photosensitivity.

Each of the first and second photomasks includes a substrate and an opaque pattern layer formed on the substrate and a pellicle formed on the substrate not covered with at least the pattern layer, wherein the difference in transmittance between the first and second photomasks is It can be adjusted by adjusting the transmittance of the pellicle of the first and second photomask.

The first and second photomasks form one mask, and the mask may form two pattern layers having different heights to give a difference in transmittance. In addition, the transmittance difference can be adjusted by forming a slit or a lattice-like fine pattern having a size equal to or less than the resolution of the light source used for exposure.

In the method for patterning a thin film according to the present invention, two or more thin films including a top layer made of a photosensitive organic insulator are formed on a substrate, and the top layer is exposed through a photomask having a light transmittance separated by at least three stages, and then developed and positioned. Depending on the thickness should be different. Next, the uppermost layer is etched at the same time as the thin film at the bottom thereof, and then another thin film is laminated on the uppermost layer and photo-etched to form a pattern of the other thin film.

Here, the etching of the uppermost layer and the lower layer at the same time may include the first step of etching the lower layer exposed through the portion where the uppermost layer is completely removed, the ashing step of removing the thinner part than the other part among the uppermost layers having different thicknesses; And a second etching step of removing the lower layer exposed through the ashing step.

In this case, the protective film may be formed of an organic insulator having positive photosensitivity, and in the step of simultaneously etching the uppermost layer and the lower film, it is preferable to use dry etching.

First, the structure of the thin film transistor for liquid crystal display according to the exemplary embodiment of the present invention will be described with reference to the drawings.

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 2 and 3 are cut along the II-II 'line and the III-III' line of FIG. 1. It is sectional drawing.

Gate wiring made of a metal or a conductor such as aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta) or the like on the insulating substrate 10 Formed. The gate wiring is connected to a scan signal line or gate line 22 extending in the horizontal direction, a gate pad 24 connected to an end of the gate line 22 to receive a scan signal from the outside, and to transfer the scan signal to the gate line 22. The gate electrode 26 of the thin film transistor that is part of the gate line 22 is included.

The gate wirings 22, 24, and 26 may be formed in a single layer, but may also be formed in a double layer or a triple layer. In the case of forming more than two layers, it is preferable that one layer is formed of a material having a low resistance and the other layer is formed of a material having good contact properties with other materials, and a double layer of Cr / Al (or Al alloy) or Al / Mo Bilayers are an example.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate wirings 22, 24, and 26 to cover the gate wirings 22, 24, and 26.

Semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed on the gate insulating layer 30, and high concentrations of n-type impurities such as phosphorus (P) are formed on the semiconductor patterns 42 and 48. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon doped with is formed.

On the contact layer patterns 55, 56, and 58, a data line made of a conductive material such as Mo or MoW alloy, Cr, Al or Al alloy, and Ta is formed. The data line is a thin film transistor which is a branch of the data line 62 formed in the vertical direction, the data pad 64 connected to one end of the data line 62 to receive an image signal from the outside, and the data line 62. A drain electrode of the thin film transistor including a data line portion formed of the source electrode 65 of the thin film transistor, and separated from the data line portions 62, 64, and 65 and positioned opposite to the source electrode 65 with respect to the gate electrode 26. Also included is a conductor pattern 68 for a storage capacitor which is positioned over the 66 and the gate line 22. The conductive pattern 68 for the storage capacitor is connected to the pixel electrode 82 to be described later to form a storage capacitor. However, the conductive capacitor pattern 68 for the storage capacitor may not be formed if the storage capacitor of sufficient size can be obtained only by the superposition of the pixel electrode 82 and the gate line 22.

The data lines 62, 64, 65, 66, and 68 may be formed in a single layer like the gate lines 22, 24, and 26, but may be formed in a double layer or a triple layer. Of course, when forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials.

The contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has exactly the same form as (62, 64, 65, 66, 68). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 64 and 65, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor pattern 68 for holding capacitors.

On the other hand, the semiconductor patterns 42 and 48 have a shape similar to that of the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 57. Specifically, the semiconductor capacitor pattern 48 for the storage capacitor has the same shape as the conductor pattern 68 for the storage capacitor and the contact layer pattern 58 for the storage capacitor, but the semiconductor pattern 42 for the thin film transistor has a data wiring and Different from the rest of the contact layer pattern. That is, the data line parts 62, 64, 65, in particular, the source electrode 65 and the drain electrode 66 are separated from the channel portion C of the thin film transistor, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode is separated. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor. On the other hand, the semiconductor pattern 42 also extends to the periphery and is formed over the entire periphery.

The data line portions 62, 64, and 65, the drain electrode 66, and the semiconductor pattern 42 are covered by the passivation layer 70, and the passivation layer 70 exposes a contact window exposing the drain electrode 66 and the data pad 64. Has (71, 73). The passivation film 70 also has a contact window 72 exposing the gate pad 24 together with the gate insulating film 30 and the semiconductor pattern 42, and a portion of the gate line 22 overlapping the data line 62. Except for the rest is not covered. The passivation layer 70 is formed of a photosensitive organic insulating material, for example, a product code PC 403 supplied by JSR of Japan, and at least between the source electrode 65 and the drain electrode 66 of the semiconductor pattern 42. It protects the channel part located.

The pixel electrode 82 is formed on the gate insulating film 30 in the region surrounded by the gate line 22 and the data line 62. The pixel electrode 82 is physically and electrically connected to the drain electrode 66 through the contact window 71 to receive an image signal from the thin film transistor to generate an electric field together with the electrode of the upper plate, and to form an indium tin oxide (ITO). Made of transparent conductive material The pixel electrode 82 also extends over the conductor pattern 68 for the storage capacitor and is physically and electrically connected so that the conductor pattern 68 for the storage capacitor and the gate line 22 and the storage capacitor thereunder are provided. To achieve. On the other hand, an auxiliary gate pad 84 and an auxiliary data pad 86 connected to the gate pad 24 and the data pad 64 through the contact windows 72 and 73, respectively, are formed. , 64) and to protect the pads and the adhesion of the external circuit device, it is not essential, and their application is optional.

Although transparent ITO has been used as an example of the material of the pixel electrode 82, an opaque conductive material may be used for the reflective liquid crystal display device.

Next, a method of manufacturing a substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 4A to 11B and FIGS. 1 to 3.

First, as shown in FIGS. 4A to 4C, a conductive layer such as a metal is deposited to a thickness of 1,000 kPa to 3,000 kPa by a sputtering method, and then dry or wet etched using a first mask, onto the substrate 10. A gate wiring including a gate line 22, a gate pad 24, and a gate electrode 26 is formed.

5A to 5C, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 are respectively 1,500 kV to 5,000 kV, 500 kV to 1,500 kV, 300 using chemical vapor deposition. Continuous deposition is carried out to a thickness of Å to 600 Å, and then the conductor layer 60 such as metal is deposited to a thickness of 1,500 Å to 3,000 Å by sputtering or the like. Subsequently, the conductor layer 60 and the intermediate layer 50 below are patterned using a second mask to form data line portions such as data lines 62, data pads 64, and source electrodes 65 and lower data line portions. The intermediate layer pattern 55, the drain electrode 66, the conductor pattern 56 for drain electrodes in the lower part, the conductor pattern 68 for sustain capacitors, and the intermediate layer pattern 58 for sustain capacitors in the lower part are formed.

As shown in FIGS. 6A, 11A, and 11B, after the photosensitive organic insulating material is spin-coated to form the protective film 70, the protective film 70, the semiconductor layer 40, and the gate insulating film are formed using a third mask. 30 is patterned to form their pattern including the contact window. At this time, the peripheral portion P removes the passivation layer 70, the semiconductor layer 40, and the gate insulating layer 30 on the gate pad 24 (also removes the passivation layer 70 on the data pad 64). In (D), only the protective film 70 and the semiconductor layer 40 are removed (the protective film 70 on the drain electrode 66 is also removed). The semiconductor layer pattern must be formed so that a channel is formed only in a necessary portion. To this end, the protective film 70 itself is formed to have a different thickness according to a portion through an exposure and development process, and then the lower film including the protective film 70 is etched, which will be described in detail with reference to FIGS. 6B to 11B. .

First, a protective film 70 is laminated by applying a photosensitive organic insulating material, for example, a product code PC 403 supplied by JSR of Japan in a thickness of 5,000 kPa to 30,000 kPa, and then stacking the protective film 70. Exposure through). The protective film 70 after exposure is different from the screen display portion D and the peripheral portion P, as shown in FIGS. 6A and 6B. That is, the portion C of the passivation layer 70 of the screen display unit D exposed to light reacts with light only to a certain depth from the surface to decompose the polymer, and the polymer remains under the periphery P. Unlike the protective film 70, the portion B exposed to light is in a state in which the polymer is decomposed in response to light. Here, portions C and B exposed to light in the screen display unit D or the peripheral portion P are portions where the protective film 70 is to be removed.

To this end, a method of changing the structure of the mask 300 used for the screen display unit D and the masks 410 and 420 used for the peripheral portion P may be used. Here, three methods are presented.

As shown in FIGS. 7A and 7B, the masks 300 and 400 are typically opaque pattern layers 320 and 420 consisting of the substrates 310 and 410 and chromium thereon, and the pattern layers 320 and 420. ) And the pellicles 330 and 430 covering the exposed substrates 310 and 410, and the light transmittance of the pellicle 330 of the mask 300 used for the screen display unit D is the peripheral portion P. FIG. ) Is lower than the light transmittance of the pellicle 430 of the mask 400. The transmittance of the pellicle 330 is preferably in the range of 10% to 80%, preferably 20% to 60% of the transmittance of the pellicle 430.

Next, as shown in FIGS. 8A and 8B, the mask 300 of the screen display unit D is left with a chromium layer 350 in a thickness of about 100 kPa to 300 kPa over the entire surface to lower the transmittance, and the peripheral portion ( The mask 400 of P) does not leave such a chromium layer. In this case, the pellicle 340 of the mask 300 used in the screen display unit D may have the same transmittance as the pellicle 430 of the peripheral portion P. FIG.

Of course, the above two methods can be used in combination.

In the above two examples, it is applicable to the split exposure using a stepper, and is possible because the screen display unit D and the peripheral portion P are exposed using different masks. In the case of the divided exposure in this manner, the thickness can be adjusted by changing the exposure time of the screen display unit D and the peripheral portion P.

However, the screen display unit D and the periphery unit P may be exposed using one mask without being dividedly exposed. In this case, a structure of a mask that can be applied will be described in detail with reference to FIG. 9.

As shown in FIG. 9, a transmittance control film 550 is formed on the substrate 510 of the mask 500, and a pattern layer 520 is formed on the transmittance control film 550. The transmittance adjusting film 550 is formed not only under the pattern layer 520 but also over the entire surface in the screen display unit D, but is formed only under the pattern layer 550 in the peripheral portion P. As a result, two or more patterns having different heights are formed on the substrate 510.

Of course, the periphery portion P may also have a transmittance adjusting film. In this case, the transmittance of the transmittance adjusting film of the peripheral portion P should have a transmittance higher than that of the transmittance adjusting film 550 of the screen display portion P.

When manufacturing the photomask 500 having the transmittance control film 550, first, a transmittance control film 550 and a pattern layer 520 having an etching ratio different from that of the transmittance control film 550 are formed on the substrate 500. Laminate in succession. After the photoresist (not shown) is applied, exposed and developed over the entire surface, the pattern layer 520 is etched using the photoresist as an etch mask. After removing the remaining photoresist film, a new photoresist pattern (not shown) is formed to expose the transmittance control film at a position corresponding to the contact window of the peripheral portion P. Then, the transmittance control film 550 is etched using this as an etching mask. By doing so, the optical mask 500 is completed.

In addition to the above method, the transmittance may be adjusted by using a mask having a slit or a lattice-like fine pattern having a size smaller than the resolution of the light source.

However, a portion of the passivation layer 70 having a highly reflective metal layer, that is, the gate wirings 22, 24, 26 or the data wirings 62, 64, 65, 66, 68, may be different during exposure due to the reflected light. The amount of light may be higher than that of the part. In order to prevent this, there may be a layer for blocking the reflected light from the bottom.

After exposing the protective film 70 which is the photosensitive organic insulating material in this manner, and developing, the protective film 70 pattern as shown in FIGS. 10A and 10B is formed. That is, the passivation layer 70 is completely removed on a portion of the gate pad 24, the data pad 64, and the drain electrode 66, and all peripheral portions P except for the gate pad 24 and the data pad 64 are formed. A thick protective film A is formed on the upper portion of the semiconductor layer 40 between the data line portions 62, 64, 65 and the drain electrode 66 in the screen display portion D, and other portions of the screen display portion D. The thin protective film B is formed in this.

At this time, the thickness of the thin portion of the protective film 70 may be about 1/4 to 1/7 of the initial thickness, that is, 350 to 10,000 Å, more preferably 1,000 to 6,000 Å. For example, the initial thickness of the protective film 70 may be 16,000 kPa to 24,000 kPa, and the thickness of the thin protective film may be 3,000 kPa to 7,000 kPa by setting the transmittance of the screen display unit D to 30%. However, since the thickness to be left must be determined according to the dry etching process conditions, the thickness of the pellicle of the mask, the residual chromium layer, or the transmittance or exposure time of the transmittance control film must be adjusted according to the process conditions.

Such a thin protective film may be formed through reflow after exposing and developing the protective film in a conventional manner. In addition, the above description is based on the premise that the protective film is positive photosensitive, but may be applied to a case having negative photosensitive. That is, in the case where the protective film is negative photosensitive, the portion where the protective film should be completely removed should not be exposed to light, the exposure amount may be decreased in the portion where the protective film is to be thinned, and the exposure amount may be increased in the portion where the protective film is thick.

Subsequently, the protective layer 70 and the underlying layers, that is, the semiconductor layer 40 and the gate insulating layer 30 are etched by a dry etching method.

At this time, as mentioned above, the portion A of the passivation layer 70 must remain without being completely removed, the semiconductor layer 40 and the gate insulating layer 30 of the portion B must be removed, and the passivation layer 70 under the portion C Only the semiconductor layer 40 and the gate insulating layer 30 should not be removed.

To this end, it is preferable to use a dry etching method capable of simultaneously etching the passivation layer 70 and the lower layer. That is, when the dry etching method is used, as shown in FIGS. 11A and 11B, two layers of the semiconductor layer 40 and the gate insulating layer 30 below the portion B without the protective layer 70 and the portion C of the gate layer 30 have a thin thickness. Two layers of the protective film 70 and the semiconductor layer 40 can be etched at the same time. However, the conductive layer 60 is not removed from the drain electrode 66 portion of the screen display unit D, the data pad 64 portion of the peripheral portion P, and the portion where the conductive capacitor conductive pattern 68 is to be formed. A condition having an etching selectivity with respect to the conductor layer 60 should be taken. In this case, the portion A of the passivation layer 70 is etched to a certain thickness.

Accordingly, only one passivation layer 70 and the semiconductor layer 40 are removed from the screen display unit D by using a single mask process and a dry etching method to form the contact window 71 and the semiconductor patterns 42 and 48. In P), all of the passivation layer 70, the semiconductor layer 40, and the gate insulating layer 30 may be removed to form the contact windows 72 and 73.

If the dry etching condition used above is not sufficient for the protective film 70, the process of ashing the protective film 70 under an etching condition having a sufficient etching rate for the protective film 70 is described above. Dry Etching Process In addition to the next step, the protective film 70 of the C portion is completely removed, and the etching is performed to remove the semiconductor layer 40 of the C portion.

Finally, as shown in FIGS. 1 to 3, an ITO layer having a thickness of 400 μs to 500 μs is deposited and etched using a fourth mask to form the pixel electrode 82, the auxiliary gate pad 84, and the auxiliary data pad. Form 86.

As described above, in the present exemplary embodiment, the contact window 72 exposing the gate pad 24 is formed by using a mask together with the passivation pattern 70 and the semiconductor patterns 42 and 48. 72 may also be formed together when patterning other films, which are within the scope naturally conceivable to one skilled in the art. In particular, the present invention is a particularly effective method for patterning a thin film etched by a dry etching method.

In addition, in the present embodiment, a case where the pixel electrode of a wide surface shape is present is illustrated, but the pixel electrode may be formed in a line shape, and the common electrode for driving the liquid crystal molecules together with the pixel electrode is formed on the same substrate as the pixel electrode. It may be formed.

As described above, the present invention reduces the manufacturing process number of the thin film transistor substrate for the liquid crystal display device through a new photolithography method of the thin film, and simplifies the process to lower the manufacturing cost and increase the yield. In particular, the process can be greatly simplified by patterning the film without an etching process and using the film itself to be patterned as an etch stop layer for patterning the underlying film.

Claims (10)

Forming a gate line including a gate line and a gate electrode of the screen display unit and a gate pad of the peripheral unit on a substrate including a screen display unit and a peripheral unit; Continuously depositing a gate insulating film, a semiconductor layer, a contact layer, and a conductor layer on the gate wiring; Photo-etching the conductor layer and the contact layer to form a data line including a data line, a source and a drain electrode of the screen display unit, and a data pad of the periphery, and a contact layer pattern thereunder; Laminating a protective film made of a photosensitive organic insulator, Exposing the passivation layer using a first photomask for patterning the screen display unit and a second photomask having a different light transmittance from the first photomask and forming the peripheral portion; Developing the protective film to form a protective film having a different thickness; The gate pad is formed by patterning the passivation layer and the semiconductor layer under the screen display unit through an etching process to form a passivation layer pattern and a semiconductor layer pattern, and patterning the passivation layer, the semiconductor layer and the gate insulation layer of the peripheral portion. A patterning step of forming an exposed first contact window, Forming a pixel electrode electrically connected to the drain electrode Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. In claim 1, The patterning step may include a first etching step of patterning the semiconductor layer and the gate insulating layer of the periphery to expose the gate pad, an ashing step of removing a portion having a thickness smaller than another portion of the passivation layer having a different thickness, and the ashing step. And a second etching step of removing the semiconductor layer exposed through the thin film transistor substrate. The method of claim 1 or 2, The said protective film is a manufacturing method of the transistor substrate for liquid crystal display devices which consists of an organic insulator which has positive photosensitivity. The method of claim 1 or 2, The first and second photomasks each include a substrate, an opaque pattern layer formed on the substrate, and a pellicle formed on the substrate not covered with at least the pattern layer, wherein the first and second photomasks The method of manufacturing a thin film transistor substrate for a liquid crystal display device, wherein the transmittance difference is controlled by adjusting transmittances of pellicles of the first and second photomasks. The method of claim 1 or 2, The first and second photomasks form a mask, and the mask includes a substrate, a first pattern layer formed on the substrate, and a second pattern layer formed on the substrate and having a different height from the first pattern layer. And a difference in transmittance between the first and second photomasks due to a height difference between the first and second pattern layers. In claim 1, The method of manufacturing a thin film transistor substrate for a liquid crystal display device, wherein the difference in transmittance between the first and second photomasks is controlled by forming a slit or a lattice-like fine pattern having a size equal to or less than the resolution of the light source used for the exposure. Forming at least two thin films on the substrate, including a top layer of photosensitive organic insulator, Exposing the top layer through an optical mask having a light transmittance separated by at least three steps; Developing the uppermost layer to form a pattern having a different thickness according to a position; The uppermost layer and the thin film of the lower part thereof are simultaneously etched to remove the portion of the uppermost layer and the lower layer from which all of the uppermost layer is removed, the uppermost layer is removed, and the lower portion of the lower layer is partially removed, and the uppermost layer and the lower layer are not removed. To make the part appear, Stacking and photo-etching another thin film on the top layer Patterning method of a thin film comprising a.  In claim 7, Etching the uppermost layer and the lower layer simultaneously may include a first step of etching the lower layer exposed through the portion from which the uppermost layer is completely removed, and ashing removing the thinner portion of the uppermost layer having a different thickness. And a second etching step of removing the lower layer exposed through the ashing step. In claim 7 or 8, The protective film is a thin film patterning method comprising an organic insulator having positive photosensitivity. In claim 7 or 8, Simultaneously etching the uppermost layer and the film below the thin film using dry etching.

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