KR100333978B1 - Manufacturing method of thin film transistor substrate for liquid crystal display device - Google Patents

Abstract

A method of manufacturing a liquid crystal display device which reduces the number of masks. On the substrate including the screen display unit and the periphery, a gate line including the gate line and the gate electrode of the screen display unit and the gate pads of the periphery are formed, successively depositing a gate insulating film, a semiconductor layer, and a silicide layer, and then depositing a positive photoresist film thereon. Apply. The photosensitive film is irradiated with light through one or more masks having different transmittances of the screen display part and transmittance of the peripheral part, and then developed to form a photosensitive film pattern having a different thickness. Here, the photoresist pattern of the screen display unit is composed of a thin portion and a thick portion, and the photoresist pattern of the peripheral portion is composed of a thick portion and a portion without a thickness. By using the dry etching method, the portion where there is no photoresist film on the peripheral portion, that is, the silicide layer, the semiconductor layer, and the gate insulation film on the gate pad are removed, and the protective film on the portion where the photoresist film is formed on the screen display portion, that is, the semiconductor pattern is to be formed, The remaining thin photoresist layer and the silicide layer and semiconductor layer underneath are removed. After successively laminating and patterning the ITO layer and the conductor layer, the exposed silicide layer is removed. A protective film is deposited and patterned to expose the gate pads, data pads and pixel electrodes, then the top conductor layer of the exposed portions is removed.

Description

Manufacturing method of thin film transistor substrate for liquid crystal display device

The present invention relates to a method for manufacturing a thin film transistor substrate for a liquid crystal display device.

In general, a liquid crystal display device is composed of two substrates, and two or more kinds of electrodes for generating an electric field are formed on one or both of these substrates to display an image by adjusting a voltage applied to the electrodes. Among liquid crystal display devices, controlling an image signal according to a scanning signal using a switching element such as a thin film transistor is widely used.

The thin film transistor substrate in which the thin film transistor is formed among the two substrates includes a thin film transistor, a pixel electrode controlled by the thin film transistor, a wiring for transmitting a signal to the thin film transistor, and a pad connecting the wiring and an external driving circuit. The common electrode, which generates the electric field together with the pixel electrode, is formed on the thin film transistor substrate or another substrate facing away.

A thin film transistor substrate is manufactured by repeatedly forming a thin film and patterning it by a photolithography method. The number of photolithography is an important factor determining the manufacturing cost, and photolithography in a manufacturing method which is mainly used recently. The number of times is five times.

As an example of the prior art, A TFT Manufactured by 4 Masks Process with New Photolithography (Chang Wook Han et al., Proceedings of The 18th International Display Research Conference Asia Display 98, p. 1109-1112, 1998. 9.28-10.1) (hereinafter " A method of manufacturing a thin film transistor using four masks including a mask in which a grid-shaped pattern is engraved on an "Asian display" is described. However, since there is no mention of a process for the entire thin film transistor substrate including the pad, it is not known how and how many masks the whole thin film transistor substrate is manufactured. In addition, it is common to form a storage capacitor in order to preserve the voltage applied to the pixel for a long time. The storage capacitor is made by superposing a pixel electrode formed on a protective film and a storage capacitor electrode made of the same layer as the gate electrode and the gate line. However, since the storage capacitor electrode is covered with the gate insulating film, the semiconductor layer, and the protective film, and the pixel electrode is formed directly on the substrate without the lower gate insulating film, in order to overlap the pixel electrode with the storage capacitor electrode, the pixel electrode is directly over the substrate. Must be placed directly on the three-layer film consisting of a gate insulating film, a semiconductor layer and a protective film. Then, there is a possibility that the step becomes severe and a disconnection occurs. In addition, since the area that can be processed as a grid mask is limited, it is difficult to process a wide range of areas, even if it can be diarrhea, even if it can be processed to have a uniform etching depth as a whole.

In addition, U.S. Patent Nos. 4,231,811, 5,618,643, 4,415,262, and Japanese Patent Laid-Open No. 61-181130 are also exposed by using a grid optical mask or by varying the transmittance by adjusting the thickness of the photomask. Ion implantation and thin film etching methods using the thickness difference of the formed photosensitive film are known, but these also have the same problem.

Another object of the present invention is to simplify the manufacturing process of a thin film transistor substrate for a liquid crystal display device.

1 is a diagram illustrating regions of a substrate for forming a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a layout view schematically illustrating devices and wirings formed on a thin film transistor substrate for one liquid crystal display according to an exemplary embodiment of the present invention.

3 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention, and is an enlarged view of one pixel and pads in FIG. 2.

4 and 5 are cross-sectional views of the thin film transistor substrate shown in FIG. 3 taken along lines IV-IV 'and V-V'.

6A is a layout view of a thin film transistor substrate at a first stage of manufacture in accordance with an embodiment of the invention,

6B and 6C are cross-sectional views taken along lines VIb-VIb 'and VIc-VIc' in FIG. 6A, respectively.

FIG. 7A is a layout view of a thin film transistor substrate in the following steps of FIGS. 6A to 6C;

7B and 7C are cross-sectional views taken along the lines 'b-'b' and 'c-'c' in FIG. 7A, respectively.

8A and 8B, 9A and 9B and 10 are cross-sectional views showing the structure of the photomask used in the steps of FIGS. 7A to 7C, respectively.

11A and 11B are cross-sectional views taken along the lines 'b-'b' and 'c-'c' in FIG. 7A, respectively, and are cross-sectional views at the next steps of FIGS. 7B and 7C;

12A is a layout view of a thin film transistor substrate in the next step of FIGS. 11A to 11B;

12B and 12C are cross-sectional views taken along the lines XIIb-XIIb 'and XIIc-XIIc' in FIG. 12A, respectively;

13 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention;

14 and 15 are cross-sectional views of the thin film transistor substrate illustrated in FIG. 3 taken along lines XIV-XIV 'and XV-XV',

16A is a layout view of a thin film transistor substrate at a first stage of manufacture in accordance with an embodiment of the invention,

16B and 16C are cross-sectional views taken along the lines XVIb-XVIb 'and XVIc-XVIc' of FIG. 16A, respectively;

17A is a layout view of a thin film transistor substrate at a next stage of FIGS. 16A to 16C,

17B and 17C are cross-sectional views taken along the lines X′b-X′b ′ and X′c—X′c ′ in FIG. 17A, respectively.

18A is a layout view of a thin film transistor substrate in the next step of FIGS. 17A to 17C.

18B and 18C are cross-sectional views taken along the lines X′b-X′b ′ and X′c—X′c ′ in FIG. 17A, respectively.

In order to solve the above problem, the present invention patterns the contact window exposing the gate pad together with at least one other thin film.

According to the present invention, a gate line including a gate line and a gate electrode of the screen display part and a gate pad of the peripheral part is formed on a substrate including the screen display part and the peripheral part, and a gate insulating film pattern is formed thereon. After forming a semiconductor layer pattern on the gate insulating film pattern, and forming a contact layer pattern thereon, a data line including a data line, a source and a drain electrode, and a data pad of the peripheral portion of the screen display is formed thereon. A channel passivation layer pattern is formed and a pixel electrode connected to the drain electrode is formed. Here, in the step of forming the gate insulating film pattern, the first photomask and the first photomask for patterning the screen display part are different from each other, and the second photomask is exposed using the second photomask for patterning the peripheral part. It is formed in one etching process together with the layer pattern.

The photosensitive film used in this process is preferably a positive photosensitive film, and the transmittance of the first photomask is preferably 20% to 60% of the transmittance of the second photomask.

Each of the first and second photomasks includes a substrate and an opaque pattern layer formed on the substrate and a pellicle formed on the substrate not covered with at least the pattern layer, wherein the difference in transmittance between the first and second photomasks is It can be adjusted by adjusting the transmittance of the pellicle of the first and second photomask.

The first and second photomasks form one mask, and the mask may form two pattern layers having different heights to give a difference in transmittance. In addition, the transmittance difference can be adjusted by forming a slit or a lattice-like fine pattern having a size equal to or less than the resolution of the light source used for exposure.

According to an embodiment of the present invention, a gate line including a gate line and a gate electrode of the screen display unit and a gate pad of the periphery is formed on a substrate including the screen display unit and the peripheral unit, and a gate insulating film, a semiconductor layer, The contact layer is laminated. After applying the photoresist on the contact layer, the photoresist is exposed using a first photomask for patterning the screen display and a first mask having a different transmittance with the first mask for forming a peripheral portion, and the photoresist is developed to have a thickness. Another photosensitive film pattern is formed. Subsequently, the first contact layer pattern and the semiconductor layer pattern are formed by patterning the contact layer of the screen display unit and the semiconductor layer under the same through one etching process, and at the same time, the contact layer, semiconductor layer, and gate insulating layer of the peripheral part are patterned to form a gate. Form a contact window that exposes the pad. The first conductor layer and the second conductor layer are successively stacked, and then photo-etched together with the lower first contact layer pattern to form a double layer of an upper layer layer and a lower layer layer, wherein the data line, the source and drain electrodes of the screen display unit, A data line including the pixel electrode and a data pad of the peripheral portion and a second contact layer pattern under the data line are formed. The protective insulating layer is stacked and patterned thereon to expose the gate pad, the data pad, and the pixel electrode, and finally the upper layer of the gate pad, the data pad, and the pixel electrode is removed.

Here, the first conductor layer is preferably made of ITO, the contact layer may be made of silicide.

This method may be applied to the case where the pixel electrode and the common electrode are provided in the thin film transistor substrate.

That is, the common electrode wire including the common electrode line and the common electrode of the screen display unit together with the gate wiring is formed, and the gate insulating film, the semiconductor layer, and the contact layer are successively deposited thereon, and then patterned by the same method as before. The first contact layer pattern and the semiconductor layer pattern are formed, and a contact window exposing the peripheral gate pads is formed. The conductor layer was stacked and photo-etched together with the primary contact layer pattern to form data lines including data lines of the screen display part, source and drain electrodes, pixel electrodes, and data pads of the peripheral part, and a lower contact layer pattern thereunder. Subsequently, the thin film transistor substrate is completed by stacking and patterning a protective insulating film to expose the gate pad and the data pad.

Then, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

In order to achieve the above object, the present embodiment is to pattern the contact window exposing the gate pad together with the semiconductor layer and the contact layer thereon, but in the screen display part, only the semiconductor layer and the contact layer are patterned, leaving the gate insulating film and leaving the gate pad part in the gate pad part. The gate insulating film is completely removed.

First, the structure of a thin film transistor substrate according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 5.

As shown in FIG. 1, several liquid crystal display panel regions are simultaneously formed on one insulating substrate. For example, as shown in FIG. 1, four liquid crystal display panel regions 110, 120, 130, and 140 are formed in one glass substrate 1, and the panel region is a thin film transistor panel. Reference numerals 110, 120, 130, and 140 include screen displays 111, 121, 131, and 141 made up of a plurality of pixels, and peripheral parts 112, 122, 132, and 142. Thin film transistors, wirings, and pixel electrodes are repeatedly arranged in the form of a matrix in the screen display units 111, 121, 131, and 141, and elements connected to driving elements in the peripheral portions 112, 122, 132, and 142. That is, pads and other static electricity protection circuits are disposed.

However, when forming such a liquid crystal display device, a stepper exposure device is usually used, and when the exposure device is used, the screen display parts 111, 121, 131, and 141 and the peripheral parts 112, 122, 132, and 142 are divided into various zones. The photosensitive film coated on the thin film is exposed using the same mask or another photomask for each zone, and after exposure, the entire substrate is developed to form a photosensitive film pattern, and then a specific thin film pattern is formed by etching the lower thin film. By repeatedly forming such a thin film pattern, a thin film transistor substrate for a liquid crystal display device is completed.

However, it can also expose at once, without using a stepper exposure machine. In addition, only one liquid crystal display panel may be formed on one insulating substrate.

FIG. 2 is a layout view schematically illustrating an arrangement of a thin film transistor substrate for a liquid crystal display device formed in one panel region in FIG. 1.

As shown in FIG. 2, the screen display unit surrounded by the line 1 includes a plurality of thin film transistors 3, a pixel electrode 63, a gate line 22, and a data line (electrically connected to each of the thin film transistors 3). A wiring including 72) is formed. A gate pad 24 connected to the gate line 22 and a data pad 74 connected to the data line 72 are disposed at the periphery outside the screen display, and the gate line 22 is disposed to prevent device destruction due to electrostatic discharge. And a gate line shorting bar 4 and a data line shorting band 5 for electrically connecting the data line 72 and the data line 72 to an equipotential, respectively. The line short circuit board 5 is electrically connected via the short circuit board connection part 6. These short-circuit bands 4 and 5 are later removed, and the line cutting the substrate when removing them is denoted by reference numeral 2. Reference numeral 7, which is not described, is drilled in the insulating film to connect the shorting line connecting portion 6 between the gate line shorting band 4 and the data line shorting band 5 and the insulating film (not shown) as a contact window. have.

3 to 5 are enlarged views of thin film transistors, pixel electrodes, wirings, and peripheral pads of the screen display unit of FIG. 2, FIG. 3 is a layout view, and FIGS. 4 and 5 are lines IV-IV ′ of FIG. 3. A cross-sectional view taken along the line VV '.

First, a gate made of a metal or a conductor such as aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta) or the like on the insulating substrate 10. Wiring is formed. The gate wiring is connected to the scan signal line or the gate line 22 extending in the horizontal direction and the gate line 22 and the gate pad 24 and the gate which receive the scan signal from the outside and transmit the scan signal to the gate line 22. A gate electrode 26 of the thin film transistor, which is a branch of the line 22;

The gate wirings 22, 24, and 26 may be formed in a single layer, but may also be formed in a double layer or a triple layer. In the case of forming more than two layers, it is preferable that one layer is formed of a material having a low resistance and the other layer is formed of a material having good contact properties with other materials, and a double layer of Cr / Al (or Al alloy) or Al / Mo Bilayers are an example.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate wirings 22, 24, and 26 to cover the gate wirings 22, 24, and 26.

Semiconductor layer patterns 42 and 48 made of a semiconductor such as hydrogenated amorphous silicon are formed on the gate insulating layer 30, and ohmic contacts such as silicide are formed on the semiconductor layer patterns 42 and 48. contact layer) patterns or intermediate layer patterns 55, 56, 57, and 59 are formed.

On the other hand, the semiconductor layer patterns 42 and 48 and the contact layer patterns 55, 56, 57, and 59 are inside the screen display, and the gate wirings 22, 24, 26, such as the upper portion of the gate electrode 26, and the data wirings to be described later. It is formed in this intersection part, and is formed in the whole in the peripheral part. However, a contact window 31 exposing the gate electrode 26 is formed in the contact layer pattern 57, the semiconductor layer pattern 48, and the gate insulating layer 30 on the gate pad 24.

First data layer patterns 62, 63, 64, 65, 66, and 67 made of a transparent or opaque conductive material such as indium tin oxide (ITO) are formed on the contact layer patterns 55, 56, 57, and 59. The data line formed of the second data layer patterns 72, 74, 75, 76, 77 made of a conductive material such as Mo or MoW alloy, Cr, Al or Al alloy, Ta is formed thereon. The data wirings are first connected to data lines 62 and 72 formed in the vertical direction, data pads 64 and 74 connected to one end of the data lines 62 and 72 to receive image signals from the outside, and data lines. And a data line portion made up of the source electrodes 65, 75 of the thin film transistor, which are branches of (62, 72). The data wiring is also separated from the data line portion and connected to the drain electrodes 66 and 76 and the drain electrodes 66 and 76 of the thin film transistor positioned opposite the source electrodes 65 and 75 with respect to the gate electrode 26. Also included are the pixel electrodes 63 and auxiliary gate pads 67 and 77 formed directly over the gate pads 24 through the contact windows 31 to cover the gate pads 24. Here, the data lines 62 and 72, the source electrodes 65 and 75, and the drain electrodes 66 and 76 are double layers, and only a part of the auxiliary gate pads 67 and 77 and the data pads 64 and 74 are double layers. The remainder is composed of only a single layer of the first data layer patterns 67 and 64, and the pixel electrode 63 is composed of only a single layer of the first data layer patterns 67 and 64.

On the other hand, the pixel electrode 63 overlaps the gate line 22 to form a storage capacitor.

The second data layer patterns 72, 74, 75, 76, and 77 may be formed in a single layer like the gate lines 22, 24, and 26, but may also be formed in a double layer or a triple layer. Of course, when forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials.

The contact layer patterns 55, 56, 57, and 59 have contact resistances between the lower semiconductor layer patterns 42 and 48 and the upper first data layer patterns 62, 63, 64, 65, 66, and 67. It serves to lower and exists only between the semiconductor layer patterns 42 and 48 and the first data layer patterns 62, 63, 64, 65, 66 and 67.

The second data layer patterns 72, 74, 75, 76, and 77 and the semiconductor layer patterns 42 and 48 not covered with the data wirings are covered with the passivation layer 80, and at least a source electrode of the semiconductor layer patterns 42. It covers and protects the channel portion located between the 75 and the drain electrode 76. The passivation layer 80 may be made of an organic insulating material such as silicon nitride or acrylic.

Although transparent ITO has been used as an example of the material of the pixel electrode 63, an opaque conductive material may be used for the reflective liquid crystal display device.

Next, a method of manufacturing a substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 6A to 12C and FIGS. 3 to 5.

First, as illustrated in FIGS. 6A to 6C, a conductive layer such as a metal is deposited to a thickness of 1,000 kPa to 3,000 kPa by a sputtering method, and first, dry or wet etch using a mask to form a gate on the substrate 10. A gate wiring including the line 22, the gate pad 24, and the gate electrode 26 is formed.

Next, as shown in FIGS. 7A and 7B, the gate insulating film 30 and the semiconductor layer 40 are continuously deposited to a thickness of 1,500 kPa to 5,000 kPa and 500 kPa to 1,500 kPa, respectively, by chemical vapor deposition. Subsequently, a material capable of reacting with the semiconductor layer 40 to form a silicide, for example, a refractory metal such as chromium, is deposited by a sputtering method, and then a silicide layer having a thickness of 300 kPa to 600 kPa on the semiconductor layer 40 ( 50), the remaining metal layer is removed. The silicide layer 50, the semiconductor layer 40, and the gate insulating layer 30 are patterned using a second mask to form the semiconductor layer patterns 42 and 48, the silicide patterns 52 and 58, and the contact window 31 thereon. ) (See FIGS. 11A and 11B). In this case, the silicide layer 50, the semiconductor layer 40, and the gate insulating layer 30 on the gate pad 24 are removed in the peripheral portion P, but the semiconductor layer patterns 42 and 48 and the screen display portion D are removed. Only portions of the semiconductor layer 40 and the silicide layer 50 should be removed from the portions other than the silicide patterns 52 and 58 thereon, and the gate insulating layer 30 should not be removed. To this end, photoresist patterns having different thicknesses are formed according to portions, and dry etching of lower layers is performed using the photoresist pattern as an etching mask, which will be described in detail with reference to FIGS. 7B to 11B.

First, a photoresist film PR, preferably a positive photoresist film, is applied on the silicide layer 50 to a thickness of 5,000 kPa to 30,000 kPa, and then exposed through the second masks 300, 410, and 420. The photosensitive film PR after exposure is different from the screen display portion D and the peripheral portion P as shown in FIGS. 7B and 8C. That is, the portion C of the photosensitive film PR of the screen display unit D that is exposed to light reacts with light only to a certain depth from the surface to decompose the polymer, and the polymer remains under the periphery P. Unlike the photoresist film PR, the portion B exposed to light is in a state in which the polymer is decomposed in response to light. Here, portions C and B exposed to light in the screen display unit D or the peripheral portion P are portions where the silicide layer 50 is to be removed.

To this end, a method of changing the structure of the mask 300 used for the screen display unit D and the masks 410 and 420 used for the peripheral portion P may be used. Here, three methods are presented.

As shown in FIGS. 8A and 8B, the masks 300 and 400 are typically opaque pattern layers 320 and 420 consisting of the substrates 310 and 410 and chromium thereon, and the pattern layers 320 and 420. ) And the pellicles 330 and 430 covering the exposed substrates 310 and 410, and the light transmittance of the pellicle 330 of the mask 300 used for the screen display unit D is the peripheral portion P. FIG. ) Is lower than the light transmittance of the pellicle 430 of the mask 400. The transmittance of the pellicle 330 is preferably in the range of 10% to 80%, preferably 20% to 60% of the transmittance of the pellicle 430.

Next, as shown in FIGS. 9A and 9B, the mask 300 of the screen display unit D is left with a chromium layer 350 at a thickness of about 100 kPa to 300 kPa over the entire surface to lower the transmittance, and the peripheral portion ( The mask 400 of P) does not leave such a chromium layer. In this case, the pellicle 340 of the mask 300 used in the screen display unit D may have the same transmittance as the pellicle 430 of the peripheral portion P. FIG.

Of course, the above two methods can be used in combination.

In the above two examples, it is applicable to the split exposure using a stepper, and is possible because the screen display unit D and the peripheral portion P are exposed using different masks. In the case of the divided exposure in this manner, the thickness can be adjusted by changing the exposure time of the screen display unit D and the peripheral portion P.

However, the screen display unit D and the periphery unit P may be exposed using one mask without being dividedly exposed. In this case, a structure of a mask that can be applied will be described in detail with reference to FIG. 10.

As shown in FIG. 10, the transmittance adjusting film 550 is formed on the substrate 510 of the mask 500, and the pattern layer 520 is formed on the transmittance adjusting film 550. The transmittance adjusting film 550 is formed not only under the pattern layer 520 but also over the entire surface in the screen display unit D, but is formed only under the pattern layer 550 in the peripheral portion P. As a result, two or more patterns having different heights are formed on the substrate 510.

Of course, the periphery portion P may also have a transmittance adjusting film. In this case, the transmittance of the transmittance adjusting film of the peripheral portion P should have a transmittance higher than that of the transmittance adjusting film 550 of the screen display portion P.

When manufacturing the photomask 500 having the transmittance control film 550, first, a transmittance control film 550 and a pattern layer 520 having an etching ratio different from that of the transmittance control film 550 are formed on the substrate 500. Laminate in succession. After the photoresist (not shown) is applied, exposed and developed over the entire surface, the pattern layer 520 is etched using the photoresist as an etch mask. After removing the remaining photoresist film, a new photoresist pattern (not shown) for exposing the transmittance control film at a position corresponding to the contact window of the peripheral portion P is formed again, and then the transmittance control film 550 is etched using this as an etching mask. The optical mask 500 is completed.

In addition to the above method, the transmittance may be adjusted by using a mask having a slit or a lattice-like fine pattern having a size smaller than the resolution of the light source.

However, the portion of the photoresist film PR having a high reflectance metal layer, that is, the gate wirings 22, 24, and 26, may have a greater amount of light irradiation than other portions during exposure due to the reflected light. In order to prevent this, a layer for blocking the reflected light from the bottom may be provided or a colored photoresist film PR may be used.

After exposing the photoresist film PR in this manner, and developing the photoresist film PR with different thicknesses as shown in FIGS. 7A and 7B. That is, the photoresist is not formed on a portion of the gate pad 24, and all of the peripheral portions P except the gate pad 24 and the silicide layer 50 of the portion where the semiconductor layer pattern is to be formed on the screen display portion D are formed. The thick photosensitive film A is formed, and a thin photosensitive film B is formed at the other part of the screen display unit D. FIG.

At this time, the thickness of the thin portion of the photoresist film PR may be about 1/4 to 1/7 level of the initial thickness, that is, 350 to 10,000 GPa, more preferably 1,000 to 6,000 GPa. For example, the initial thickness of the photosensitive film PR may be 25,000 kPa to 30,000 kPa, and the transmittance of the screen display unit D may be 30% so that the thickness of the thin photosensitive film may be 3,000 kPa to 5,000 kPa. However, since the thickness to be left should be determined according to the process conditions of dry etching, the thickness of the pellicle of the mask, the remaining chromium layer or the transmittance or exposure time of the transmittance control film should be adjusted according to the process conditions.

Such a thin photosensitive film may be formed through reflow after exposing and developing the photosensitive film in a conventional manner.

Subsequently, etching is performed on the photoresist pattern PR and the lower layers thereof, that is, the silicide layer 50, the semiconductor layer 40, and the gate insulating layer 30 by a dry etching method.

In this case, as mentioned above, part A of the photoresist pattern PR should remain without being completely removed, and the silicide layer 50, the semiconductor layer 40, and the gate insulating layer 30 under the part B should be removed. Under the portion C, only the silicide layer 50 and the semiconductor layer 40 are removed, and the gate insulating layer 30 should not be removed.

To this end, it is preferable to use a dry etching method capable of simultaneously etching the photoresist pattern PR and the films below it. That is, using the dry etching method, as shown in Figs. 11A and 11B, the three layers and the C layer of the silicide layer 50, the semiconductor layer 40 and the gate insulating film 30 below the B portion without the photosensitive film are thin. Three layers of the photosensitive film, the silicide layer 50 and the semiconductor layer 40 can be etched simultaneously. At this time, the portion A of the photosensitive film pattern PR is also etched to a certain thickness.

Accordingly, the silicide layer patterns 52 and 58 and the semiconductor layer patterns 42 and 48 may be removed by removing only the silicide layer 50 and the semiconductor layer 40 from the screen display unit D through one mask process and a dry etching method. In the peripheral portion P, the silicide layer 50, the semiconductor layer 40, and the gate insulating layer 30 may be removed to form the contact window 31.

Subsequently, the remaining photosensitive film pattern of the A portion is removed, and an ITO layer having a thickness of 400 kPa to 500 kPa and a conductor layer having a thickness of 1,500 kPa to 3,000 kPa are deposited by sputtering or the like. Subsequently, the conductor layer, the ITO layer, and the silicide patterns 52 and 58 thereunder are patterned using a third mask, and the data wiring having the structure as shown in FIGS. 12A to 12C and the contact layer patterns 55 and 56 thereunder. , 57, 59). At this time, the data wiring is not yet completed, and the two layers have the same shape.

3 to 5, silicon nitride is deposited by CVD or spin-coated an organic insulating material to deposit a protective film 80 having a thickness of 3,000 Å or more and then patterned using a fourth mask. In this case, the passivation layer 80 must be patterned to expose a portion of the upper layer of the pixel electrode 63, the auxiliary gate pad 67, and the data pad 64, that is, the second data layer patterns 76, 77, and 74. .

Finally, the exposed portions of the second data layer patterns 76, 77, and 74 are removed to complete the thin film transistor substrate.

As described above, in this embodiment, the contact window 31 exposing the gate pad 24 is formed by using a mask together with the semiconductor layer patterns 42 and 48 and the silicide patterns 52 and 58 thereon, thereby forming a mask. Reduce the number

Meanwhile, in the above embodiment, the case where only the pixel electrode is provided on the thin film transistor substrate is taken as an example. However, the method may be applied to the case where both the pixel electrode and the common electrode are provided on the thin film transistor substrate.

This case is shown in the second embodiment of the present invention to be described hereafter, and this will be described in detail with reference to FIGS. 13 to 18C.

FIG. 13 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment, and FIGS. 14 and 15 are cross-sectional views taken along the lines XIV-XIV 'and XV-XV' of FIG. 3.

First, a gate made of a metal or a conductor such as aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta) or the like on the insulating substrate 10. Wiring is formed. The gate wiring is connected to the scan signal line or the gate line 22 extending in the horizontal direction and the gate line 22 and the gate pad 24 and the gate which receive the scan signal from the outside and transmit the scan signal to the gate line 22. A gate electrode 26 of the thin film transistor that is part of the line 22.

On the substrate 10 is also formed a common electrode wiring made of the same material as the gate wiring. The common electrode wiring includes a common electrode line 27 extending in the horizontal direction in parallel with the gate line 22 and a common electrode 28 that is a vertical branch of the common electrode line 27, but is not illustrated, but the common electrode line 27 is shown. The common electrode line pads formed at the end of the s) to receive the common electrode signal and transmit the common electrode signal to the common electrode line 27 are also formed in substantially the same shape as the gate pad 24.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate wirings 22, 24, 26, and the common electrode wirings 27, 28 to form the gate wirings 22, 24, 26, and the common electrode wiring 27. , 28).

The semiconductor layer patterns 42, 44, and 48 formed of a semiconductor such as hydrogenated amorphous silicon are formed on the gate insulating layer 30, and the n-type impurities such as phosphorus (P) are formed on the semiconductor layer patterns 42, 44, and 48. Resistive contact layer patterns or interlayer patterns 54, 55, 56, 59 made of doped hydrogenated amorphous silicon or silicide are formed.

Meanwhile, the semiconductor layer patterns 42, 44, and 48 intersect the gate wirings 22, 24, 26 and the common electrode wirings 27, 28, such as the upper portion of the gate electrode 26, and the data wirings to be described later in the screen display unit. It is formed in the part to which it is made, and is formed in the whole in the peripheral part. However, the contact window 31 exposing the gate electrode 26 is drilled through the semiconductor layer pattern 48 and the gate insulating film 30.

On the contact layer patterns 54, 55, 56, 59, data wirings 72, 74, 75, 76, 77, 78, 79 made of a conductive material such as Mo or MoW alloy, Cr, Al or Al alloy, Ta, etc. Formed. First, the data line is a branch of the data line 72 formed in the vertical direction, the data pad 74 connected to one end of the data line 72 to receive an image signal from the outside, and the data line 72. A drain of the thin film transistor including a data line part formed of the source electrode 75 of the thin film transistor, which is separated from the data line parts 72, 74, and 75 and is located opposite to the source electrode 75 with respect to the gate electrode 26. Electrode 76. The data wiring is also connected to the drain electrode 76 and is connected to the pixel electrode line 79 and the pixel electrode line 79 in a horizontal direction parallel to the common electrode line 27 and to the pixel electrode parallel to the common electrode 28. (78). The pixel electrode 78 and the common electrode 28 are alternately arranged to form an electric field.

The pixel electrode 78 may overlap the common electrode line 27 to form a storage capacitor.

The data wirings 72, 74, 75, 76, 77, 78, 79 may also be formed in a single layer like the gate wirings 22, 24, 26 and the common electrode wirings 27, 28, but a double layer or a triple layer may be used. It may be formed as. Of course, when forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials.

The contact layer patterns 54, 55, 56, and 59 have contact resistances between the lower semiconductor layer patterns 42, 44, and 48 and the upper data lines 72, 74, 75, 76, 77, 78, and 79. It serves to lower the, and is present only between the semiconductor layer patterns 42, 44, 48 and the data wirings (72, 74, 75, 76, 77, 78, 79).

The data wirings 72, 74, 75, 76, 77, 78, 79 and the semiconductor layer patterns 42, 44, and 48 not covered with the data wirings are covered with the protective film 80, and the gate pads 24 and the data are covered with the passivation layer 80. It has contact windows 82 and 83 exposing the pad 74. The passivation layer 80 covers and protects a channel portion between at least the source electrode 75 and the drain electrode 76 of the semiconductor layer pattern 42, and may be made of an organic insulating material such as silicon nitride or acrylic. .

Next, a method of manufacturing a substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 16A to 18C and FIGS. 13 to 15.

First, as shown in FIGS. 16A to 16C, a conductive layer such as a metal is deposited to a thickness of 1,000 kPa to 3,000 kPa by a sputtering method, and first, dry or wet etch using a mask, and then gated on the substrate 10. A gate wiring including a line 22, a gate pad 24, and a gate electrode 26 and a common electrode wiring including a common electrode line 27, a common electrode line pad (not shown), and a common electrode 28 are formed. do.

17A and 17B, the gate insulating film 30, the amorphous silicon layer 40, and the doped amorphous silicon layer 50 were each subjected to chemical vapor deposition using 1,500 kPa to 5,000 kPa, and 500 kPa to Continuous deposition at a thickness of 1,500 kPa, 300 kPa to 600 kPa. The semiconductor layer patterns 42, 44, and 48 and the doped amorphous silicon layer patterns thereon are patterned by patterning the doped amorphous silicon layer 50, the amorphous silicon layer 40, and the gate insulating layer 30 using the second mask. 52, 54, 58 and the contact window 31 is formed. In this case, the doped amorphous silicon layer 50, the amorphous silicon layer 40, and the gate insulating layer 30 on the gate pad 24 are removed from the peripheral portion P, but the semiconductor layer pattern 42 is removed from the screen display portion D. , 44, 48, and portions other than the doped amorphous silicon layer patterns 52, 54, and 58 thereon, only the semiconductor layer 40 and the doped amorphous silicon layer 50 are removed, and the gate insulating layer 30 is removed. It should not be.

The method used for this is the same as in the first embodiment.

That is, a photosensitive film pattern having a different thickness is formed according to a part, and the lower layers are dry-etched using this as an etching mask. When forming the photosensitive film pattern, a mask having a different light transmittance is used.

Subsequently, a conductive layer such as metal is deposited to a thickness of 1,500 kPa to 3,000 kPa by a method such as sputtering. Subsequently, the conductor layer and the doped amorphous silicon layer patterns 52, 54, and 58 thereunder are patterned using a third mask to form data wires 72, 74, 75, and 76 having a structure as shown in FIGS. 18A to 18C. , 77, 78, 79 and lower contact layer patterns 54, 55, 56, 59.

Finally, as shown in FIGS. 13 to 15, silicon nitride is deposited by CVD or spin-coated an organic insulating material to deposit a protective film 80 having a thickness of 3,000 3,000 or more, and then patterned by using a fourth mask. The thin film transistor substrate is completed by forming contact windows 82 and 83 exposing the gate pad 24, the common electrode line pad and the data pad 74.

As such, in this embodiment, the contact window 31 exposing the gate pad 24 is formed together with the semiconductor layer patterns 42, 44, and 48 and the doped amorphous silicon layer patterns 52, 54, and 58 thereon. By forming using a mask, the number of masks is reduced.

As described above, the present invention reduces the manufacturing process number of the thin film transistor substrate for a liquid crystal display device through a new photolithography method of the thin film, and simplifies the process to lower the manufacturing cost and increase the yield. In addition, it is possible to etch a large area to different depths while having a uniform etching depth for one etching depth.

Claims (11)

Forming a gate line on the substrate including a screen display unit and a peripheral unit, a gate line connected to the gate display unit, a gate electrode and the gate line, connected to an external driving element, and including a gate pad positioned at the peripheral unit , Forming a gate insulating layer pattern on the gate wiring; Forming a semiconductor layer pattern on the gate insulating layer pattern; Forming a contact layer pattern on the semiconductor layer pattern, Forming a data line on the contact layer pattern, the data line including a data pad positioned at the screen display unit, a source and drain electrode connected to the data line, connected to external driving elements, and a data pad positioned at the periphery; Forming a channel passivation pattern, and Forming a pixel electrode connected to the drain electrode Including; In the gate insulating film pattern forming step, a first photomask for patterning the screen display unit and a first photomask are different from each other in transmittance, and are exposed using a second photomask for patterning the peripheral portion. The gate insulating layer pattern is formed together with the semiconductor layer pattern and the contact layer pattern in one photo process. The manufacturing method of the thin film transistor substrate for liquid crystal display devices. In claim 1, And the gate insulating film pattern is formed using a positive photosensitive film. In claim 2, The transmittance of the first photomask is 20% to 60% of the transmittance of the second photomask. In claim 1, The first and second photomasks each include a substrate, an opaque pattern layer formed on the substrate, and a pellicle formed on the substrate not covered with at least the pattern layer, wherein the first and second photomasks The method of manufacturing a thin film transistor substrate for a liquid crystal display device, wherein the transmittance difference is controlled by adjusting transmittances of pellicles of the first and second photomasks. In claim 1, The first and second photomasks form a mask, and the mask includes a substrate, a first pattern layer formed on the substrate, and a second pattern layer formed on the substrate and having a different height from the first pattern layer. And a difference in transmittance between the first and second photomasks due to a height difference between the first and second pattern layers. In claim 1, The method of manufacturing a thin film transistor substrate for a liquid crystal display device, wherein the difference in transmittance between the first and second photomasks is controlled by forming a slit or a lattice-like fine pattern having a size equal to or less than the resolution of the light source used for the exposure. Forming a gate line on the substrate including a screen display unit and a peripheral unit, a gate line connected to the gate electrode and the gate line, connected to external driving radiations, and including a gate pad of the peripheral unit; Continuously depositing a gate insulating film, a semiconductor layer, and a contact layer on the gate wiring; Applying a photoresist film on the contact layer, Exposing the photosensitive film using a first photomask for patterning the screen display unit and a second photomask having a transmittance different from that of the first mask and forming the peripheral portion; Developing the photoresist to form a photoresist pattern having a different thickness; The first contact layer pattern and the semiconductor layer pattern are formed by patterning the contact layer and the semiconductor layer under the screen display unit through one etching process, and at the same time, the contact layer, the semiconductor layer, and the gate of the peripheral part. Patterning an insulating film to form a contact window exposing the gate pad, Sequentially stacking the first conductor layer and the second conductor layer, Photo-etching the first and second conductor layers and the first contact layer pattern below the photoconductor to form a double layer of an upper layer and a lower layer, and are connected to a data line, a source and a drain electrode, and the data line on the screen display unit. Forming a data line connected to external driving elements and including a data pad positioned at the periphery and a second contact layer pattern below the data line; Stacking a protective insulating film, Patterning the protective insulating film to expose the gate pad, the data pad, and the pixel electrode; and Removing the upper layer of the gate pad, the data pad, and the pixel electrode Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. In claim 7, And the first conductor layer is made of ITO. In claim 8, The contact layer is a silicide manufacturing method of a thin film transistor substrate for a liquid crystal display device. A gate line and a gate electrode on the substrate including a screen display unit and a peripheral unit, a gate wire connected to the gate electrode and the gate line, connected to external driving elements, and including a gate pad positioned at the peripheral unit, and the screen display unit Forming a common electrode wiring including a common electrode line and a common electrode, Continuously depositing a gate insulating film, a semiconductor layer, and a contact layer on the gate wiring and the common electrode wiring; Applying a photoresist film on the contact layer, Exposing the photosensitive film using a first photomask for patterning the screen display unit and a second photomask having a transmittance different from that of the first mask and forming the peripheral portion; Developing the photoresist to form a photoresist pattern having a different thickness; The first contact layer pattern and the semiconductor layer pattern are formed by patterning the contact layer and the semiconductor layer below the screen display unit through one etching process, and at the same time, the contact layer, the semiconductor layer, and the gate of the peripheral part. Patterning an insulating film to form a contact window exposing the gate pad, Laminating the conductor layer, Data etching the conductive layer and the first contact layer pattern below the data pad, a data pad, a source and a drain electrode, and a data pad, which is connected to the data line and is connected to external driving elements, and is disposed on the peripheral part. Forming a second data layer and a second contact layer pattern under the data line; Stacking a protective insulating film, Patterning the protective insulating layer to expose the gate pad and the data pad Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. Forming a gate line on the substrate including a screen display unit and a peripheral unit, a gate line connected to the gate electrode and the gate electrode and the gate line and connected to external driving elements, and including a gate pad positioned at the peripheral unit; Forming a gate insulating layer pattern on the gate wiring; Forming a semiconductor layer pattern on the gate insulating layer pattern; Forming a contact layer pattern on the semiconductor layer pattern, Forming a data line on the contact layer pattern, the data line including a data pad positioned at the screen display unit, a source and drain electrode connected to the data line, connected to external driving elements, and a data pad positioned at the periphery; Forming a channel passivation pattern, and Forming a pixel electrode connected to the drain electrode Including; The thickness of the photoresist pattern for patterning the screen display part and the thickness of the photoresist pattern for patterning the peripheral part are different from each other in the gate insulating film pattern forming step, A method of manufacturing a thin film transistor substrate for a liquid crystal display device, wherein the gate insulating film pattern, the semiconductor layer pattern, and the contact layer pattern are formed in one photo process.