KR100729767B1 - manufacturing method of thin film transistor array panel for liquid crystal display - Google Patents

Abstract

A gate wiring including a gate line, a gate electrode, and a gate pad is formed on an insulating substrate, and a gate insulating film, a semiconductor layer, and an ohmic contact layer are sequentially formed. Next, after forming a data line including a data line, a source electrode, a drain electrode, and a data pad, a protective film is deposited and a photosensitive film pattern having a different thickness is formed on the protective film. In this case, the thickness of the portion of the photoresist pattern located above the gate line of the front end is thinner than other portions, and the photoresist of the drain electrode, the gate pad, and the data pad is removed. Next, the protective film and the gate insulating film are removed to expose the drain electrode, the gate pad, and the data pad, and then the photoresist pattern is ashed to expose the protective film on the gate line. Next, the exposed protective film is etched with only a predetermined thickness, and then the remaining photoresist pattern is removed to leave a thin protective film on the gate line. Next, a pixel electrode, an auxiliary gate pad, and an auxiliary data pad are formed. As described above, by reducing the thickness of the protective film forming the storage capacitor with the gate line in front of the pixel electrode interposed therebetween, the same amount of storage capacitance can be obtained even if the overlapping area is reduced, so that the aperture ratio can be improved. In addition, it is possible to control the holding capacity by adjusting the thickness of the protective film forming the holding capacity, and when the thickness of the protective film forming the holding capacity is increased to increase the holding capacity, the kickback voltage may be reduced to reduce the flicker phenomenon.

Photosensitive film pattern, holding capacity, aperture ratio

Description

Manufacturing method of thin film transistor substrate for liquid crystal display device

1 is a layout view illustrating a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention.

2 is a cross-sectional view taken along the line II-II in FIG.

3A is a layout view showing a thin film transistor substrate in a first step of manufacturing according to the first embodiment of the present invention;

FIG. 3B is a cross sectional view taken along line IIIb-IIIb in FIG. 3A;

FIG. 4a is a layout view in the next step of FIG. 3a;

4B is a cross-sectional view of the line in FIG. 4A;

FIG. 5A is a layout view of the next step of FIG. 4A;

FIG. 5B is a cross sectional view taken along the line Vb-Vb in FIG. 5A;

FIG. 6a is a sectional view at the next step of FIG. 5a;

6B and 6C are cross-sectional views sequentially showing the processes in the next step of FIG. 6A in the order thereof;

FIG. 7a is a layout view in the next step of FIG. 6c;

FIG. 7B is a cross sectional view taken along the line VIIb-VIIb in FIG. 7A;                 

8 is a layout view illustrating a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

9 is a cross-sectional view taken along line VII-VII in FIG. 8,

10A is a layout view showing a thin film transistor substrate in a first step of manufacturing according to the second embodiment of the present invention;

FIG. 10B is a cross-sectional view taken along the line VIIb-VIIb in FIG. 10A;

FIG. 11A is a layout view in the next step of FIG. 10A;

FIG. 11B is a cross-sectional view taken along the line XIB-XIB in FIG. 11A,

12A is a layout view at the next step of FIG. 11A;

FIG. 12B is a cross sectional view taken along line XIIb-XIIb in FIG. 12A;

FIG. 13 is a sectional view at the next step of FIG. 12B;

FIG. 14a is a layout view in the next step of FIG. 13;

FIG. 14B is a cross-sectional view taken along line XIVb-XIVb in FIG. 14A.

The present invention relates to a method for manufacturing a thin film transistor substrate for a liquid crystal display device.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two glass substrates on which electrodes are formed and a liquid crystal layer interposed therebetween. The liquid crystal molecules of the liquid crystal layer are applied by applying a voltage to the two electrodes. A display device for controlling the amount of light transmitted by rearranging them.

It is common to have a thin film transistor for switching a voltage applied to an electrode on one substrate of the liquid crystal display device. In addition to the thin film transistor, the thin film transistor substrate has a gate line for receiving a scan signal from the outside and a data line for receiving an image signal from the outside. And a pixel electrode formed in each pixel region formed by the intersection of the gate line and the data line.

In such a liquid crystal display device, a storage capacitor should be formed in order to improve the charge storage capability of the pixel.

In the method of forming the storage capacitor, the gate line and the pixel electrode are overlapped with an insulating film interposed therebetween, and the storage capacitor electrode is formed in the same layer as the data line to increase the storage capacitance and reduce the overlapping area. There is a method of contacting the pixel electrode. In this case, since the thickness of the insulating film between the pixel electrode and the gate line is large, the overlapping area of the pixel electrode and the gate line must be increased in order to obtain an appropriate holding capacitance value. On the other hand, when the storage capacitor electrode is formed to reduce the thickness between the pixel electrode and the gate line, there is a possibility that pixel defects may be caused due to film residue, impurity particles, and the like in the formation process.

The technical problem to be achieved by the present invention is to improve the aperture ratio without reducing the holding capacity.

In order to achieve the above object, in the present invention, a contact hole is formed using a photosensitive film pattern having a different thickness according to a position, and at the same time, a predetermined thickness of the passivation layer on the gate line overlapping the pixel electrode is removed.

According to the present invention, a gate wiring including a gate line and a gate electrode is formed on an insulating substrate, and a gate insulating film and a semiconductor layer are sequentially formed thereon. Next, a data line including a data line, a source electrode and a drain electrode is formed, and a protective film is deposited. Next, a first contact hole exposing the drain electrode is formed in the protective film, and a pixel electrode overlapping the gate line is formed. Here, when forming the first contact hole, it is preferable to use a photolithography process using a photoresist pattern having a different thickness depending on the position, by removing a predetermined thickness of the passivation layer on the upper gate line.

The photoresist pattern includes a first portion having a first thickness, a second portion thicker than the first thickness, and a third portion having no thickness and excluding the first and second portions, wherein the third portion is an upper portion of the drain electrode and the first portion. Preferably, the portion is formed above the gate line and the second portion is positioned at the remaining portions except for the first and third portions.

When forming the first contact hole, the protective film is first removed using the photosensitive film pattern as a mask, and the protective film of the first portion is exposed by ashing the photosensitive film pattern. Next, the protective film of the first portion is removed by a predetermined thickness, and the photosensitive film pattern is removed.

Meanwhile, the protective film and the photoresist pattern may be etched together to form the first contact hole, and the protective film of the first portion may be removed by a predetermined thickness.                     

The photoresist pattern is formed using an optical mask including a first region, a second region having a lower transmittance than the first region, and a third region having a higher transmittance than the first region, and the first, second and third regions. The silver is preferably aligned to correspond to the first, second and third portions of the photosensitive film pattern, respectively. Here, in order to control the transmittance of the first to third regions differently, a slit pattern smaller than the resolution of the transflective film or the exposure machine may be formed in the photomask.

The gate wiring further includes a gate pad connected to the gate line, and the data wiring further includes a data pad connected to the data line, and the gate pad and the data when forming the first contact hole exposing the drain electrode. Second and third contact holes exposing the pads are formed, respectively, and when forming the pixel electrode, an auxiliary gate pad and an auxiliary data pad respectively connected to the gate pad and the data pad may be formed.

An ohmic contact layer may be further formed between the semiconductor layer and the data line.

According to another embodiment of the present invention, a gate wiring including a gate line and a gate electrode and a storage capacitor wiring are formed on an insulating substrate, and a gate insulating film and a semiconductor layer are sequentially formed. Next, a data line including a data line, a source electrode and a drain electrode is formed, and a protective film is deposited. Next, a contact hole exposing the drain electrode is formed in the protective film, and a pixel electrode overlapping the storage capacitor wiring is formed. Here, it is preferable to remove the predetermined thickness of the protective film on the upper part of the storage capacitor wiring when forming the contact hole.                     

In this case, when the contact hole is formed, a photolithography process using a photoresist pattern having a different thickness is used, and the photoresist pattern has a first portion having a first thickness, a second portion thicker than the first thickness, and no thickness. It is preferred to include a third portion except for the first and second portions. In the photoresist pattern, the third part is preferably formed above the drain electrode, the first part is located above the storage capacitor wiring, and the second part is located at the remaining part except for the first and third parts.

When forming the contact hole, first, the protective film is removed using the photosensitive film pattern as a mask, and the protective film of the first portion is exposed by ashing the photosensitive film pattern. Next, the protective film of the first portion is removed by a predetermined thickness, and the photosensitive film pattern is removed.

Meanwhile, the protective film and the photoresist pattern may be etched together to form contact holes, and the protective film of the first portion may be removed by a predetermined thickness.

In the present invention, even if the thickness of the passivation film forming the storage capacitor with the gate line or the storage capacitor wiring and the pixel electrode is made thin, the same amount of storage capacitance can be obtained, so that the aperture ratio can be improved.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings so that a person skilled in the art can easily practice the present invention. .

First, the structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a layout view illustrating a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1.

1 and 2, on the insulating substrate 10, aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten alloy (MoW), chromium (Cr), tantalum (Ta), etc. Gate wirings 21, 22, and 23 made of a metal or a conductor are formed. The gate wiring is connected to the gate line 21 extending in the horizontal direction, the gate electrode 22 that is part of the gate line 21, and the end of the gate line 21, and receives a scan signal from the outside to the gate line 21. A gate pad 23.

The gate wirings 21, 22, and 23 may be formed in a single layer, but may be formed in a double layer or a triple layer. In the case of forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials. For example, a double layer of Cr / Al (or an Al alloy) or Al / A bilayer of Mo can be mentioned.

A gate insulating layer 30 made of silicon nitride (SiN _X ) is formed on the gate lines 21, 22, and 23.

A semiconductor layer 41 made of a semiconductor such as amorphous silicon is formed on the gate insulating layer 30, and an semiconductor such as amorphous silicon doped with n-type impurities such as phosphorus (P) is formed on the semiconductor layer 41. Resistive contact layers 52 and 53 are formed on both sides of the gate electrode 22.

On the ohmic contacts 52 and 53, data wirings 61, 62, 63 and 64 made of a metal or a conductor such as aluminum or an aluminum alloy, molybdenum or molybdenum-tungsten alloy, chromium and tantalum are formed. The data line includes a data line 61 extending in the vertical direction, a source electrode 62 which is a part of the data line 61, a drain electrode 63 facing the source electrode 62 around the gate electrode 22, and data. And a data pad 64 connected to the line 61 to receive an image signal from the outside and transmit the image signal to the data line 61.

The data wirings 61, 62, 63, and 64 can be formed in a single layer similarly to the gate wirings 21, 22, and 23, but can also be formed in a double layer or a triple layer. In the case of forming more than two layers, it is preferable that one layer is formed of a material having a low resistance and the other layer is formed of a material having good contact properties with other materials.

A protective film 70 made of silicon nitride is formed on the data lines 61, 62, 63, and 64 and the gate insulating film 30. The passivation layer 70 has not only a contact hole 73 exposing the gate pad 23 with the gate insulating film 30, but also a contact hole 74 and a drain electrode 63 exposing the data pad 64. It has a contact hole 72. In addition, the passivation layer 70 of the upper portion P of the gate line 21 at the front end is removed to have a predetermined thickness and is thinner than the passivation layer 70 of other portions.

The pixel electrode 80, the auxiliary gate pad 83, and the auxiliary data pad 84 made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) are formed on the passivation layer 70.

The pixel electrode 80 is connected to the drain electrode 63 through the contact hole 72 to receive an image signal. The pixel electrode 80 overlaps the gate line 21 of the previous stage, and interposes the gate insulating layer 30 and the passivation layer 70 therebetween. Leaving capacity. The auxiliary gate pad 83 and the auxiliary data pad 84 are connected to the gate pad 23 and the data pad 64 through the contact holes 73 and 74, respectively, which are the pads 23 and 64 and the external circuit. It serves to complement the adhesion with the device and to protect the pads 23 and 64.

Here, since the thickness of the passivation layer 70 constituting the storage capacitor is thin, the thickness between the gate line 21 and the pixel electrode 80 can be reduced, so that the same area is reduced even when the gate line 21 and the pixel electrode 80 overlap. Since a positive holding capacity can be obtained, the aperture ratio can be improved. The holding capacity can be adjusted by adjusting the thickness of the passivation layer 70 constituting the holding capacity, and when the thickness of the passivation layer 70 constituting the holding capacity is increased to increase the holding capacity, the kickback voltage is reduced to reduce the flicker phenomenon. You can. In addition, as in the prior art, it is not necessary to form the storage capacitor electrode made of the same layer as the data line to form the storage capacitor, thereby preventing pixel defects due to film residue or impurities.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention will be described with reference to FIGS. 3A to 7B and FIGS. 1 and 2.

First, as shown in FIGS. 3A and 3B, a gate wiring conductor or a metal is deposited on the insulating substrate 10 to a thickness of 1,000 Å to 3,000 으로 by sputtering, and patterned by a photolithography process using a mask. A gate wiring including 21, the gate electrode 22, and the gate pad 23 is formed.                     

Next, as shown in FIGS. 4A and 4B, the gate insulating film 30, the amorphous silicon layer, and the amorphous silicon layer doped with n-type impurities are respectively 1,500 kV to 5,000 kV, 500 kV to 1,500 kV using chemical vapor deposition. The semiconductor layer 41 and the ohmic contact layer 51 are formed by sequentially depositing a thickness of 300 kPa to 600 kV and patterning the two upper layers by a photolithography process using a mask.

Next, as shown in FIGS. 5A and 5B, a conductor or a metal for data wiring is deposited to a thickness of 1,500 kV to 3,000 kV by a sputtering method, and patterned by a photolithography process using a mask to form a data line 61 and a source electrode. A data line including the 62, the drain electrode 63, and the data pad 64 is formed. Next, the ohmic contact layer 51 not covered by the source electrode 62 and the drain electrode 63 is removed to separate the two portions 52 and 53.

Next, as shown in FIG. 6A, after the protective film 70 is deposited to a thickness of 3,000 Pa or more using silicon nitride by chemical vapor deposition, a photosensitive film is applied. Next, the photosensitive film is irradiated with light using a mask 100 having a different transmittance depending on the location, and then developed to form photosensitive film patterns 112 and 114 having different thicknesses according to the location. In this case, the thickness of the second portion 114 positioned on the upper portion C of the gate line 21 of the front end of the photoresist patterns 112 and 114 may be equal to the first portion positioned in the region A except for the second portion 114. It is thinner than 112 and removes the photoresist of the drain portion 63, the gate pad 23, and the portion B of the upper portion of the data pad 64.

As such, there may be various ways of varying the thickness of the photoresist film according to the position, and in order to control the light transmittance in the C region, a slit or lattice-shaped pattern is mainly used or a semi-transmissive film is used.

In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure machine used for exposure. In the case of using a semi-transmissive film, a different transmittance for controlling the transmittance when fabricating a mask A thin film having a thickness or a thin film may be used.

Here, the second portion 114 of the photoresist layer is exposed to light using a photoresist layer made of a reflowable material, and is exposed using a conventional mask that is divided into a portion that can completely transmit light and a portion that can not completely transmit light. And a portion of the photoresist film flows down to a portion where the photoresist film does not remain.

Next, the photoresist patterns 112 and 114, the passivation layer 70, and the gate insulating layer 30 are etched.

First, as shown in FIG. 6B, the exposed protective film 70 and the gate insulating film 30 of the portion B are removed to expose the drain electrode 63, the gate pad 23, and the data pad 64. In this process, the photoresist patterns 112 and 114 are preferably performed under conditions that are hardly etched.

Next, as shown in FIG. 6C, the protective film 70 is exposed by ashing the photoresist pattern to remove the photoresist pattern 114 of the C portion. At this time, since the photoresist layer pattern 112 of the portion A is also etched, the thickness becomes thin, so that the photoresist pattern 112 is removed so that the protective layer 70 of the portion A is not exposed.

Next, as shown in FIGS. 7A and 7B, after etching the protective film 70 of the portion C with only a predetermined thickness, the photoresist pattern 112 remaining in the portion A is removed, and the upper portion P of the gate line 21 is removed. The thin protective film 70 is left. Here, the thickness of the protective film 70 left in the portion C is determined by the amount of the storage capacitance.

Next, as shown in FIG. 1 and FIG. 2, a transparent conductive material such as ITO or IZO is deposited to a thickness of 400 kV to 500 kV by a sputtering method, and patterned by a photolithography process using a mask to form the pixel electrode 80. The auxiliary gate pad 83 and the auxiliary data pad 84 are formed.

On the other hand, after forming the photoresist patterns 112 and 114 having different thicknesses according to the position, the contact hole 72 is formed by etching the protective film 70, the gate insulating film 30 and the photoresist patterns 112 and 114 together. , 73 and 74 may be formed and a predetermined thickness of the photoresist pattern 114 and the passivation layer 70 of the C portion may be removed.

In the first embodiment of the present invention, the storage capacitor is formed by using the front gate line 21, but the storage capacitor may be formed separately from the gate line 21 to form the storage capacitor. In this case as well, the protective film on the upper portion of the storage capacitor wiring is removed by a predetermined thickness to form the storage capacitor, thereby obtaining the same effect as in the first embodiment, which will be described as a second embodiment of the present invention.

First, a structure of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention will be described with reference to FIGS. 8 and 9.                     

8 and 9, in the thin film transistor substrate according to the second embodiment, the storage capacitor wiring 25 is formed in parallel to the same layer as the gate line 21 between the gate lines 21. Except that the wiring 25 and the pixel electrode 80 overlap to form a storage capacitor, the structure is the same as that of the first embodiment.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention will be described with reference to FIGS. 10A to 14B and FIGS. 8 and 9.

First, as shown in FIGS. 10A and 10B, a gate wiring conductor or a metal is deposited on the insulating substrate 10 and patterned by a photolithography process using a mask to form a gate line 21, a gate electrode 22, and a gate pad ( A gate wiring and a storage capacitor wiring 25 including 23 are formed.

Next, as shown in FIGS. 11A and 11B, the gate insulating layer 30, the amorphous silicon layer, and the amorphous silicon layer doped with n-type impurities are sequentially deposited, and the upper two layers are patterned by a photolithography process using a mask to form a semiconductor. Layer 41 and ohmic contact layer 51 are formed.

Next, as shown in FIGS. 12A and 12B, a conductor or a metal for data wiring is deposited and patterned by a photolithography process using a mask to form a data line 61, a source electrode 62, a drain electrode 63, and a data pad ( A data line including 64) is formed. Next, the ohmic contact layer 51 not covered by the source electrode 62 and the drain electrode 63 is removed to separate the two portions 52 and 53.                     

Next, as shown in Figure 13, after the protective film 70 made of silicon nitride is deposited, a photosensitive film is applied. Next, the photosensitive film is irradiated with light using a mask having a different transmittance depending on the location, and then developed to form photosensitive film patterns 212 and 214 having different thicknesses depending on the location. In this case, the thickness of the second portion 214 positioned on the upper portion F of the storage capacitor wiring 25 among the photoresist patterns 212 and 214 may be the first portion 212 positioned in the region D except for the second portion 214. It is thinner than), and the photoresist of the portion E of the upper portion of the drain electrode 63, the gate pad 23, and the data pad 64 is removed. Here, the photosensitive films 212 and 214 having different thicknesses depending on the position are formed by using a mask having different transmittances depending on the position in the same manner as in the first embodiment of the present invention.

Next, etching is performed on the photoresist patterns 212 and 214, the passivation layer 70, and the gate insulating layer 30 in the same manner as in the first embodiment of the present invention.

First, the exposed protective film 70 and the gate insulating film 30 of the portion E are removed to expose the drain electrode 63, the gate pad 23, and the data pad 64. Next, the protective film 70 is exposed by ashing the photoresist pattern to remove the photoresist pattern 214 of the F portion. Next, after etching the protective film 70 of the portion F, leaving only a predetermined thickness, and removing the photoresist pattern 212 remaining in the portion D, as shown in Figure 14a and 14b, the upper portion (P) of the storage capacitor wiring 25 The thin protective film 70 is left. Here, the thickness of the protective film 70 left in the F portion is determined according to the amount of the storage capacitance.

In this case, after forming the photoresist patterns 212 and 214 having different thicknesses according to positions, the contact holes 72 may be formed by etching the protective layer 70, the gate insulating layer 30, and the photoresist patterns 112 and 114 together. , 73 and 74 may be formed and a predetermined thickness of the photoresist pattern 214 and the passivation layer 70 of the F portion may be removed.

Next, as shown in FIGS. 8 and 9, a transparent conductive material such as ITO or IZO is deposited and patterned by a photolithography process using a mask to form the pixel electrode 80, the auxiliary gate pad 83, and the auxiliary data pad. Form 84.

As described above, in the present invention, even if the overlapping area is reduced by reducing the thickness of the protective film forming the storage capacitor with the gate line or the storage capacitor wiring in front of the pixel electrode interposed therebetween, the opening ratio can be improved. . In addition, it is possible to control the holding capacity by adjusting the thickness of the protective film forming the holding capacity, and when the thickness of the protective film forming the holding capacity is increased to increase the holding capacity, the kickback voltage may be reduced to reduce the flicker phenomenon. In addition, as in the prior art, it is not necessary to form the storage capacitor electrode made of the same layer as the data line to form the storage capacitor, thereby preventing pixel defects due to film residue or impurities.

Claims (16)

Forming a gate wiring including a gate line and a gate electrode on the insulating substrate, Forming a gate insulating film, Forming a semiconductor layer, Forming a data line including a data line, a source electrode and a drain electrode, Depositing a protective film, Forming a first contact hole exposing the drain electrode in the passivation layer, Forming a pixel electrode overlapping the gate line Including; And removing a predetermined thickness of the passivation layer on the gate line in the forming of the first contact hole. In claim 1, In the forming of the first contact hole, a method of manufacturing a thin film transistor substrate for a liquid crystal display device using a photolithography process using a photosensitive film pattern having a different thickness depending on a position. In claim 2, The photoresist pattern may include a first part having a first thickness, a second part thicker than the first thickness, and a third part having no thickness and excluding the first and second parts. Manufacturing method. In claim 3, In the photoresist pattern, the third portion is formed on the drain electrode, the first portion is on the gate line, and the second portion is formed on the remaining portions except for the first and third portions. Method for manufacturing a transistor substrate. In claim 4, Forming the first contact hole, Removing the protective film using the photoresist pattern as a mask; Ashing the photoresist pattern to expose the passivation layer of the first portion; Removing the protective film of the first portion by a predetermined thickness; Removing the photoresist pattern Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. In claim 5, And etching the protective film and the photosensitive film pattern together to form the first contact hole and simultaneously removing the protective film of the first portion by a predetermined thickness. In claim 4, The photoresist pattern is formed using an optical mask including a first region, a second region having a lower transmittance than the first region, and a third region having a higher transmittance than the first region, wherein the first, second, The second and third regions are arranged to correspond to the first, second and third portions of the photosensitive film pattern, respectively. In claim 7, A method of manufacturing a thin film transistor substrate for a liquid crystal display device, wherein a slit pattern smaller than the resolution of a transflective film or an exposure machine is formed in the photomask to differently control the transmittances of the first to third regions. In claim 1, The gate line further includes a gate pad connected to the gate line, and the data line further includes a data pad connected to the data line. Forming second contact holes exposing the gate pad and the data pad, respectively, in forming a first contact hole exposing the drain electrode; And forming an auxiliary gate pad and an auxiliary data pad connected to the gate pad and the data pad, respectively, in the forming of the pixel electrode. In claim 1, And forming an ohmic contact layer between the semiconductor layer and the data line. Forming a gate wiring and a storage capacitor wiring including a gate line and a gate electrode on the insulating substrate, Forming a gate insulating film, Forming a semiconductor layer, Forming a data line including a data line, a source electrode and a drain electrode, Depositing a protective film, Forming a contact hole in the passivation layer to expose the drain electrode; Forming a pixel electrode overlapping the storage capacitor wiring Including; And removing a predetermined thickness of the passivation layer on the storage capacitor wiring in the step of forming the contact hole. In claim 11, In the forming of the contact hole, a method of manufacturing a thin film transistor substrate for a liquid crystal display device using a photolithography process using a photosensitive film pattern having a different thickness depending on a position. In claim 12, The photoresist pattern may include a first part having a first thickness, a second part thicker than the first thickness, and a third part having no thickness and excluding the first and second parts. Manufacturing method. In claim 13, In the photoresist pattern, the third portion is formed above the drain electrode, the first portion is located above the storage capacitor wiring, and the second portion is positioned in the remaining portions except for the first and third portions. Method of manufacturing a thin film transistor substrate. The method of claim 14, Forming the contact hole, Removing the protective film using the photoresist pattern as a mask; Ashing the photoresist pattern to expose the passivation layer of the first portion; Removing the protective film of the first portion by a predetermined thickness; Removing the photoresist pattern Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. The method of claim 15, And etching the protective film and the photoresist pattern together to form the contact hole and simultaneously removing the protective film of the first portion by a predetermined thickness.

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