KR20010001361A - a manufacturing method of a thin film transistor panel for liquid crystal displays - Google Patents

Abstract

PURPOSE: A method for manufacturing a substrate of a thin film transistor for liquid crystal display is provided to reduce manufacturing cost and process, by effectively decreasing the number of masks. CONSTITUTION: A gate interconnection including a gate line and a gate electrode connected to the gate line is formed on an insulating substrate. A gate insulating layer covering the gate interconnection is formed. A semiconductor layer is deposited on the gate insulating layer. A resistive contact layer is deposited on the semiconductor layer. A metal layer for a data interconnection is deposited on the resistive contact layer. A photoresist layer pattern having the first portion of the first thickness, the second portion of the second thickness thicker than the first portion and the third portion of no thickness are formed on the metal layer for the data interconnection. The metal layer for the data interconnection is firstly dry-etched to form a metal pattern for the data interconnection placed under the first and second portions by using the photoresist layer pattern as a mask. The resistive contact layer and the semiconductor layer are secondly dry-etched to form a resistive contact pattern and a semiconductor pattern placed under the metal pattern. The first portion is etched back to expose the fourth portion of the metal pattern for the data interconnection placed under the first portion. The fourth portion is thirdly dry-etched to form source/drain electrodes and a data line. The exposed resistive contact layer pattern is fourth dry-etched.

Description

A manufacturing method of a thin film transistor panel for liquid crystal displays

The present invention relates to a method for manufacturing a thin film transistor substrate for a liquid crystal display device.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. By controlling the amount of light transmitted.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on each of two substrates and switching a voltage applied to the electrode is generally used. The thin film transistor is generally formed on one of two substrates.

The substrate on which the thin film transistor is formed is generally manufactured through a photolithography process using a mask. At this time, in order to reduce the production cost, it is preferable to reduce the number of masks, and five or six masks are currently used. Of course, a method of manufacturing a thin film transistor substrate using four masks has also been disclosed.

An example of the manufacturing method of the conventional thin film transistor substrate for liquid crystal display devices using four masks is demonstrated.

First, a gate wiring is formed of aluminum or an aluminum alloy having a low resistance on a substrate by using a first mask, and then a gate insulating film, an amorphous silicon layer, an n + amorphous silicon layer, and a metal layer are sequentially stacked thereon. Using a second mask, a three-layer film of a metal layer, an n + amorphous silicon layer, and an amorphous silicon layer is patterned. At this time, only the gate insulating film remains without the three-layer film pattern remaining on the gate pad. Subsequently, an indium tin oxide (ITO) film is laminated and patterned using a third mask. At this time, no ITO film remains on the gate pad. The metal layer and the n + amorphous silicon layer are patterned using the ITO film as a mask, and then a protective film is laminated. Finally, the thin film transistor substrate is completed by patterning the passivation layer and the gate insulating layer under the passivation layer using a fourth mask. Here, the gate insulating film of the gate pad portion is removed in the last step of the protective film patterning step.

In the conventional manufacturing method using four masks, since the ITO process is performed before the protective film process, after the step of patterning the protective film and the gate insulating film, the gate pad made of aluminum or an aluminum alloy is exposed to the outside air as it is. These aluminum or aluminum alloys are easily damaged because of their low resistance but weak physical and chemical stimuli.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a novel method for manufacturing a thin film transistor substrate for a liquid crystal display device, which can perform the ITO process after the protective film process and can also reduce the number of masks.

Another object of the present invention is to provide a method of manufacturing a thin film transistor substrate for a liquid crystal display device, which simplifies an etching process performed in one photo process.

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention.

2 and 3 are cross-sectional views of the thin film transistor substrate shown in FIG. 1 taken along lines II-II 'and III-III';

4A is a layout view of a thin film transistor substrate in a first step of manufacturing according to the first embodiment of the present invention,

4B and 4C are cross-sectional views taken along the lines IVb-IVb 'and IVc-IVc' in FIG. 4A, respectively.

5A and 5B are cross-sectional views taken along the IVb-IVb 'line and the IVc-IVc' line in FIG. 4A, respectively, and are cross-sectional views of the next steps of FIGS. 4B and 4C.

6A is a layout view of a thin film transistor substrate in the next steps of FIGS. 5A and 5B;

6B and 6C are cross-sectional views taken along lines VIb-VIb 'and VIc-VIc' in FIG. 6A, respectively.

7A, 8A, 9A, and 7B, 8B, and 9B are cross-sectional views taken along the lines VIb-VIb 'and VIc-VIc' in FIG. 6A, respectively, illustrating the following steps in the order of the process. ,

10A is a layout view of a thin film transistor substrate in the next steps of FIGS. 9A and 9B;

10B and 10C are cross-sectional views taken along lines Xb-Xb 'and Xc-Xc', respectively, in FIG. 10A;

11 is a flowchart of a detailed etching process performed after performing a photolithography process using one mask.

In order to achieve this problem, in the present invention, data wirings such as source and drain electrodes and data lines, ohmic contact layer patterns, and semiconductor patterns are formed by dry etching in one chamber.

According to the present invention, a gate wiring including a gate line and a gate electrode connected thereto is formed on an insulating substrate, and a gate insulating film, a semiconductor layer, an ohmic contact layer, and a metal layer for data wiring are successively deposited thereon. Next, a photoresist pattern including a first portion having a first thickness, a second portion having a thickness thicker than the first thickness, and a third portion having no thickness is formed on the data wiring metal layer in a portion positioned above the gate electrode, Using the photosensitive film pattern as a mask, the metal layer for data wiring is first dry-etched to form a metal pattern for data wiring underlying the first and second portions. Next, the resistive contact layer and the semiconductor layer are secondaryly dry-etched to form a resistive contact pattern and a semiconductor pattern under the metal pattern, and the first portion of the photoresist pattern is etched under the back surface of the metal pattern for data wiring under the first portion. Reveal the fourth part. Subsequently, the fourth portion of the metal pattern for data wiring is dry-etched in a third manner using the second portion of the photoresist pattern as a mask to form a source electrode, a drain electrode, and a data line. Thereafter, the ohmic contact layer pattern exposed between the source electrode and the drain electrode is removed by dry etching in a fourth order. At this time, the first to fourth dry etching and back etching is performed in the same chamber.

In this case, the source electrode and the drain electrode, the data line, the ohmic contact layer pattern, and the semiconductor pattern may be formed using one mask.

The first dry etching and the second dry etching are continuously performed, and it is preferable to use He, H _2, N ₂ or O ₂ as a dilution gas so that the upper photoresist ensures uniformity within 15%. Do.

Back etching is performed using O ₂ gas to ensure a sufficient selection ratio with the data wiring metal layer, the ohmic contact layer, the semiconductor layer, the gate insulating film, and the like. In this case, a small amount of Cl ₂ , SF ₆ is used to control the etching ratio. Alternatively, the mixture may be performed by mixing CF ₄ gas.

The metal layer for data wiring is preferably formed of a metal having low resistance such as Al, Ti, Mo, MoW or Ta and capable of dry etching.

In addition, the third dry etching may be performed under conditions in which the etching selectivity of the metal pattern for data wiring with respect to the gate insulating film is 5: 1 or more, thereby securing a process margin.

In addition, the second portion of the photoresist pattern may be removed before or after the dry etching stepwise.

After that, a protective insulating film is deposited and etched together with the gate insulating film to form contact holes that expose the drain electrode, the gate pad formed at the end of the gate line, and the data pad formed at the end of the data line, respectively. The ITO pixel electrode, the auxiliary gate pad, and the auxiliary data pad may be formed to contact the drain electrode, the gate pad, and the data pad, respectively.

Then, the liquid crystal display according to an exemplary embodiment of the present invention and a manufacturing method thereof will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

First, the structure of the thin film transistor substrate for a liquid crystal display according to the first embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3.

FIG. 1 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention, and FIGS. 2 and 3 are lines II-II 'and III-III' of the thin film transistor substrate shown in FIG. A cross-sectional view taken along the line.

First, a gate made of a metal or a conductor such as aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta) or the like on the insulating substrate 10. Wiring is formed. The gate wiring is connected to the scan signal line or the gate line 22 extending in the horizontal direction and the gate line 22 and the gate pad 24 and the gate which receive the scan signal from the outside and transmit the scan signal to the gate line 22. A gate electrode 26 of the thin film transistor that is part of the line 22, and a sustain electrode 28 that is parallel to the gate line 22 and receives a voltage such as a common electrode voltage input to the common electrode of the upper plate from the outside. . The storage electrode 28 overlaps with the conductive capacitor conductor 68 for the storage capacitor connected to the pixel electrode 82, which will be described later, to form a storage capacitor which improves the charge retention capability of the pixel. The pixel electrode 82 and the gate line, which will be described later, If the holding capacity generated by the overlap of (22) is sufficient, it may not be formed.

The gate wirings 22, 24, 26, and 28 may be formed as a single layer, but may be formed as a double layer or a triple layer. In the case of forming more than two layers, it is preferable that one layer is formed of a material having a low resistance and the other layer is formed of a material having good contact properties with other materials, and a double layer of Cr / Al (or Al alloy) or Al / Mo Bilayers are an example.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate wirings 22, 24, 26, and 28 to cover the gate wirings 22, 24, 26, and 28.

Semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed on the gate insulating layer 30, and high concentrations of n-type impurities such as phosphorus (P) are formed on the semiconductor patterns 42 and 48. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon doped with is formed.

On the contact layer patterns 55, 56, and 58, a data line made of a conductive material such as Mo or MoW alloy, Cr, Al or Al alloy, and Ta is formed. The data line is a thin film transistor which is a branch of the data line 62 formed in the vertical direction, the data pad 64 connected to one end of the data line 62 to receive an image signal from the outside, and the data line 62. And a data line portion of the source electrode 65 of the source electrode 65, separated from the data line portions 62, 64, and 65, of the source electrode 65 with respect to the gate electrode 26 or the channel portion C of the thin film transistor. It also includes a conductive capacitor conductor 68 for the storage capacitor located on the drain electrode 66 and the storage electrode 28 of the thin film transistor located on the opposite side. When the sustain electrode 28 is not formed, the conductor pattern 68 for the storage capacitor is also not formed.

The data lines 62, 64, 65, 66, 68 may also be formed in a single layer like the gate lines 22, 24, 26, 28, but may be formed in a double layer or a triple layer. Of course, when forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials.

The contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has exactly the same form as (62, 64, 65, 66, 68). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 64 and 65, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor pattern 68 for holding capacitors.

The semiconductor patterns 42 and 48 have the same shapes as the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 57 except for the channel portion C of the thin film transistor. have. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor pattern 68 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the semiconductor pattern 42 for the thin film transistor has data wiring and contact. Slightly different from the rest of the layer pattern. That is, the data line parts 62, 64, 65, in particular, the source electrode 65 and the drain electrode 66 are separated from the channel portion C of the thin film transistor, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode is separated. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor.

The passivation layer 70 is formed on the data wires 62, 64, 65, 66, and 68, and the passivation layer 70 forms the drain electrode 66, the data pad 64, and the conductive pattern 68 for the storage capacitor. The contact holes 71, 73, and 74 are exposed, and the contact holes 72 are exposed to expose the gate pad 24 together with the gate insulating film 30. As shown in FIG. The passivation layer 70 may be made of an organic insulating material such as silicon nitride or acrylic.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as indium tin oxide (ITO), and is physically and electrically connected to the drain electrode 66 through the contact hole 71 to receive an image signal. The pixel electrode 82 also overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. In addition, the pixel electrode 82 is also connected to the storage capacitor conductor pattern 68 through the contact hole 74 to transmit an image signal to the conductor pattern 68. On the other hand, an auxiliary gate pad 84 and an auxiliary data pad 86 connected to the gate pad 24 and the data pad 64 through the contact holes 72 and 73, respectively, are formed. , 64) and to protect the pads and the adhesion of the external circuit device, it is not essential, and their application is optional.

Although transparent ITO has been used as an example of the material of the pixel electrode 82, an opaque conductive material may be used for the reflective liquid crystal display device.

Next, a method of manufacturing a liquid crystal display substrate according to a first embodiment of the present invention will be described in detail with reference to FIGS. 4A to 13C and FIGS. 1 to 3.

First, as shown in FIGS. 4A to 4C, a conductive layer such as a metal is deposited to a thickness of 1,000 kPa to 3,000 kPa by a sputtering method, and first, dry or wet etch using a mask to form a gate on the substrate 10. A gate wiring including a line 22, a gate pad 24, a gate electrode 26, and a sustain electrode 28 is formed.

Next, as shown in FIGS. 5A and 5B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 are respectively 1,500 kV to 5,000 kV, 500 kV to 2,000 kV, and 300 kV using chemical vapor deposition. Continuously deposited to a thickness of from about 600 kPa to about 600 kPa, and then depositing the conductor layer 60 to a thickness of 1,500 kPa to 3,000 kPa by using a metal such as Mo or MoW alloy, Al or Al alloy, Ta, Ti or the like. Then, the photosensitive film 110 is applied thereon to a thickness of 1 μm to 2 μm.

Thereafter, the photosensitive film 110 is irradiated with light through a second mask and then developed to form photosensitive film patterns 112 and 114 as illustrated in FIGS. 6B and 6C. In this case, among the photoresist patterns 112 and 114, the channel portion C of the thin film transistor, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, is the data wiring portion A, that is, the data. The thickness of the wirings 62, 64, 65, 66, and 68 is smaller than that of the second portion 112 positioned at the portion where the wirings 62, 64, 65, 66, and 68 are to be formed. At this time, the ratio of the thickness of the photoresist film 114 remaining in the channel portion C to the thickness of the photoresist film 112 remaining in the data wiring portion A should be different depending on the process conditions in the etching process described later. It is preferable to make the thickness of the 1st part 114 into 1/2 or less of the thickness of the 2nd part 112, for example, it is good that it is 4,000 Pa or less.

Subsequently, as shown in FIGS. 7A to 9B, the photoresist pattern 114 and the lower layers thereof, that is, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40 are etched, thereby performing data wiring. The data wiring and the lower layers thereof remain in the portion A, the semiconductor layer remains only in the channel portion C, and all three layers 60, 50, and 40 are removed in the remaining portion B, thereby removing the gate insulating film. Let (30) be revealed. In this case, the intermediate layer 50 and the semiconductor layer 40 are etched by a dry etching method, and the conductor layer 60 is etched by a wet etching method or a dry etching method. However, when the conductor layer 60 is formed of Cr, Cr is hardly removed by the dry etching method. Therefore, it is preferable to use a wet etching method.

As such, in each case where the conductor layer 60 is etched by the wet etching method and the dry etching method, the conductor layer patterns 62, 64, 65, 66, 68, the semiconductor layer patterns 42, 48, and the contact layer pattern ( 55, 56 and 58 will be described in more detail with reference to FIGS. 7A and 9B.

First, as shown in FIGS. 7A and 7B, the exposed conductor layer 60 of the other portion B is removed to expose the lower intermediate layer 50. In this process, both a dry etching method and a wet etching method may be used. In this case, the conductive layer 60 may be etched and the photoresist patterns 112 and 114 may be hardly etched.

When the conductor layer 60 is formed of any one of Mo or MoW alloy, Al or Al alloy, Ta, Ti, either dry etching or wet etching can be used. However, when formed of Cr as described above, after performing wet etching using an etchant such as CeNHO ₃ , hard bake is performed.

This leaves only the conductor layer of the channel portion C and the data wiring portion A, that is, the conductor pattern 67 for the source / drain and the conductor pattern 68 for the storage capacitor, and the conductor layer of the other portion B. All 60 are removed to reveal the underlying intermediate layer 50. The remaining conductor patterns 67 and 68 have the same shape as the data lines 62, 64, 65, 66, and 68 except that the source and drain electrodes 65 and 66 are connected without being separated.

When the processes of FIGS. 7A and 7B are performed by using a dry etching method, it is difficult to find a condition in which only the conductor layer 60 is etched and the photoresist patterns 112 and 114 are not etched. Etching is performed under the condition that the patterns 112 and 114 are etched together. In this case, the thickness of the first portion 114 is thicker than in the case of wet etching, and the conductor layer 60 is etched to form the source / drain conductor pattern 67 and the storage capacitor conductor 68. In this process, the first portion 114 is completely removed so that the conductive layer 60 under the first portion 110 is not exposed. In this case, as the etching gas, a mixture of CF ₄ and HCl or a mixture of CF ₄ and O ₂ may be used. In the latter case, the etching ratio of the photoresist film is almost the same.

Subsequently, as shown in FIGS. 8A and 8B, the exposed intermediate layer 50 of the other portion B and the semiconductor layer 4 thereunder together with the first portion 114 of the photosensitive film are simultaneously subjected to a dry etching method. Remove Then, the first portion 114 of the channel portion C is removed to expose the conductor pattern 67 for the source / drain, and the intermediate layer 50 and the semiconductor layer 40 of the other portion B are removed. The lower gate insulating layer 30 is exposed. On the other hand, since the second portion 112 of the data wiring portion A is also etched, the thickness becomes thin. In this step, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 indicate the intermediate layer pattern under the source / drain conductor pattern 67 and the intermediate layer pattern under the storage capacitor conductor pattern 68, respectively.

In this step, when the conductive layer 60 has been wet etched and patterned in advance, such dry etching is performed in a chamber different from the chamber where wet etching is performed. At this time, the etching should be performed under the condition that the gate insulating film 30 is not etched, and the selectivity is about 5: 1 or more. In particular, the etching ratio of the photoresist patterns 112 and 114 and the semiconductor layer 40 is almost the same. It is preferable to etch. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etch ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first portion 114 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50.

Meanwhile, in the case where the conductor patterns 67 and 68 are etched by the dry etching method, the intermediate layer 50 and the semiconductor layer 40, which are the lower layers, are formed in a chamber after the conductive layer 50. It is possible to etch continuously. However, in the continuous etching of the conductor layer 60, the intermediate layer 50, and the semiconductor layer 60, diluting gases such as He, H ₂ , N ₂ , and O _{2 in} order to etch the photoresist uniformly within 15%. Use independently or in combination of two or more.

Subsequently, the photoresist residue remaining on the surface of the source / drain conductor pattern 67 of the channel part C is removed by ashing or back-etching. When performing back etching, selection of the source / drain conductor pattern 67 of the channel portion C, and the source / drain intermediate layer pattern 57 and the semiconductor pattern 42 and the gate insulating film 30 thereunder. In order to secure the ratio and prevent the gate insulating film 30 from being etched, O ₂ gas may be used as a basic etching gas, but a small amount of gas such as Cl ₂ , SF ₆ , CF ₄ may be mixed to control the etching ratio. It may be.

Next, as shown in FIGS. 9A and 9B, the source / drain conductor pattern 67 of the channel portion C is wet or dry etched, and the source / drain interlayer pattern 57 thereunder is dried. By etching, the data lines 62, 64, 65, 66, and 68 including the source electrode 65 and the drain electrode 66 and the intermediate layer patterns 55, 56, and 58 underneath are completed.

When the source / drain conductor pattern 67 is wet etched and the source / drain interlayer pattern 57 is dry etched, the etching pattern is prevented from being etched through the photoresist pattern 112 during the wet etching process. The hard bake can be done before. The wet etching is performed in a chamber different from the chamber in which dry etching for forming the semiconductor patterns 42 and 48 is performed, and then in a dry etching chamber for forming the intermediate layer patterns 55, 56 and 58. Examples of the etching gas used to etch the source / drain interlayer pattern 57 may include the aforementioned mixed gas of CF ₄ and HCl or mixed gas of CF ₄ and O ₂ . Since there is almost no selectivity, as shown in FIG. 9B, a part of the semiconductor pattern 42 may be removed to reduce the thickness.

When both the source / drain conductor pattern 67 and the source / drain interlayer pattern 57 are etched by dry etching, a separate hard bake is performed before the source / drain conductor pattern 67 is etched. There is no need to do it. In addition, it is carried out in the same chamber as the previous step. In this case, it is preferable to perform etching under the condition that the etching selectivity of the source / drain conductor pattern 67 and the interlayer pattern 57 is large, which is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 42 remaining in the. In addition, examples of the etching gas used to etch the conductor pattern 67 for the source / drain may include a mixed gas of SF ₆ and O ₂ , and may be used to etch the intermediate layer pattern 57 for the source / drain. Examples of the etching gas may include the aforementioned mixed gas of CF ₄ and HCl or mixed gas of CF ₄ and O ₂ .

Finally, the second photoresist layer 112 remaining in the data wiring portion A is removed. However, the removal of the second portion 112 may be made after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 57 thereunder.

After the data wirings 62, 64, 65, 66, and 68 are formed in this manner, as shown in FIGS. 10A to 10C, silicon nitride is deposited by CVD or spin-coated an organic insulating material to have a thickness of 3,000 Å or more. The protective film 70 is formed. Subsequently, the passivation layer 70 is etched together with the gate insulating layer 30 by using a third mask to form the drain electrode 66, the gate pad 24, the data pad 64, and the conductive pattern 68 for the storage capacitor, respectively. The exposed contact holes 71, 72, 73, 74 are formed.

Finally, as shown in FIGS. 1 to 3, an ITO layer having a thickness of 400 μs to 500 μs is deposited and etched using a fourth mask to form the pixel electrode 82, the auxiliary gate pad 84, and the auxiliary data pad. Form 86.

As described above, in the present exemplary embodiment, the data lines 62, 64, 65, 66, 68, the contact layer patterns 55, 56, 58, and the semiconductor patterns 42, 48 below them are formed using one mask. In this process, since the source electrode 65 and the drain electrode 66 are separated, a thin film transistor substrate for a liquid crystal display device can be manufactured using only four masks. In addition, since the ITO film is formed after the protective insulating film, the gate pad and the data pad are covered by the auxiliary gates and the data pads 84 and 86 without being exposed to the outside, thereby reducing damage to the pad portion.

On the other hand, when all of the data lines 62, 64, 65, 66, 68, the contact layer patterns 55, 56, 58, and the semiconductor patterns 42, 48 under the dry etching method are described above, As described above, the data lines 62, 64, 65, 66, and 68, the contact layer patterns 55, 56, and 58, and the semiconductor patterns 42 and 48 may be continuously formed in the same chamber without changing the etching chamber. Since no hard bake process is required, it is advantageous in terms of simplification of the process.

This will be described below with reference to FIG. 11.

11 shows a detailed etching process flow chart performed after performing a photolithography process using one mask.

As shown in FIG. 11, in the left flowchart in which the primary and the secondary etching of the source / drain conductor layer 60 are performed by the wet etching method, between the wet etching and the dry etching stages, that is, the primary wet etching. And transferring the thin film transistor substrate to a chamber for another purpose at least three times, one time after the hard bake, one time after the semiconductor dry etching and photoresist film (PR) back etching and the hard bake, and one time after the second wet etching. Move it. This chamber movement can cause bottlenecks at certain stages of the process, which can be an obstacle to mass production.

In contrast, as shown in the flowchart on the right, where the primary and secondary etching of the source / drain conductor layer 60 is performed by the dry etching method, it is possible to perform all the processes in one chamber for one photo process. As such, the process is simplified and more advantageous for mass production applications.

As described above, according to the present invention, when the thin film transistor substrate for a liquid crystal display device is manufactured, deterioration of the pad part characteristics can be prevented and the number of masks can be effectively reduced, thereby reducing manufacturing cost and maximizing the simplification of the manufacturing process. have.

Claims (10)

Forming a gate wiring including a gate line and a gate electrode connected to the insulating substrate, Forming a gate insulating film covering the gate wiring; Depositing a semiconductor layer on the gate insulating film, Depositing an ohmic contact layer over the semiconductor layer; Depositing a metal layer for data wiring on the ohmic contact layer; Forming a photoresist pattern on the data line metal layer, wherein the photoresist pattern includes a first portion having a first thickness, a second portion having a thickness greater than the first thickness, and a third portion having no thickness; , Forming a data wiring metal pattern under the first portion and the second portion by first dry etching the data wiring metal layer using the photoresist pattern as a mask; Forming a ohmic contact pattern and a semiconductor pattern under the metal pattern by second dry etching the ohmic contact layer and the semiconductor layer using the photoresist pattern and the metal pattern for data wiring as a mask; Back etching the first portion of the photoresist pattern to expose a fourth portion of the data wiring metal pattern under the first portion; Forming a source electrode, a drain electrode, and a data line by removing the fourth part of the data wiring metal pattern by a third dry etching using the second part of the photoresist pattern as a mask; and Removing the ohmic contact layer pattern exposed between the source electrode and the drain electrode by a fourth dry etching; The first to fourth dry etching and the back etching are performed in the same chamber. In claim 1, And forming the source electrode and the drain electrode, the data line, the ohmic contact layer pattern, and the semiconductor pattern using a mask. In claim 1, And removing the second portion of the photoresist pattern prior to performing the fourth dry etching. In claim 1, And removing the second portion of the photoresist pattern after performing the fourth dry etching. The method of claim 3 or 4, Forming a gate pad formed at an end of the gate line; Etching the metal layer for data wiring to form a data pad formed at an end of the data line; Depositing a protective insulating layer on the source electrode, the drain electrode, the data line, the semiconductor pattern, the gate pad, the data pad, and the gate insulating film; Etching the protective insulating film and the gate insulating film to form first to third contact holes respectively exposing the drain electrode, the gate pad, and the data pad; and And forming an ITO pixel electrode, an auxiliary gate pad, and an auxiliary data pad in contact with the drain electrode, the gate pad, and the data pad, respectively, through the first to third contact holes. Method of preparation. In claim 1, The first dry etching and the second dry etching are continuously performed, and a method of manufacturing a thin film transistor substrate for a liquid crystal display device using He, H _2, N ₂ or O ₂ as a diluent gas. In claim 1, The back side etching is performed by using an O ₂ gas. In claim 7, The back etching is a method of manufacturing a thin film transistor substrate for a liquid crystal display device is performed by mixing Cl ₂ , SF ₆ or CF ₄ . In claim 1, The data wiring metal layer is formed of Al, Ti, Mo, MoW or Ta. In claim 1, And the third dry etching is performed under a condition that an etch selectivity of the metal pattern for data wiring with respect to the gate insulating film is 5: 1 or more.