TW200421467A - Method of manufacturing IPS-LCD by using 4-mask process - Google Patents

Abstract

A method of manufacturing IPSLCD by using 4-mask process is provided. One character of the method is to form the amorphous silicon islands and the contact holes by the same mask. Herein, each amorphous silicon island is used to form the channel of one transistor for controlling the LCD pixel inside the active area, and each contact hole is used to form portion of the anti-ESD circuit around the active area. Another character of the method is to form the amorphous silicon islands and the contact holes by a phase-shaft mask. Herein, partial phase shift mask over the contact holes is not covered by any pattern, and partial phase shift mask over the transistors inside the active area and the transistors of the anti-ESD circuit is covered by low transmittance pattern, and other partial phase shift mask is covered by high transmittance pattern.

Description

200421467 V. Description of the invention (1) 1. [Technical field to which the invention belongs] The present invention relates to a method for forming a lateral electric field-driven liquid crystal display panel (IPS-LCD) using a four-mask process, and a method thereof structure. In particular, the present invention relates to a method and a structure for driving a liquid crystal display panel using a four-mask process to form a lateral electric field using a same mask to form contact holes and channels before forming a second metal layer. Second, [prior art]

Known technology for forming a thin film transistor liquid crystal display panel (TFT-LCD)

The gate bus (g a t e b u s 1 i n e), the channel layer (or amorphous stone island), the data bus, the protective layer, the contact hole and the pixel electrode circuit, etc. are usually defined using different masks. Obviously, the more masks are used, the higher the manufacturing cost. Therefore, how to reduce the number of masks required in the manufacturing process has become an important issue for the thin film transistor liquid crystal display panel industry. Since backcha η ne 1 etch (BCE) thin-film transistor liquid crystal display panels do not require additional optical lithography and deposition steps during the manufacture of such thin-film transistor liquid crystal display panels, such thin film transistor liquid crystal display panels have been widely used to Reduce the number of masks required for the process. The manufacturing process of this thin film transistor liquid crystal display panel needs to define different patterns and define at least one contact hole on four different materials, so at least five masks are needed. To further reduce the number of masks required in the process, two

200421467 V. Description of the invention (2) Different material layers are defined with a mask ^ ^ 9 or the same material layer b * is called. So far, some four masking processes have emerged. For example, # „. 〇7, j = σung’ Samsung has proposed a method of using a slit (si it) (or gray-

The mask method to define both the channel layer and the data bus line at the same time is obviously a four-mask process. However, due to the lateral electric field driving fluid, the display panel must be protected against electrostatic discharge (㈣t ^ e 1 ectr 〇-static disehairge 'anti ~ ESD) circuit to protect all transistors located in the active area' and The anti-static discharge protection circuit is a transistor whose gate is electrically coupled to the drain (or source), so an additional lithography step is needed to define the gate to the drain / source. Contact hole for pole channel. Samsung's method can roughly summarize the basic steps described below;

As shown in FIG. 1A, a first metal layer is formed on the substrate 丨 0, and the first metal layer is patterned using a mask and is formed into a plurality of first metal lines 1 1 (or gates). Polar line) on the substrate 10. Next, an insulating layer 1 2, a silicon layer 1 3, an N + type silicon layer 14, and a second metal layer 15 are formed on the substrate 10 and the first metal line 11 in this order. Among them, the substrate 10 is a transparent substrate and can be divided into at least three areas ... a common / pixel area, a transistor area, and an anti-ESD protection circuit area (anti-ESD circuit area). In addition, Samsung's method only focuses on the formation method of driving the liquid crystal display panel in a lateral electric field, and the layout method is not particularly emphasized, and the layout using conventional technology can be used (

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200421467 V. Description of the invention (3) layout). As shown in FIG. 1B, a photoresist layer 16 is formed on the second metal layer 15 and a slit mask (second mask) is used to pattern the photoresist layer 16 3. The slit mask includes a plurality of first patterns 16 1 and a plurality of second patterns 16 2 above the transparent substrate 160. The first pattern 1 6 1 is located above a conductive line (such as a bus line), and the second pattern 1 6 2 is located above a transistor. By appropriately adjusting the shape and arrangement of the above-mentioned first pattern 16 and the above-mentioned second pattern 16 2, especially the adjustment between any one of the first pattern 16 and the adjacent second pattern 16 2 is appropriately adjusted. Distance, a hole 1 6 4 can be formed in the photoresist layer 1 6 3 under the second pattern 16 2. As shown in FIG. 1C, the second metal layer 15, the N + type silicon layer 14 and the amorphous silicon layer 13 are patterned using the photoresist layer 16 as a mask. As shown in the first D diagram, the photoresist layer 16 is etched to expose the second metal layer 15. The thickness of the photoresist layer 16 is controlled so as not to be depleted in a subsequent etching step. Then, the remaining photoresist layer 16 is used as a mask to define the channel of each transistor. As shown in the first E diagram, the remaining photoresist layer 13 is removed, and then a protective layer 17 is formed on the substrate 10. As shown in the first F diagram, an indium tin oxide layer 18 (ITO layer) is formed.

Page 7 200421467 V. Description of the invention (4) The first metal wire 11 and the second metal layer 15 are electrically connected in the anti-ESD circuit area. The structure shown in the first F figure needs to be completed with two masks. The third mask is used to form a contact hole to expose a portion of the first metal wire 11 in the area of the anti-static discharge protection circuit, and the fourth The mask is used to pattern the indium tin oxide layer 18. Of course, the fourth mask can also be used to pattern define some outer lead bonding (0LB) pads on the substrate 10. To sum up, Samsung's method does not include a process of forming a contact hole before forming a source / drain. Therefore, at least one step of forming a contact hole and one additional metallization step for electrically connecting the first metal line 11 and the second metal line 15 are required. Among them, the electrical connection is usually achieved by using a transparent layer of indium tin oxide. Obviously, Samsung's method did not completely solve the previous problem. Without counting the steps of forming ITO, any four-mask process using IPS-LCD can further reduce costs. In other words, the previous problem is still a problem to be solved, and further research and development is necessary. 3. Summary of the Invention The main object of the present invention is to provide a method for improving the disadvantages of the conventional method by using a four-channel mask to form a lateral electric field to drive a liquid crystal display panel.

Page 8 200421467 V. Description of the invention (5) Another main object of the present invention is to propose a four-mask process, which can save the burden of indium tin oxide by forming contact holes, pixel electrodes and channel layers with the same mask. Physical related costs. ^ Another main object of the present invention is to propose a four-mask process using a phase shift mask. This phase shifting mask can be divided into three parts: • Directional transmittance area, low transmittance area, and transparent area.

The main purpose of the present invention is to provide a liquid crystal display device with a lateral electric field driving type (I = SmOd =). Among them, the electrical connection of the anti-static discharge protection circuit is completely located under the protective layer, and an additional material of the thin film transistor can be used as an electrical circuit. The present invention does not require any electrical connection at all. The present invention achieves the above-mentioned object by first, using a pattern of 4 inches. It is not located on the surface of the substrate > a predetermined position is formed and covered by the photoresist layer of the channel layer and the pixel electrode. To ground, the contact hole is located in the non-photoresist layer and defines the contact ^. Hunting this ’* resistive layer can be in the same-second lithography step. Second, provide U-through: layer and pixel electrode. Different light transmittance zones. Two masks, especially-phase shift masks, the beans are right ·-still transmittance F ± 乂 This phase shift mask has one, # Γ has two kinds of hands, and the range is-the same transmittance area, a low The moon region was attacked by two bismuth% π. Generally, t Α is low, and the transparent region H is: This high light transmittance region is composed of: H-rate region system, and J is a transparent substrate. In this way, ^ materials are used to define the contact hole with the method of 200421467 V. Description of Invention (6), and use other areas to pattern and define the channel layer and the pixel electrode, respectively. Crystal display liquid: The step-by-step driving power is used to drive the horizontal package into a small shape to reach the distance. The example mask is used to cover the road and the road is better! Use the method to make the method to apply the fang board and the surface. First, as shown in FIG. 2A, a substrate 20 is provided. The substrate 20 can be divided into at least the following three regions: a common line / pixel region, a transistor region, and an antistatic discharge protection circuit region. Next, a first metal layer is formed on the substrate 20 and patterned using a first mask. As a result, a plurality of first metal lines 2 1 1 are formed in a common line / pixel region, a plurality of second metal lines 2 1 2 are formed in a transistor region, and a plurality of third metal lines 2 1 3 are formed in anti-static discharge protection. Circuit area. Next, an insulating layer 2 2, a silicon layer 23, and a semiconductor layer 24 are sequentially formed on the substrate 20, and then a first metal line 2 1 1, a second metal line 2 1 2 and a third metal line are sequentially formed. 2 1 3. Here, the silicon layer 23 is an amorphous silicon layer, and the semiconductor layer 24 is an N + type amorphous silicon layer. As shown in FIG. 2B, a second photoresist layer 26 3 is formed on the semiconductor layer 24 by using a second mask (phase shift mask). Among them, the photoresist layer 26 3 has a plurality of openings 2 5 1 on the third metal line 2 13, and the photoresist layer 2 6 3 can be divided into a thicker part of a photoresist and a thinner part of a photoresist. This thicker photoresist

-Page 10, 200421467 V. Description of the invention (7) is located above the second metal line 2 1 2 and its vicinity, and this thicker part of the photoresist is also located part of the third metal line 2 1 3 and A part of the semiconductor layer 24 in the above-mentioned anti-static discharge protection circuit area is above. In contrast, the thinner portion of the photoresist is located above the other portions of the semiconductor layer 24. Here, the thickness of the thinner photoresist layer '2 63 is 30% to 70% of the thicker photoresist layer 2 63, depending on the actual process requirements, but It is not intended to limit the invention. Next, by using the photoresist layer 2 6 3 as a mask, a part of the semiconductor layer 24, a part of the silicon layer 23, and a part of the insulating layer 22 are removed to form an exposed part of the third metal line 2 described above. The plurality of first contact holes 2 5 1 1 are in the semiconductor layer 2 4, the silicon layer 23 and the insulating layer 22, as shown in the second B diagram. In addition, since the transparent area of the phase shift mask is located above the area of the antistatic discharge protection circuit, the first contact hole 2 51 is also located in the area of the antistatic discharge protection circuit. As shown in FIG. 2C, the photoresist layer 2 6 3 is processed by ashing (ash) to remove the thinner part of the photoresist and reduce the thickness of the thicker part of the photoresist. Then, using the remaining photoresist layer 2 6 3 as a mask, a part of the semiconductor layer 24 and a part of the silicon layer 23 are removed, and a part of the insulating layer 22 is exposed. As shown in the second D diagram, the remaining photoresist layer 2 6 3 is removed, and then a second metal layer 25 is formed on the exposed insulating layer 22 and the semiconductor layer 23. The first contact hole 2 5 1 is filled with the second metal layer 25. Next, borrow

(11) Five-general invention description (8) Two-gold Use a third mask to form layer 25. In the above-mentioned case, the U-based chemical barrier layer 2 64 is formed by using the above-mentioned photoresist layer 264 as a mask. The second contact hole is said to be located on the third upper line 22 and the third metal and line 213. The second to first contact holes 2 51 do not overlap. 2, 4, I t ′ is removed from the semiconductor layer of the second contact hole 2 5 2 and the patterned photoresist layer 2 64 is removed at the same time. As shown in the second, 'on the second metal layer 25, the insulating layer 22, and the exposure spoon. A protective layer 2 7 (passivati ο η iayer) is formed over the 1Mb stone evening layer 2 3 〇 Furthermore, another step in this embodiment is to use a fourth mask to form an outer lead bonding pad on the substrate 20 on. Although this Bebe embodiment has been described above, it is not intended to limit the present invention. Hereinafter, in order to explain the present invention more clearly, this embodiment provides a method for forming a desired photoresist layer 2 6 3 by using a phase shift mask. As shown in Figure B, the phase-shifting mask is made of a transparent substrate 2 60 and low transmittance.

Page 12 200421467 V. Description of the invention (9) The transmittance pattern 261 and the high light transmittance pattern 262 are formed. Among them, the low light transmittance pattern 2 6 1 is located on the transparent substrate 2 6 0 and above the thicker portion of the photoresist layer 2 6 3, and the high light transmittance pattern 2 6 2 is located on the transparent substrate 2 6 0 and above the thinner portion of the photoresist layer 263. In addition, above the first contact hole 25 1 is a transparent substrate 2 60. In other words, here, because the phase shift mask includes three regions: a high light transmittance region, a low light transmittance region, and a transparent region, that is, the phase shift mask can define the contact in the same lithography step Holes, channel layers and pixel electrodes. For example, the light transmittance of the high light transmittance pattern 2 6 2 may be about 30% to 70%, and the light transmittance of the low light transmittance pattern 2 6 1 may be slightly lower than Thirty percent. However, the actual light transmittance of the above-mentioned pattern 2 6 1/2 6 2 can still be adjusted according to actual conditions, which is not intended to limit the present invention. In this embodiment, the high light transmittance pattern 2 6 2 is formed by a silicide layer, such as a manganese silicide layer, and the low light transmittance pattern 2 6 1 is formed by a silicide layer and a chromium layer. For example, a low-resistance chromium layer may be mentioned. In addition, comparing the first F-picture and the second F-picture, it is obvious that the structure obtained by this embodiment is different from the structure obtained by using Samsung's method. The biggest difference between the two lies in the anti-static discharge protection circuit area, especially the N + amorphous silicon layer / semiconductor layer 14 and the first metal line 11 are electrically connected, or the semiconductor layer 24 and the first The three metal wires 2 1 3 are electrically connected.

Page 13 200421467 V. Explanation of the invention (ίο) In addition, another preferred embodiment of the present invention is a lateral electric field driven liquid crystal display panel. The top view of this embodiment is the same as the top view of a conventional lateral electric field driven liquid crystal display panel, but the cross-sectional side view of this embodiment in the area of the anti-static discharge protection circuit and the cross-section of the area of the anti-static discharge protection circuit in the conventional technology The side views are not the same. As shown in FIG. 3A, the lateral electric field driven liquid crystal display panel of this embodiment includes at least: a substrate 30 (such as a transparent substrate), an active area 3 1, a plurality of conductive lines 32, and a plurality of antistatic discharge protections. Circuit 3 3. The active area 31 and the conductive line 3 2 are located in the substrate 30. Each conductive line 32 is electrically connected to the active area 31 and has an external terminal connected to the active area 31. The above-mentioned anti-static discharge protection circuit 3 3 is located on the substrate 30 and each The anti-static discharge protection circuit 3 3 is electrically connected to a conductive line 3 2. The third B diagram shows the area of the substrate's anti-static discharge protection circuit. Any anti-static discharge protection circuit 33 includes at least: the gate electrode 3 3 1. Insulating layer 332, silicon layer 333, semiconductor layer 334, conductor layer 335, and protective layer 3 3 6. Comparing the third B diagram with the first F diagram and the second F diagram, it is obvious that the conductor layer 3 3 5 (that is, the electrical connection channel) of this embodiment is completely located on the protective layer 3 3 6

Page 14 200421467 ---------- One-* ——-- _________ V. Description of the invention (π) * Bottom 'but the indium tin oxide layer produced by the method disclosed by the two stars 18 systems Interleaved with the protective layer 17. Also, 'the conductive layer 335 in this embodiment is in direct contact with the surface of the semiconductor layer 334', so that this embodiment does not need to form any dielectric layer over the semiconductor layer 334 before forming the conductive layer 335. Also, in this embodiment, the top surface of the semiconductor layer 3 3 4 is not in direct contact with any dielectric layer, especially the protective layer 336.

Also, in this embodiment, it is not necessary to form any additional contact holes in the protective layer 336 to electrically connect the plutonium conductor layer 3 3 5. In addition, since the conductive layer 335 is completely below the protective layer 336 and is located above most of the insulating layer 3 3 2, the position of the conductive layer 3 3 5 is the first to drive a liquid crystal display panel with a conventional lateral electric field. The positions of the two metal layers are very similar. In other words, when the lateral electric field-driven liquid crystal display panel is formed by a manufacturing method using only four masks, the conductive layer 3 3 5 can be used as the second metal layer.

The step is used to form the active region to form the substrate 30. At this time, the conductive layer 3 35 can enter the conductive line 32 of the domain 31, and it can further use several pixel electrodes.

Section 1.1 200421467 Five 'invention description (12) Finally, the features and advantages of the present invention compared to the conventional Samsung method are listed as follows: (a) The contact hole and the channel layer are defined in the same lithography step. Out of 0 (b), a phase shift mask is used to define the contact hole and channel layers. Among them, a transparent pattern is located above the channel layer, a low light transmittance pattern is located above the contact hole, and a high light transmittance pattern is located above the other parts of the substrate. (c) Before the second metal layer is formed, the contact hole is defined to be formed. Therefore, the contact hole is filled by the second metal layer, so the related cost of the conventional indium tin oxide layer can be saved. (d) After the protective layer is formed, no further metallization step is required to make the electrostatic discharge protection circuit electrically conductive. (f) All electrical connections are located under the protective layer. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention. Any other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following In the scope of patent application.

Page 16 200421467 Brief description of the drawings V. [Simplified description of the drawings] Figures A through F are cross-sectional views showing the basic steps of the method proposed by Samsung; Figures A through F are A schematic cross-sectional view of the basic steps of a preferred embodiment of the present invention; and FIGS. 3A to 3B are schematic diagrams of the basic structure of another preferred embodiment of the present invention. 〇Representative symbols of main parts: 10 substrates 1 1 first metal wire 1 2 insulating layer 1 3 silicon layer 1 4 N + type silicon layer 15 second metal layer 1 6 transparent substrate 1 7 protective layer 1 8 indium tin oxide Physical layer 20 Substrate 2 2 Insulation layer 23 Silicon layer 24 Semiconductor layer

Page 17 200421467 Schematic illustrations. 25 Second metal layer 2 7 Protective layer 3 0 Substrate 3 1 Active area 3 2 Conductor 3 3 Anti-static discharge protection circuit 1 6 0 Transparent substrate 161th 162th 163th 164 light 164 Hole 211 No. 212 No. 213 No. 251 No. 2 5 2 No. 2 6 0 through 2 6 1 low 2 6 2 high 2 6 3 light 2 6 4 light 331 gate 3 3 2 absolutely 3 3 3 silicon one pattern two pattern «_ resistance Layer hole 1 metal wire 2 metal wire 3 metal wire 1 contact hole 2 contact hole bright substrate light pattern light transmittance pattern resist layer resist layer electrode layer

Page 18 200421467 Brief description of the drawings 334 Semiconductor layer 3 3 5 Conductor layer 3 3 6 Protective layer 〇

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Claims (1)

200421467 6. Scope of patent application 1. A method of using four masks in the first domain of a square area, the three-layer gold photoresist layer in the domain, and the bulk layer L method, providing the use of a metal and a complex sequential number of lines to use a resist layer The substrate having the plurality of steps includes the following steps: a substrate, and the process of forming a lateral electric field to drive the liquid crystal display panel: the substrate includes at least the following three regions: a first second region and a third region; a first metal A layer on the substrate; a first mask patterning the first metal layer to form a plurality of lines in the first region, and a plurality of second metal lines in the second region and a plurality of third metal lines are formed In the third region; forming an insulating layer, a chipping layer, and a semiconductor layer on the substrate and the first metal line, the plurality of second metal lines and the plurality of first portions; a second mask having a plurality of portions A thick portion of light includes several second gold and third gold cubes, and the thin portion uses the photoresist layer as a shielding insulating layer to reduce the thickness of the plurality and the plurality of ashes in the insulating layer. Part A photoresist layer is formed on the semiconductor layer through the ashing portion, and the photoresist layer is opened on the plurality of third metal lines. The photoresist and a thin portion of the photoresist belong to the line. And the area lines adjacent to the plurality of second metal lines and the semiconductor photoresist located in the third area are located in the cover of the other part of the semiconductor layer, removing a part of the semiconductor layer, the semiconductor layer and the semiconductor layer The third metal lines are exposed from the semiconductor layer and the first contact holes of the silicon layer; the photoresist layer is removed to remove the thin portion of the photoresist and the thickness; the treated photoresist layer is a mask removal portion The half Page 20 200421467 VI. Patent application scope Conductor layer and the silicon layer to expose part of the insulating layer; removing the photoresist layer after the above ashing treatment; forming a second metal layer on the exposed insulating layer And the semiconductor layer, wherein the second metal layer is filled in the plurality of first contact holes; and a third mask is used to pattern the second metal layer to form a plurality of second contact holes in the second metal Within the layer and on the plurality of second metal lines and the plurality of third metal lines, wherein the plurality of second contact holes and the plurality of first contact holes do not overlap; and the exposure is removed by the plurality of second contact holes A part of the semiconductor layer; and forming a protective layer over the second metal layer, the exposed insulating layer and the silicon layer. 2. A method of forming a lateral electric field to drive a liquid crystal display panel using a four-mask process as described in item 1 of the scope of the patent application, wherein the first region is a common line / pixel region and the second region is a transistor. Region, the third region is an anti-static discharge protection circuit region. 3. The method for forming a lateral electric field to drive a liquid crystal display panel using a four-mask process as described in item 1 of the scope of the patent application, which further includes forming a plurality of outer wire bonding pads on the substrate using a fourth mask. A step of. 4. The method for forming a horizontal electric field driven liquid crystal display panel using a four-mask process as described in item 1 of the scope of patent application, wherein the second mask is a shift Page 21 200421467 6. Scope of patent application Phase mask. 5. The method of forming a lateral electric field to drive a liquid crystal display panel using a four-mask process as described in item 4 of the scope of the patent application, wherein the phase-shift mask is composed of a transparent substrate, a high light transmittance pattern and a Formed by a low light transmittance pattern, the high light transmittance pattern is located on the transparent substrate and above the thin portion of the photoresist, the low light transmittance pattern is located on the transparent substrate and is located on the transparent substrate Above the thick photoresist. 6. The method of forming a lateral electric field to drive a liquid crystal display panel using a four-mask process as described in item 5 of the scope of the patent application, wherein the light transmittance of the southern light transmittance pattern is 30% to 30%. seventy. 7. The method for forming a lateral electric field driven liquid crystal display panel using a four-mask process as described in item 6 of the scope of patent application, wherein the light transmittance of the low light transmittance pattern is less than 30%. 8. The method for forming a lateral electric field driven liquid crystal display panel using a four-mask process as described in item 1 of the scope of the patent application, wherein the high light transmittance pattern is formed by a silicide layer. 9. The method for forming a transverse electric field driven liquid crystal display panel using a four-mask process as described in item 8 of the scope of the patent application, wherein the silicide layer is a silicide layer. Page 22, 200421467 VI. Patent application scope 10 · The method of forming a lateral electric field to drive a liquid crystal display panel using a four-mask process as described in item 1 of the patent application scope, wherein the low-light-transmittance pattern is composed of a stone compound And a chromium layer. 1 1 · A method of forming a lateral electric field to drive a liquid crystal display panel using a four-mask process as described in item 10 of the scope of patent application ', wherein the complex layer is a low-resistance chromium layer. 12. The method for forming a lateral electric field driven liquid crystal display panel using a four-mask process as described in item 1 of the scope of the patent application, wherein the semiconductor layer is an N + type amorphous silicon layer. 13. The method for forming a lateral electric field-driven liquid crystal display panel using a four-mask process as described in item 1 of the scope of the patent application, wherein the semiconductor layer is an amorphous silicon layer. 1 4. A lateral electric field-driven liquid crystal display panel includes: a substrate; an active area on the substrate; a plurality of conductive lines, the plurality of conductive lines are located on the substrate, each of which A conductive line is electrically connected to the active area and has an end point located outside the active area; and a plurality of anti-static discharge protection circuits, the plurality of anti-static discharge protection circuits 200421467 6. The scope of the patent application is located on the substrate. 'Among them, the anti-static discharge protection circuit is electrically connected to any one of the conductive lines, and any of the anti-static discharge protection circuit includes at least: a gate An electrode layer on the substrate; an insulating layer on the substrate and the gate electrode, the insulating layer having a first contact hole and exposing the gate electrode; a silicon layer on the exposed insulation A semiconductor layer on the silicon layer, wherein the semiconductor layer has a second contact hole and exposing the silicon layer; a conductor layer on the semiconductor layer, and the conductor layer fills the first contact hole And a protective layer on the conductor layer and the silicon layer exposed by the second contact hole. 15. The lateral electric field-driven liquid crystal display panel described in item 14 of the patent application scope, wherein the conductor layer directly contacts the surface of the semiconductor layer and the sidewall of the first contact hole. 16. The lateral electric field-driven liquid crystal display panel according to item 14 of the scope of patent application, wherein the stone layer is an amorphous stone layer. 17. The lateral electric field-driven liquid crystal display panel according to item 14 of the scope of patent application, wherein the semiconductor layer is an N + type amorphous silicon layer. _1 Page 24 200421467 VI. Patent application scope 1 8. As described in the patent application scope. The lateral electric field-driven liquid crystal display panel described in item 14 wherein the conductor layer is used to form the plurality of conductive lines in the active area. . 19. The lateral electric field driven liquid crystal display panel according to item 14 of the scope of patent application, wherein the conductor layer is used to form a plurality of pixel electrodes on the substrate. Page 25