JP4264675B2 - Liquid crystal display device and manufacturing method thereof - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a large-screen active matrix liquid crystal display device having a wide viewing angle and high image quality at low cost.
[0002]
[Prior art]
In a conventional active matrix liquid crystal display device, a gate insulating film, a semiconductor film, and a passivation film are deposited on the entire surface of the substrate except for the periphery of one substrate on which active elements are formed. In the process of forming the scanning line first, a step of removing the gate insulating film deposited on the scanning line terminal portion is necessary to connect to the driving IC circuit. (FIGS. 1 and 2 are cross-sectional views of an active element substrate of a conventional liquid crystal display device.) It is necessary to remove the gate insulating film also at the junction between the wirings of the protection transistor for static electricity countermeasures.
[0003]
[Problems to be solved by the invention]
As shown in FIGS. 1 and 2, the conventional TN mode active element substrate requires five photomask processes in all processes. In the active element substrate in the horizontal electric field liquid crystal mode, the photomask process is required four times or more in all processes. As the liquid crystal display screen is enlarged, the number of liquid crystal display elements that can be taken from one glass substrate is reduced, and the price of the large liquid crystal display element has become very high. Furthermore, the amount of static electricity generated when the glass substrate becomes large is very large, and dust adheres and breaks down frequently, resulting in a low yield of large liquid crystal display elements.
[0004]
When there are many photomask processes, a large number of expensive exposure apparatuses are required, and the amount of initial investment increases. Since the area of the clean room in the manufacturing plant also increases, the running cost also increases. Unless the time from the introduction of the glass substrate to the completion of the active element substrate is shortened as much as possible, a large number of stockers are required for storage.
[0005]
When a glass substrate becomes larger, when a silicon nitride film or an amorphous silicon semiconductor film is deposited by plasma CVD, since the expansion coefficient is different from that of the glass substrate, stress is generated after the deposition, and the entire substrate is distorted. Arise. Since the stress generation rate is different between the central portion of the glass substrate and the peripheral portion of the glass substrate, the dimensional change does not occur uniformly throughout the effective pixel region.
For this reason, there was a problem of misalignment between photomasks.
[0006]
The present invention provides a means for solving these problems, and the object of the present invention is to increase the investment efficiency of a large-sized liquid crystal display device manufacturing plant and to make an ultra-large and ultra-wide viewing angle liquid crystal display device inexpensive. An object of the present invention is to provide a method capable of producing with high yield.
[0007]
[Means for Solving the Problems]
In order to solve the above problems and achieve the above object, the present invention uses the following means.
[0008]
A scanning line and a video signal wiring on the substrate, a thin film transistor formed at each intersection of the scanning line and the video signal wiring, a pixel electrode connected to the thin film transistor, and at least a part facing the pixel electrode And a liquid crystal layer sandwiched between the active matrix substrate and the counter substrate, and a liquid crystal layer sandwiched between the active matrix substrate and the active matrix substrate. ,
[Means 1] When the gate insulating film of the thin film transistor element is deposited on the substrate, it is partially deposited only on the local area including the effective pixel region, and the semiconductor layer and the passivation protection film of the thin film transistor element are deposited on the entire surface of the substrate.
[0009]
[Means 2] When the gate insulating film and the semiconductor layer of the thin film transistor element are deposited on the substrate, they are partially deposited only on the local area including the effective pixel region, and the passivation protection film layer is deposited on the entire surface of the substrate.
[0010]
[Means 3] When the gate insulating film and the passivation protection film layer of the thin film transistor element are deposited on the substrate, they are partially deposited only on the local area including the effective pixel region, and the semiconductor layer is deposited on the entire surface of the substrate.
[0011]
[Means 4] In the manufacturing method described in the means 3, the passivation film region is deposited wider than the gate insulating film partially deposited only in the local portion including the effective pixel region.
[0012]
[Means 5] When the gate insulating film, the semiconductor layer, and the passivation protective film layer of the thin film transistor element are deposited on the substrate, they are partially deposited only on the local area including the effective pixel region.
[0013]
[Means 6] In the manufacturing method described in the means 5, the passivation film region is deposited wider than the gate insulating film partially deposited only in the local portion including the effective pixel region.
[0014]
[Means 7] In a liquid crystal display device manufactured by the manufacturing method described in any one of means 1 to 6, an anti-static protective transistor element connecting the common electrode and the scanning line, the common electrode, and the video signal wiring And the protection transistor element for static electricity countermeasures connected to each other are completely covered with a passivation film layer.
[0015]
[Means 8] In a liquid crystal display device manufactured by the manufacturing method described in any one of the means 1 to 6, an anti-static protective transistor element connecting the common electrode and the scanning line, the common electrode, and the video signal wiring Are arranged on two or more sides around the boundary of the gate insulating film deposited locally.
[0016]
[Means 9] In a liquid crystal display device manufactured by the manufacturing method according to any one of the means 1 to 6, the connection portion of the protection transistor element for static electricity countermeasures connecting the common electrode and the scanning line, the common electrode, The connection portion of the anti-static protection transistor element connecting the video signal wiring is arranged outside the region of the locally deposited gate insulating film.
[0017]
[Means 10] In a liquid crystal display device manufactured by the manufacturing method described in means 1 to 9, a seal region for forming a liquid crystal cell by bonding two substrates is formed around a locally deposited gate insulating film. It was placed on the boundary or outside the gate insulating film deposition region and inside the passivation deposition region.
[0018]
[Means 11] The film thickness of the positive photoresist is changed to three or more levels by changing the amount of light transmitted through the photomask to three or more levels of complete transmission, semi-transmission and complete blocking.
[0019]
[Means 12] According to the manufacturing method described in the means 11, the steps of the scanning lines, the semiconductor regions of the active elements, and the respective electrodes constituting the liquid crystal display element such as the video signal wiring and the pixel electrode intersect with each other. The amount of light transmitted through the partial photomask is changed in three steps or more, and after developing the positive photoresist, the thickness of the photoresist is changed in three steps or more.
[0020]
[Means 13] By the method described in means 11, the amount of light transmitted through the photomask in the channel portion of the thin film transistor element connecting the video signal wiring and the pixel electrode is increased, and after the positive photoresist development, the positive photoresist film in the channel portion of the thin film transistor element The thickness was reduced.
[0021]
[Means 14] Using the method described in the means 3, 4, 5, 6 and 13, the video signal wiring and the pixel electrode are simultaneously separated and formed. ⁺ Remove the layer. This process and the photomask process for forming the scanning lines are included, and all the processes are completed in two photomask processes.
[0022]
[Means 15] Using the method described in the means 1, 2 and 13, the video signal wiring and the pixel electrode are formed simultaneously, and n ⁺ After removing the layer, a passivation protective film is deposited on the entire surface of the substrate. Thereafter, a contact hole is formed in the terminal portion for connection to the driving IC circuit.
[0023]
[Means 16] Using the method described in the means 15, the video signal wiring and the drain electrode are simultaneously formed separately, and the channel portion n ⁺ After removing the layer, a passivation protective film is deposited on the entire surface of the substrate. After that, a contact hole for a terminal portion for connecting to the driving IC circuit and a contact hole for connecting the transparent pixel electrode and the drain electrode are formed simultaneously. Then, a transparent conductive film is deposited to form a transparent pixel electrode and a terminal part electrode.
[0024]
[Means 17] After the video signal wiring and the pixel electrode are formed at the same time by using the method described in the means 3, 4, 5, 6, the metal film of the channel portion of the thin film transistor element and n ⁺ Remove the layer. Then, a passivation protection film is partially deposited only on the local area including the effective pixel area.
[0025]
[Means 18] When the video signal wiring and the drain electrode are simultaneously formed by using the method described in the means 3, 4, 5, 6, and then the transparent conductive film is deposited and the video signal wiring and the pixel electrode are patterned. Metal film and n in the channel portion of the thin film transistor portion ⁺ Remove the layer. Thereafter, a passivation protection film is partially deposited only on the local area including the effective pixel region.
[0026]
[Means 19] Using the method described in the means 2, 5 and 6, the gate insulating film and the semiconductor layer are partially deposited only in the local area including the effective pixel region, and then the video signal wiring and the pixel electrode are formed simultaneously. . N exposed on the surface ⁺ After removing the layer, a passivation film is partially deposited on the entire surface of the substrate or only on the local area including the effective pixel region. Then, an extra passivation film and a semiconductor layer are removed to form a channel portion of the thin film transistor element, a video signal wiring, and a pixel electrode.
[0027]
[Means 20] Using the method described in the means 1, 3 and 4, the gate insulating film is partially deposited only on the local area including the effective pixel region, and then the semiconductor layer is deposited on the entire surface of the substrate. After that, the video signal wiring and the pixel electrode are formed at the same time and then exposed to the surface ⁺ Remove the layer. Next, a passivation film is partially deposited on the entire surface of the substrate or only on the local area including the effective pixel region. Then, an extra passivation film and a semiconductor layer are removed to form a channel portion of the thin film transistor element, a video signal wiring, and a pixel electrode.
[0028]
[Means 21] Using the method described in the means 19 and 20, the video signal wiring and the drain electrode are formed simultaneously, and then exposed to the surface. ⁺ Remove the layer. Next, a passivation film is partially deposited on the entire surface of the substrate or only locally including the effective pixel region. Thereafter, in order to form a channel portion of the thin film transistor element, a video signal wiring, and a drain electrode, an extra passivation film and a semiconductor layer are removed, and then a transparent pixel electrode is formed.
[0029]
[Means 22] Using the method described in the means 5 and 6, the gate insulating film and the semiconductor layer are partially deposited only on the local area including the effective pixel region, and then the channel portion of the thin film transistor element is patterned. Thereafter, the video signal wiring and the pixel electrode are formed at the same time, and then the channel portion n of the thin film transistor element is formed. ⁺ Remove the layer. Then, a passivation film is partially deposited only on the local area including the effective pixel area.
[0030]
[Means 23] Using the method described in the means 3 and 4, the gate insulating film is partially deposited only on the local area including the effective pixel region, and then the semiconductor layer is deposited on the entire surface of the substrate. Thereafter, after patterning the channel portion of the thin film transistor element, the video signal wiring and the pixel electrode are formed simultaneously. Then n of the channel portion of the thin film transistor ⁺ After removing the layer, a passivation film is deposited only on the local area including the effective pixel area.
[0031]
[Means 24] Using the method described in Means 1 and 2, after the gate insulating film is partially deposited only on the local area including the effective pixel region, the semiconductor layer is partially applied on the entire surface of the substrate or only on the local area including the effective pixel region. To deposit.
Then, after patterning the channel portion of the thin film transistor and simultaneously forming the video signal wiring and the pixel electrode, the n of the channel portion of the thin film transistor is formed. ⁺ Remove the layer. Next, after depositing a passivation film on the entire surface of the substrate, a contact hole is formed in the terminal portion in order to connect to the driving IC.
[0032]
[Means 25] Using the method described in the means 5 and 6, the gate insulating film and the semiconductor layer are partially deposited only on the local area including the effective pixel region, and then the channel portion of the thin film transistor is patterned. Next, after the video signal wiring and the pixel electrode are formed at the same time, n of the channel portion of the thin film transistor is formed. ⁺ After the layer is removed, a passivation film is partially deposited only on the local area including the effective pixel area. Thereafter, a common electrode is formed on the passivation film.
[0033]
[Means 26] After the gate insulating film is partially deposited only on the local area including the effective pixel region, the semiconductor layer and the etching stopper layer are partially deposited on the entire surface of the substrate or only on the local area including the effective pixel region. N to take ⁺ In the case of ion implantation, the layer is partially implanted only in the local area including the effective pixel region. n ⁺ When the layer is deposited by the plasma CVD method, it is partially deposited on the entire surface of the substrate or only on the local area including the effective pixel region.
[0034]
[Means 27] Using the method described in the means 26, the video signal wiring and the pixel electrode are simultaneously patterned, and then exposed to the surface. ⁺ Layers and n ⁺ By removing both of the semiconductor layers below the layer, the channel portion of the thin film transistor element, the video signal wiring, and the pixel electrode are formed independently and simultaneously.
[0035]
[Means 28] After the video signal wiring and the pixel electrode are simultaneously formed by using the method described in the means 26 and 27, the passivation is partially deposited on the entire surface of the substrate or only in the local area including the effective pixel region. Next, in order to connect to the drive circuit IC, an extra passivation film on the connection terminal portion and n ⁺ The layer and the semiconductor layer are removed.
[0036]
[Means 29] For each display pixel, two or more gate electrodes of the thin film transistor are arranged in a row, and two or more channel regions of the thin film transistor are formed in a row, and each drain is attached to each of the two or more channels. The electrodes were connected to each other and joined to the pixel electrode.
[0037]
[Means 30] A horizontal electric field method is used for the liquid crystal display panel produced by the methods 1 to 6 and 11 to 28.
[0038]
[Means 31] A twisted nematic liquid crystal method, a ferroelectric liquid crystal method, an antiferroelectric liquid crystal method, or a vertical alignment liquid crystal method is used for the liquid crystal display panel produced by the methods of means 16 and 21.
[0039]
[Means 32] A scanning line of a liquid crystal display element produced by the methods of means 1 to 6 and means 11 to 28 is formed of a two-layer structure of aluminum (or an alloy of aluminum) and titanium (or titanium alloy), or aluminum (or 3 layer structure of aluminum (alloy), titanium (or titanium alloy) and molybdenum (or molybdenum alloy), or 3 layer structure of aluminum (or aluminum alloy), chromium (or chromium alloy) and molybdenum (or molybdenum alloy) The common electrode facing the pixel electrode is a single layer structure of titanium (or titanium alloy), or a two-layer structure of titanium (or titanium alloy) and molybdenum (or molybdenum alloy), or chromium (or chromium alloy) and molybdenum. (Or molybdenum alloy).
[0040]
[Means 33] A scanning line of a liquid crystal display element produced by the methods of means 1 to 6 and means 11 to 28 is formed of a three-layer structure of titanium (or titanium alloy), copper (or copper alloy) and titanium (or titanium alloy). Or it is made of a three-layer structure of chromium (or chromium alloy), copper (or copper alloy) and molybdenum (or molybdenum alloy), and the common electrode facing the pixel electrode is a single layer structure of titanium (or titanium alloy), or titanium. A two-layer structure of (or titanium alloy) and molybdenum (or molybdenum alloy) or a two-layer structure of chromium (or chromium alloy) and molybdenum (or molybdenum alloy) was employed.
[0041]
[Means 34] Two-layer structure of titanium (or titanium alloy) and aluminum (or aluminum alloy) or titanium (or titanium alloy) and molybdenum (or the video signal wiring of the liquid crystal display device manufactured by the method of means 1 to 28 A two-layer structure of molybdenum alloy) or a two-layer structure of chromium (or chromium alloy) and molybdenum (or molybdenum alloy) was used.
[0042]
[Means 35] A three-layer structure of titanium (or titanium alloy), aluminum (or aluminum alloy) and titanium (or titanium alloy), or titanium (or titanium alloy) for the video signal wiring of the liquid crystal display device manufactured by the method of means 1 to 28 Or titanium alloy), aluminum (or aluminum alloy) and molybdenum (or molybdenum alloy), or a three-layer structure of titanium (or titanium alloy), aluminum (or aluminum alloy) and chromium (or chromium alloy), or Three-layer structure of titanium (or titanium alloy) and molybdenum (or molybdenum alloy) and titanium (or titanium alloy), or three layers of titanium (or titanium alloy), chromium (or chromium alloy) and molybdenum (or molybdenum alloy) Structure was used.
[0043]
[Means 36] In the liquid crystal display device manufactured by the method according to any one of the means 1 to 9, the region where the gate insulating film is deposited is localized in the effective pixel region, the terminal portion region of the video signal wiring, and the protection active element region for static electricity countermeasures Limited.
[0044]
[Means 37] In the liquid crystal display device manufactured by the method described in any one of the means 1 to 9, the distance from the gate insulating film deposition boundary to the scanning line terminal end, and the gate insulating film deposition boundary The distance to the junction terminal end was set to be 2 mm or more.
[0045]
[Means 38] In the liquid crystal display device manufactured by the method described in any one of means 1 to 6, a portion connecting the common electrode intersecting the scanning line and the common electrode intersecting the video signal wiring is locally It was installed outside the area of the deposited gate insulating film.
[0046]
[Means 39] Two-layer structure of titanium silicide and aluminum (or aluminum alloy) or two layers of molybdenum silicide and aluminum (or aluminum alloy) in the video signal wiring of the liquid crystal display panel manufactured by the method described in means 1 to 28 A structure, or a two-layer structure of chromium silicide and aluminum (or aluminum alloy), a two-layer structure of titanium silicide and molybdenum (or molybdenum alloy), or a two-layer structure of chromium silicide and molybdenum (or molybdenum alloy) is used.
[0047]
[Action]
A cross-sectional view of a conventional thin film transistor element substrate for twisted nematic liquid crystal mode is shown in FIG. A manufacturing method that deposits three layers of a gate insulating film, a semiconductor film, and a passivation film on the entire surface of the glass substrate. However, the photomask process is required 5 times in all processes, and it is impossible to further reduce the cost. A cross-sectional view of the thin film transistor element substrate for the horizontal electric field mode liquid crystal mode is as shown in FIG. Also in this case, as in FIG. 1, a manufacturing method is used in which the three layers of the gate insulating film, the semiconductor film, and the passivation film are deposited on the entire surface of the glass substrate. In the horizontal electric field method, the pixel electrode (transparent electrode) used in FIG. 1 is not necessary. Therefore, the photomask process is completed once, and the process is completed in four photomask processes. However, in this case, it is impossible to connect the scanning line and the common electrode. Similarly, connection between the video signal wiring and the common electrode is impossible. For this purpose, five photomask steps are required to form the contact electrode 13 after forming the contact hole in the scanning line terminal portion and the video signal wiring terminal portion and to install the protection transistor for preventing static electricity. In other words, no matter which liquid crystal mode is adopted, in order to achieve stable production without reducing yield, there is a limit to cost reduction if the conventional process is adopted.
[0048]
By using means 1 to 9, the process of opening the contact hole in the terminal portion is not necessary, and the process can be greatly shortened. Moreover, even if the process is shortened, the protection transistor for static electricity countermeasures can be formed on the substrate as in the conventional case, so that the yield is not lowered.
By depositing a thick gate insulating film on the minimum necessary area, the stress on the glass substrate can be reduced, so that the deformation of the pattern is also reduced. For this reason, the amount of misalignment between photomasks is also reduced, so that display unevenness caused by misalignment is greatly reduced. Similarly, since the misalignment amount between the color filter substrate and the thin film transistor substrate as the counter substrate is also reduced, the yield in the liquid crystal cell process is greatly improved.
[0049]
By using means 10, it becomes easy to make the cell gap in the seal region uniform, so that cell gap defects in the liquid crystal cell process can be reduced.
[0050]
By using the means 3 to 9 and the means 11 to 14, an anti-static protective transistor can be formed on the thin film transistor element substrate, and the entire process can be realized with only two photomask processes. This process makes it possible to significantly shorten the process compared to the prior art, and can realize a significant cost reduction and productivity improvement. The clean room area of the production plant can be reduced, and the expensive investment in the washer, resist coater, developing device, and exposure device can be reduced to less than half of the conventional one, so the initial investment cost can be greatly reduced. Furthermore, since a storage stocker or the like for storage is not required, adhesion of dust to a large substrate is reduced and yield is improved. The cleaning process is also drastically reduced, so the amount of pure water used is reduced and the running cost is greatly reduced. By combining with an inexpensive printing color filter, an active matrix liquid crystal panel (lateral electric field liquid crystal mode) can be realized at a lower production cost than a simple matrix liquid crystal panel (STN mode). This makes it possible to replace a home TV with an active matrix liquid crystal panel from a cathode ray tube (CRT).
[0051]
By using the means 15, it becomes possible to make a more compact liquid crystal panel.
[0052]
By using means 16 and 21, a conventional twisted nematic liquid crystal mode liquid crystal panel can be produced in four photomask steps. A small cost reduction can be achieved.
[0053]
By means 17 and 18, the area where the gate electrode and the pixel electrode (drain electrode) are bulky can be controlled with high precision, so that display unevenness is drastically reduced and the yield is improved.
[0054]
By means 19, 20 and 21, an anti-static protective transistor can be formed on the thin film transistor element substrate, and the entire process can be completed in three photomask processes. Significant cost reduction and significant productivity improvement can be realized. Further, in this step, the passivation film does not cover the entire effective screen and does not apply a large stress to the glass substrate. Therefore, the glass substrate dimensional change is the smallest, and the alignment error generated when the color filter substrate and the thin film active matrix substrate are bonded in the liquid crystal cell process when the liquid crystal display screen becomes very large can be minimized. In this process, the photomask alignment error between the gate electrode and the pixel electrode (drain electrode) is very high, and the process stability is very high, so that display unevenness is generated and a high yield can be realized.
[0055]
By using the means 22, 23, 24, 25, a protection transistor for preventing static electricity can be formed on the thin film transistor element substrate, and the entire process can be completed in 3 to 4 photomask processes. In this step, the common electrode can be formed last, and the degree of freedom of the process is very large. Since the gap between the steps after pattern formation can be minimized, wiring breakage is unlikely to occur, and the rubbing process after alignment film formation in the liquid crystal cell process is very easy to perform, so the yield can be maximized. is there.
[0056]
By using the means 26, 27 and 28, a protection transistor for preventing static electricity can be formed on the thin film transistor element substrate, and the entire process can be completed in 3 to 4 photomask processes. In this process, the thin film semiconductor layer can be formed as thin as about 500 mm, and n ⁺ Since the layer does not remain in the channel portion, the degree of uniformity requirement on the entire surface of the substrate during dry etching is relaxed. It is possible to easily change to the polysi thin film transistor process in combination with an excimer laser.
By using the backside exposure technology, self-alignment technology can be applied and an ultra-large-screen LCD screen can be realized.
[0057]
In the case of an ultra-large screen by using means 29, even if misalignment occurs locally due to a change in substrate dimensions, the capacitance formed by the drain electrode and the gate electrode does not change. Does not occur.
[0058]
By using the means 32 to 35, the resistance of the scanning line can be greatly reduced, and the resistance of the common electrode can be greatly reduced.
Further, since the electrode film thickness of the liquid crystal drive electrode inside the pixel and the pixel common electrode facing the liquid crystal drive electrode can be reduced, the rubbing process in the liquid crystal cell process becomes very easy. For this reason, since the rubbing processing density and uniformity can be greatly increased, it is possible to obtain a uniform image with good reliability and reproducibility.
[0059]
By using the means 34, 35, 39, film peeling at the boundary portion of the gate insulating film deposition region can be prevented. In particular, a silicide compound of titanium or a refractory metal has a very strong adhesive force with a glass substrate or a plasma CVD film (silicon oxide film, silicon nitride film) and does not peel off. In the present invention, the film peeling after the electrode pattern formation at the boundary portion of the deposition region is the biggest problem, and the types of metals that can be used are limited. Even if aluminum or aluminum alloy is used for the video signal wiring, the film does not peel off. ⁺ Because direct bonding with the layer is not possible, aluminum and n ⁺ A refractory metal layer or a refractory metal silicide compound layer is required between the layers.
[0060]
By means of means 36, the gate insulating film deposition range is expanded to the area of the video signal wiring terminal and the protection active element for preventing static electricity, so that there is no crossing at the boundary between the video signal wiring terminal section and the gate insulating film deposition area. The number of defects decreases drastically. This significantly improves the yield.
[0061]
By means 37, an error in the dimensional processing accuracy of the glass substrate and the accuracy of the deposition position on the local portion of the gate insulating film can be sufficiently guaranteed. Since the gate insulating film deposition temperature in the P-CVD apparatus is around 300 ° C., this value is a conventional value in consideration of the deformation of the tool of the apparatus and the difference in thermal expansion coefficient. When the value is smaller than this value, a gate insulating film is deposited on the entire surface of the scanning line terminal portion or an effective junction area with the TAB is reduced, so that contact failure frequently occurs and horizontal stripe unevenness of the image occurs. If the means 37 is used, contact failure does not occur and horizontal stripe unevenness is eliminated.
[0062]
【Example】
[Embodiment 1] FIGS. 3, 50, 51, 52, 53, 54 and 55 are a sectional view and a plan view of a first embodiment of the present invention. After patterning the scanning line (gate electrode), the gate insulating film (4) and the amorphous silicon semiconductor film (5) and n ⁺ Amorphous silicon film (6) is partially deposited locally. After the deposition, the metal electrode is exposed at the terminal portion (3) of the scanning line. Then, a metal film is deposited by a sputtering method in order to simultaneously form the video signal wiring (7), the liquid crystal drive electrode (17), and the scanning line terminal joint metal electrode (19). Method 11 described in means 11 and means 13 Using FIG. 30, the channel part of the thin film transistor element is formed by only one photomask process, and the extra metal film and n in the channel part are formed. ⁺ The layer is removed. In the photomask used in this process, the amount of transmitted light changes in three or more stages as shown in FIGS. 25 and 26 are cross-sectional views of the channel portion of the photomask transistor element. FIG. 29 is a cross-sectional view of the positive resist exposed and developed using this photomask. Since the resolving power of an exposure apparatus used in a thin film semiconductor is about 2 to 3 μm at the maximum, the average amount of transmitted light is adjusted using a pattern of about 1/10 to 1/5 of the resolving power when making a photomask of the type shown in FIGS. To do. A semi-transmitted light amount region (23) is formed with a line width of about 0.2 to 0.5 μm and a space width of about 0.5 to 1 μm. When making a photomask of the type as shown in FIGS. 26 and 28, a silicon nitride film can be used as the film of the semi-transmission light quantity region (24). The amount of transmitted UV light can be freely adjusted by changing the component ratio of silicon and nitrogen. As shown in FIG. 29, the positive resist film thickness {circle around (30)} of the unexposed portion is about 1.2 to 2.0 μm, and the positive resist film thickness {circle around (31)} of the exposed region in the semi-transmission light quantity region is 0.05 to 0. Use around 2 μm. n ⁺ The metal layer above the layer is processed by wet etching to leave the metal layer where necessary. Next, dilute hydrofluoric acid with n ⁺ The layer and the non-doped semiconductor layer may be wet etched or n by dry etching. ⁺ The layer and the non-doped semiconductor layer may be removed. Then, the thin remaining positive resist in the semi-transmitted light amount region (24) in the channel portion of the thin film transistor is removed by plasma ashing. The metal layer of the channel part and n ⁺ The layer is removed by the same wet and dry etching as before. Finally, a passivation film is locally partially deposited to complete the active element substrate. The photomask process is only twice in all steps.
[0063]
[Embodiment 2] FIG. 6 is a cross-sectional view of a second embodiment of the present invention. A manufacturing method is employed in which after the last passivation film of Example 1 is deposited on the entire substrate, a contact hole is formed in the scanning line terminal portion. The photomask process is only three times in all steps.
[0064]
[Embodiment 3] FIG. 4 is a cross-sectional view of a third embodiment of the present invention. In Example 1, the scanning line (2) and the common electrode (18) were formed simultaneously by one photomask process using the same metal material. In Example 3, the common electrode was formed first. Thereafter, the scanning line base insulating film {circle around (20)} is locally deposited. The photomask process is three times in all steps. Since the short circuit due to the pattern defect of the common electrode (18) and the scanning line (2) is drastically reduced, the yield is greatly improved.
[0065]
[Embodiment 4] FIG. 5 is a sectional view of a fourth embodiment of the present invention. As in the third embodiment, the scanning line (2) and the common electrode (18) are not formed at the same time, but the scanning line (2) is formed first and then the common electrode (18) is formed at the end of the process. is doing. The photomask process is three times in all steps. Since the short circuit due to the pattern defect of the common electrode (18) and the scanning line (2) is drastically reduced, the yield is greatly improved. Since the material for the common electrode can be freely selected as in the third embodiment, the degree of freedom of the process is expanded.
[0066]
[Embodiment 5] FIG. 7 is a cross-sectional view of a fifth embodiment of the present invention. Examples 1 to 4 are horizontal electric field type liquid crystal display modes, but Example 5 is applicable to vertical electric field type liquid crystal display modes (TN mode, vertical alignment mode, ferroelectric mode, antiferroelectric mode). . After forming the video signal wiring (7) and the drain electrode (8) and depositing the passivation film, the passivation film on the drain electrode is removed by making a contact hole (10). Finally, a transparent pixel electrode (14) is formed. The photomask process is four times in all steps.
[0067]
[Embodiment 6] FIGS. 56, 57, 58, 59, 60 and 61 are plan views of a sixth embodiment of the present invention. The cross-sectional view is the same as FIG. 3 and FIG. The difference from Examples 1 to 5 is that the process shown in FIG. 30 is not used. After the metal film is deposited and patterned in order to form the video signal wiring (7), the liquid crystal drive electrode (17), and the scanning line terminal junction metal (19) at the same time, it is left in the channel region of the thin film transistor element. Metal film and n ⁺ Remove the layer.
On the contrary, after depositing a metal film, the metal film in the channel region of the thin film transistor element and n ⁺ It is also possible to remove the layer and then pattern the video signal wiring, liquid crystal drive electrode, and scanning line terminal bonding metal.
[0068]
[Embodiment 7] FIGS. 8, 68, 69, 70, 71, 72, and 73 are a sectional view and a plan view of a seventh embodiment of the present invention. After patterning the scanning line (2), the gate insulating film (4) and the amorphous silicon semiconductor film (5) and n ⁺ Amorphous silicon film (6) is partially deposited locally as shown in FIGS. The metal electrode is exposed at the terminal portion (3) of the scanning line after deposition. Next, in order to form the video signal wiring (7) and the liquid crystal driving electrode (17) at the same time, a metal film is deposited using a sputtering method. N where the metal film disappears after the metal film is patterned using wet etching or dry etching ⁺ The layer is similarly removed using wet or dry etching. Then, a passivation film is deposited on the entire surface of the substrate, and the passivation film and the amorphous silicon semiconductor film in an extra region are removed in order to separate the channel portion of the thin film transistor element, the video signal wiring, and the liquid crystal driving electrode. The photomask process can be done three times in all processes.
[0069]
[Eighth Embodiment] FIG. 9 is a sectional view of an eighth embodiment of the present invention. After locally depositing the gate insulating film locally as shown in FIGS. 92 and 93, the amorphous silicon semiconductor film and n ⁺ The amorphous silicon film is deposited on the entire surface of the substrate. Next, after forming the video signal wiring and the liquid crystal driving electrode, a passivation film is deposited on the entire surface of the substrate. Then, in order to separate the channel portion of the thin film transistor element, the video signal wiring, and the liquid crystal drive electrode, the extra passivation film and the amorphous silicon semiconductor film are removed. At the same time, the excess passivation film and amorphous silicon semiconductor film covering the terminal electrode of the scanning line are also removed. The passivation film may be a local partial deposition instead of the entire surface deposition.
[0070]
[Embodiment 9] FIG. 11 is a sectional view of a ninth embodiment of the present invention. As in the third embodiment, the common electrode is first formed and then the scanning line base insulating film {circle around (20)} is locally deposited. The subsequent process is exactly the same as in Example 7. Although the photomask process is performed four times in all steps, the yield is greatly improved because the short circuit due to the pattern defect of the common electrode (18) and the scanning line (2) is drastically reduced.
[0071]
[Embodiment 10] FIG. 12 is a sectional view of a tenth embodiment of the present invention. Similar to the fourth embodiment, the common electrode is formed last. Unlike Example 4, since the passivation film is not covered on the entire effective pixel region, the processed cross section of the amorphous silicon layer is exposed. For this reason, a process for oxidizing the side surface of the exposed amorphous silicon layer by ashing or the like to form an insulating film is required.
[0072]
[Embodiment 11] FIGS. 10, 74, 75, 76, 77, 78 and 79 are a sectional view and a plan view of an eleventh embodiment of the present invention. This embodiment is applied to a vertical electric field type liquid crystal display mode (TN mode, vertical alignment mode, ferroelectric mode, antiferroelectric mode). First, after patterning the scanning line (2), the gate insulating film (4), the amorphous silicon conductor film (5) and n ⁺ Amorphous silicon film (6) is partially deposited locally as shown in FIGS. Next, a metal film is deposited on the entire surface, and the image signal wiring (7) and the drain electrode (8) are patterned. N in the region where the metal film disappeared ⁺ After removing the amorphous silicon film, a passivation film is deposited on the entire surface of the substrate. Next, in order to separate the channel portion of the thin film transistor element, the video signal wiring, and the drain electrode, the extra passivation film and amorphous silicon semiconductor film are removed. At this time, the excessive passivation film on the drain electrode, the excessive passivation film on the terminal electrode of the scanning line, and the excessive passivation film on the terminal electrode of the video signal wiring are removed. Finally, a transparent pixel electrode (14) is formed. The photomask process is four times in all processes. As in Example 8, the amorphous silicon semiconductor film and n ⁺ A method of depositing an amorphous silicon film on the entire surface of the substrate is also possible.
[0073]
[Embodiment 12] FIGS. 13, 64, 65, 66, 67, 97, 100, and 101 are a sectional view and a plan view of a twelfth embodiment. After patterning the scanning lines, the gate insulating film (4), the amorphous silicon semiconductor film (5) and n ⁺ Amorphous silicon film (6) is partially deposited locally as shown in FIGS. Next, a metal film is deposited on the entire surface of the substrate, and the image signal wiring and the liquid crystal drive electrode are patterned. N without metal ⁺ After removing the layer and the amorphous silicon layer, a transparent conductive film or a titanium metal film is deposited on the entire surface of the substrate. Next, in order to electrically isolate the video signal wiring and the liquid crystal drive electrode, the metal layer of the channel portion of the thin film transistor element and n ⁺ The layer amorphous silicon layer is removed.
Finally, a passivation film is deposited locally. 97, 100, and 101, after forming the video signal wiring and the drain electrode, a transparent conductive film, a titanium-based metal film, or a refractory metal silicide compound is deposited on the entire surface of the substrate to form the video signal wiring and the liquid crystal drive electrode. Pattern it. And then a metal layer in the channel and n ⁺ After removing the layer, a passivation film is deposited locally.
[0074]
[Embodiment 13] FIG. 14 is a sectional view of a thirteenth embodiment of the present invention. The process is the same as in Example 12 until the passivation film is deposited. In Example 13, after a passivation film is deposited on the entire surface of the substrate, contact holes (11) are formed in the scanning line terminal portion and the video signal wiring terminal portion, and the much passivation film deposited on the terminal portion is removed. ing.
[0075]
[Embodiment 14] FIG. 98 is a sectional view of a fourteenth embodiment of the present invention. As in Example 4, the scanning line (2) and the common electrode (18) are not formed at the same time, but the scanning line (2) is formed first, and then the common electrode (18) is formed at the end of the process. Forming. The photomask process is performed four times in all steps.
[0076]
[Embodiment 15] FIG. 99 is a sectional view of a fifteenth embodiment of the present invention. As in the third embodiment, the scanning electrode (2) and the common electrode (18) are not formed at the same time, and the common electrode (18) is formed first, and then the scanning wiring base insulating film (20) is locally deposited. is doing. The photomask process is performed four times in all steps.
[0077]
[Embodiment 16] FIGS. 15, 62, 63, 64, 65, 66, and 67 are a sectional view and a plan view of a sixteenth embodiment of the present invention. After patterning the scanning lines, the gate insulating film (4) and the amorphous silicon semiconductor film (5) and n ⁺ An amorphous silicon film (6) is locally deposited as shown in FIGS. Next, a metal film is deposited on the entire surface of the substrate to form a video signal wiring and a drain electrode. Then, a transparent conductive film is deposited on the entire surface of the substrate to pattern the video signal wiring and the transparent pixel electrode (14). The next metal layer in the channel part of the next thin film transistor and n ⁺ Remove the layer. Finally, a passivation film is deposited locally. This embodiment is applied to a vertical electric field type liquid crystal display mode (TN mode, vertical alignment mode, ferroelectric liquid crystal mode, antiferroelectric liquid crystal mode).
The photomask process is performed three times in all steps.
[0078]
[Embodiment 17] FIGS. 16, 106, 107, 82, 83, and 84 FIG. 85 is a sectional view and a plan view of a seventeenth embodiment of the present invention.
After patterning the scanning lines, the gate insulating film (4) and the amorphous silicon semiconductor film (5) and n ⁺ Amorphous silicon film (6) is partially deposited locally as shown in FIGS. Next, the amorphous silicon film is patterned to form a channel portion of the transistor. Thereafter, after depositing a metal film on the entire surface of the substrate, the image signal wiring (7) and the liquid crystal driving electrode (17) are patterned. N of the channel portion of the transistor ⁺ Finally, a passivation film is deposited locally after removing the layer. In the case of FIG. 16, there is no amorphous silicon layer below the liquid crystal drive electrode (17) of FIGS.
In FIGS. 102, 80, and 81, an amorphous silicon layer is present below the liquid crystal drive electrode (17), but it can be produced by the same process. The photomask process is 3 times in all steps.
[0079]
[Embodiment 18] FIGS. 17 and 105 are sectional views of an eighteenth embodiment of the present invention. This is exactly the same as Example 17 until the passivation film is deposited. In Example 18, after depositing a passivation film on the entire surface of the substrate, contact holes (11) are formed in the scanning line terminal portion and the video signal wiring terminal portion, and the excessive passivation film deposited on the terminal portion is removed. is doing. The photomask process is performed four times in all steps.
[0080]
[Embodiment 19] FIGS. 18 and 103 are sectional views of a nineteenth embodiment of the present invention. As in the third embodiment, the scanning electrode (2) and the common electrode (18) are not formed at the same time, and the common electrode (18) is formed first, and then the scanning wiring base insulating film (20) is locally deposited. is doing. The rest of the process is the same as in Example 18.
The photomask process is four times in all processes. In the case of FIG. 18, the amorphous silicon layer does not exist under the liquid crystal drive electrode (17), but in the case of FIG. 103, the amorphous silicon layer exists under the liquid crystal drive electrode (17). ing. FIG. 18 and FIG. 103 can be made by the exact same process.
[0081]
[Embodiment 20] FIGS. 19 and 104 are sectional views of a twentieth embodiment of the present invention. As in Example 4, the scanning line (2) and the common electrode (18) are not formed at the same time, but the scanning line (2) is formed first, and then the common electrode (18) is formed at the end of the process. Forming. The photomask process is 4 times in all processes.
In the case of FIG. 19, there is no amorphous silicon layer under the liquid crystal drive electrode (17), but in the case of FIG. 104, there is an amorphous silicon layer under the liquid crystal drive electrode (17). ing. 19 and 104 can be made by the exact same process.
[0082]
[Embodiment 21] FIGS. 20, 86, 87, 88, 89, 90, and 91 are a sectional view and a plan view of a twenty-first embodiment of the present invention.
After patterning the scanning line (2), a gate insulating film (4), an amorphous silicon semiconductor film (5), and an etching stopper film (21) are partially deposited locally as shown in FIGS. After the deposition, the metal electrode is exposed at the terminal portion (3) of the scanning line. Next, as shown in the plan views of FIGS. 86 and 87, the etching stopper film (21) is left only in the region for forming the channel portion of the transistor in the inner portion of the scanning line (gate electrode), and other regions. Remove all the etching stopper film except the semiconductor layer {59} around the effective pixel region. Then n to make ohmic contact ⁺ Amorphous silicon layer or n ⁺ A microcrystalline silicon layer is deposited locally. It is also possible to obtain ohmic contact by performing ion shower doping or ion implantation only on the effective pixel region and the protection transistor region for preventing static electricity. Thereafter, in order to form the video signal wiring and the liquid crystal drive electrode, a metal film is deposited on the entire surface of the substrate. After patterning the video signal wiring (7) and the liquid crystal drive electrode (17), ⁺ The layer and the amorphous silicon layer are removed. Finally, a passivation film is deposited locally. In this step, the last passivation film is not absolutely necessary. The passivation process may be omitted. The photomask process is performed three times in all steps.
[0083]
[Embodiment 22] FIG. 21 is a sectional view of a twenty-second embodiment of the present invention. It is exactly the same as Example 21 until the passivation film is deposited. In Example 22, after depositing a passivation film on the entire surface of the substrate, contact holes (11) are formed in the scanning line terminal portion and the video signal wiring terminal portion, and the much passivation film deposited on the terminal portion is removed. ing. The photomask process is performed four times in all steps.
[0084]
[Embodiment 23] FIG. 22 is a sectional view of a twenty-third embodiment of the present invention. As in the third embodiment, the common electrode (18) is formed first without simultaneously forming the scanning line (2) and the common electrode (18), and then the scanning line base insulating film (20) is locally formed. It is accumulating. The rest of the process is the same as in Example 21.
The photomask process is four times in all processes.
[0085]
[Embodiment 24] FIG. 23 is a sectional view of a twenty-fourth embodiment of the present invention. Similarly to the fourth embodiment, the scanning line (2) and the common electrode (18) are not formed at the same time, the scanning line (2) is formed first, and then the common electrode (18) is formed at the very end of the process. Is forming. The photomask process is four times in all processes.
[0086]
[Embodiment 25] FIG. 24 is a sectional view of a twenty-fifth embodiment of the present invention. Example 25 can be applied to a vertical electric field type liquid crystal display mode (TN mode, vertical alignment mode, ferroelectric liquid crystal mode, antiferroelectric liquid crystal mode). After the video signal wiring (7) and the drain electrode (8) are formed, a transparent conductive film is deposited on the entire surface of the substrate to form a transparent pixel electrode (14). Thereafter, a passivation film is deposited locally. The photomask process is four times in all processes.
[0087]
[Embodiment 26] FIGS. 31, 32, 33 and 34 are plan views of a twenty-sixth embodiment of the present invention. For each display pixel, two gate electrodes of the thin film transistors are formed in a row, and two channel regions of the thin film transistors are formed in a row. The drain electrodes are combined into one and connected to the liquid crystal drive electrode. The present invention can be applied to the thin film transistor elements of the types shown in FIGS. 3, 8, 13, 16, and 20. With this structure, even if misalignment occurs between the gate electrode and the drain electrode, the capacitance of the drain electrode hardly changes.
[0088]
[Embodiment 27] FIGS. 25, 26, 27, 28, 29 and 30 are a sectional view and a plan view of a twenty-seventh embodiment of the present invention. FIG. 25 shows an example in which the semi-transmissive region is made only of the photomask metal material. It is the Example of the photomask at the time of applying to the channel area | region of a transistor. Any pattern may be used as long as the amount of transmitted UV light in the channel region can be uniformly controlled. FIG. 26 is a cross-sectional view of a photomask on which a semi-transmissive film (24) capable of uniformly absorbing a necessary amount of UV light is deposited. A nitride film that can be deposited by a plasma CVD apparatus is suitable as a material for the semi-transmissive film. SiH ₄ (Silane) and N ₂ (Nitrogen gas) and NH ₃ By changing the mixing ratio of (ammonia gas), the absorption amount of UV light can be freely and uniformly controlled. Any film can be used as long as the UV absorption amount does not change even when UV irradiation is performed for a long time. FIG. 28 shows an example of a photomask when a UV absorbing film is applied to the channel region of a transistor. FIG. 29 is a cross-sectional view of the positive resist when the positive resist is exposed and developed using the photomask having the structure shown in FIGS. By adjusting the amount of semi-transmitted light, the film thickness of the positive resist in the semi-exposed area and the non-exposed area can be freely controlled. FIG. 30 is a process flow for forming a thin film transistor element using the photomask process of the present invention.
[0089]
[Embodiment 28] FIGS. 35, 36, 37 and 38 are a sectional view and a plan view of a twenty-eighth embodiment of the present invention. As shown in FIG. 35, the scanning line uses an aluminum-based or copper-based material in order to reduce the resistance as much as possible. Of the common electrodes, the pixel common electrode (36) facing the liquid crystal drive electrode has no problem even if the resistance is high. Considering the rubbing process, the film thickness of the pixel common electrode and the liquid crystal drive electrode should be as thin as possible. In the case of aluminum, cap metal is used to prevent the generation of hillocks in aluminum. In the case of copper, titanium, tantalum and chromium metals are used as the base metal to improve adhesion to the glass substrate. Alternatively, a refractory metal silicide compound is used, and a cap metal is always required to prevent oxidation.
A refractory metal or a refractory metal silicide compound is used as the cap metal for both aluminum and copper. As can be seen from the cross-sectional views 36, 37, and 38, the pixel common electrode facing the liquid crystal drive electrode has a higher rubbing density in the rubbing process when the film thickness is thinner than the scanning line. The orientation force becomes stronger. When the film thickness of the pixel common electrode is increased, the movement of the rubbing tip of the rubbing cloth does not move linearly in parallel with the rotation direction, and the alignment direction of the liquid crystal molecules is found and the stability of the alignment of the liquid crystal molecules decreases. .
[0090]
[Embodiment 29] FIGS. 39, 40, 41 and 42 are a sectional view and a plan view of a twenty-ninth embodiment of the present invention. FIG. 39 is a plan view of the video signal wiring and the drain electrode. FIGS. 40, 41, and 42 are cross-sectional views of the drain electrode. When the video signal wiring crosses the boundary of the gate insulating film, amorphous silicon semiconductor film, or passivation film deposition area, the video signal wiring breaks at the boundary of the deposition area due to the difference in the thermal expansion coefficient of the underlying film and the difference in adhesion. Defects such as film peeling off occur. By using a titanium-based metal, a chromium-based metal, or a refractory metal silicide compound for the base video signal wiring as in the present invention, the disconnection and film peeling are drastically reduced.
[0091]
[Embodiment 30] FIGS. 43, 44 and 45 are plan views of a thirtieth embodiment of the present invention. The deposition region of the passivation film is wider than the deposition region of the gate insulating film. The protection active element (55) for countermeasure against static electricity is formed on two or more sides of the effective pixel, and the junction region between the common electrode and the video signal wiring, and the junction region between the common electrode and the scanning line are the gate insulating film deposition region. The protective active element for preventing static electricity and the junction region are all covered with a passivation film.
As shown in FIGS. 43 and 45, when the gate insulating film is deposited to the bottom of the terminal portion of the video signal wiring, the disconnection of the video signal wiring is drastically reduced.
The distance (B) from the terminal part end of the scanning line to the deposition boundary of the gate insulating film and the distance (A) from the terminal part terminal of the scanning line to the deposition boundary of the passivation film must be 2 mm or more, respectively. Similarly, the distance from the deposition boundary of the gate insulating film to the end of the junction terminal portion of the protection active element for preventing static electricity needs to be 2 mm or more.
In the case of 2 mm or less, there is a high possibility that the gate insulating film covers the entire terminal portion of the scanning line, resulting in frequent contact failures.
[0092]
[Embodiment 31] FIGS. 46 and 47 are plan views of a thirty-first embodiment of the present invention. A seal line for bonding the two substrates is present on the peripheral boundary of the locally deposited gate insulating film, or outside the gate insulating film deposition region and in the passivation film deposition region.
[0093]
[Embodiment 32] FIGS. 94 and 95 are plan views of a thirty-second embodiment of the present invention. FIG. 94 shows a photomask for a scanning line. A transflective film is provided at a position where the video signal wiring and the scanning line intersect. FIG. 95 is a photomask for forming a channel region of a thin film transistor element. A semi-transmissive film is provided at a portion intersecting with the liquid crystal driving electrode and the transparent pixel electrode. When the positive resist is exposed using this photomask, the thickness of the positive resist film at the portion where the semi-transmissive film is installed becomes thin, and ultra-taper processing becomes possible when dry etching is performed. This drastically reduces the disconnection.
The same effect can be obtained by using a photomask as shown in FIG. 25 instead of the semipermeable membrane. The present invention can also be applied to the intersection between the common electrode and the video signal wiring.
[0094]
[Embodiment 33] FIG. 96 is a plan view of a thirty-third embodiment of the present invention. A portion that connects the common electrode that intersects the scanning line and the common electrode that intersects the video signal wiring exists outside the region of the locally deposited gate insulating film.
[0095]
【The invention's effect】
According to the present invention, the number of photomask processes can be drastically reduced from 2 to 3 times in all processes of the active element substrate.
As a result, the area of the clean room can be reduced, and the number of exposure apparatuses, cleaning apparatuses, resist-related apparatuses, and clean storage can be greatly reduced. The amount of initial investment can be greatly reduced and the running cost of the factory can also be greatly reduced. Furthermore, since the process can be shortened, quality control is easy and yield can be improved. Since the production efficiency is greatly improved, the price of the liquid crystal display panel can be reduced. By locally depositing the thickest gate insulating film locally, the stress generated in the glass substrate is made uniform. Therefore, an abnormal dimensional change is less likely to occur after the glass substrate is cut, and the alignment error between the color filter substrate and the thin film transistor substrate is also reduced. By using the transistor structure of the present invention and the protection transistor for countermeasures against static electricity, it is possible to manufacture a liquid crystal panel which is resistant to static electricity and does not cause display unevenness even if misalignment between photomasks occurs. By using the common electrode structure of the present invention, rubbing processing is greatly reduced, and disconnection of video signal wiring is drastically reduced. A 40-inch large-screen liquid crystal panel can also be realized by using copper for the scanning wiring. By using a titanium-based metal or a refractory metal silicide compound for the base of the video signal wiring, the film does not peel off. Even if the size is increased, the yield does not decrease.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a unit pixel of a conventional vertical electric field type thin film semiconductor substrate.
FIG. 2 is a cross-sectional view of a unit pixel of a conventional lateral electric field type thin film semiconductor substrate.
FIG. 3 is a cross-sectional view of a unit pixel of a lateral electric field type thin film semiconductor substrate of the present invention.
FIG. 4 is a cross-sectional view of a unit pixel of a lateral electric field type thin film semiconductor substrate of the present invention.
FIG. 5 is a cross-sectional view of a unit pixel of a lateral electric field type thin film semiconductor substrate of the present invention.
FIG. 6 is a sectional view of a unit pixel of a lateral electric field type thin film semiconductor substrate of the present invention.
FIG. 7 is a cross-sectional view of a unit pixel of a vertical electric field type thin film semiconductor substrate of the present invention.
FIG. 8 is a cross-sectional view of a unit pixel of a lateral electric field type thin film semiconductor substrate of the present invention.
FIG. 9 is a cross-sectional view of a unit pixel of a lateral electric field type thin film semiconductor substrate of the present invention.
FIG. 10 is a cross-sectional view of a unit pixel of a vertical electric field type thin film semiconductor substrate of the present invention.
FIG. 11 is a sectional view of a unit pixel of a lateral electric field type thin film semiconductor substrate of the present invention.
FIG. 12 is a sectional view of a unit pixel of a lateral electric field type thin film semiconductor substrate of the present invention.
FIG. 13 is a sectional view of a unit pixel of a lateral electric field type thin film semiconductor substrate of the present invention.
FIG. 14 is a cross-sectional view of a unit pixel of a lateral electric field type thin film semiconductor substrate of the present invention.
FIG. 15 is a cross-sectional view of a unit pixel of a vertical electric field type thin film semiconductor substrate of the present invention.
FIG. 16 is a cross-sectional view of a unit pixel of a lateral electric field type thin film semiconductor substrate of the present invention.
FIG. 17 is a sectional view of a unit pixel of a lateral electric field type thin film semiconductor substrate of the present invention.
FIG. 18 is a sectional view of a unit pixel of a lateral electric field type thin film semiconductor substrate of the present invention.
FIG. 19 is a cross-sectional view of a unit pixel of a lateral electric field type thin film semiconductor substrate of the present invention.
FIG. 20 is a cross-sectional view of a unit pixel of a lateral electric field type thin film semiconductor substrate of the present invention.
FIG. 21 is a sectional view of a unit pixel of a lateral electric field type thin film semiconductor substrate of the present invention.
FIG. 22 is a cross-sectional view of a unit pixel of a lateral electric field type thin film semiconductor substrate of the present invention.
FIG. 23 is a sectional view of a unit pixel of a lateral electric field type thin film semiconductor substrate of the present invention.
FIG. 24 is a sectional view of a unit pixel of a vertical electric field type thin film semiconductor substrate of the present invention.
FIG. 25 is a sectional view of a transmitted light amount adjustment photomask of the present invention.
FIG. 26 is a cross-sectional view of the transmitted light amount adjustment photomask of the present invention.
FIG. 27 is a plan view of the transmitted light amount adjustment photomask of the present invention.
FIG. 28 is a plan view of the transmitted light amount adjustment photomask of the present invention.
FIG. 29 is a sectional view of a positive resist exposed and developed using the transmitted light amount adjustment photomask of the present invention.
FIG. 30 is a process flow of a thin film transistor element using the transmitted light amount adjustment photomask of the present invention.
FIG. 31 is a plan view of a thin film transistor element of the present invention.
FIG. 32 is a plan view of the thin film transistor element of the present invention.
FIG. 33 is a plan view of the thin film transistor element of the present invention.
FIG. 34 is a plan view of the thin film transistor element of the present invention.
FIG. 35 is a plan view of a scan electrode and a common electrode according to the present invention.
FIG. 36 is a cross-sectional view of a scan electrode and a common electrode according to the present invention.
FIG. 37 is a sectional view of a scan electrode and a common electrode according to the present invention.
FIG. 38 is a cross-sectional view of a scan electrode and a common electrode according to the present invention.
FIG. 39 is a plan view of the video signal wiring and drain electrode of the present invention.
FIG. 40 is a sectional view of the video signal wiring of the present invention.
FIG. 41 is a sectional view of the video signal wiring of the present invention.
FIG. 42 is a sectional view of the video signal wiring of the present invention.
FIG. 43 is a plan view of a thin film semiconductor substrate of the present invention.
FIG. 44 is a plan view of a thin film semiconductor substrate of the present invention.
FIG. 45 is a plan view of a thin film semiconductor substrate of the present invention.
FIG. 46 is an arrangement plan view of the seal line of the present invention.
FIG. 47 is an arrangement plan view of the seal line of the present invention.
FIG. 48 is a protection circuit diagram for static electricity countermeasures used in the present invention.
FIG. 49 is a protection circuit diagram for static electricity countermeasures used in the present invention.
FIG. 50 is a plan view of a lateral electric field type thin film semiconductor element of the present invention.
FIG. 51 is a plan view of a lateral electric field type thin film semiconductor element of the present invention.
FIG. 52 is a plan view of the protection transistor element for static electricity countermeasure according to the present invention.
FIG. 53 is a plan view of the protection transistor element for static electricity countermeasure according to the present invention.
FIG. 54 is a plan view of the protection transistor element for static electricity countermeasure according to the present invention.
FIG. 55 is a plan view of a protection transistor element for static electricity countermeasures according to the present invention.
FIG. 56 is a plan view of a lateral electric field type thin film semiconductor element of the present invention.
FIG. 57 is a plan view of a lateral electric field type thin film semiconductor element of the present invention.
FIG. 58 is a plan view of the protection transistor element for static electricity countermeasure according to the present invention.
FIG. 59 is a plan view of a protection transistor element for static electricity countermeasures according to the present invention.
FIG. 60 is a plan view of the protection transistor element for static electricity countermeasure according to the present invention.
FIG. 61 is a plan view of a protection transistor element for static electricity countermeasures according to the present invention.
FIG. 62 is a plan view of a vertical electric field mode thin film semiconductor element of the present invention.
FIG. 63 is a plan view of a vertical electric field type thin film semiconductor element of the present invention.
FIG. 64 is a plan view of the protection transistor element for static electricity countermeasure according to the present invention.
FIG. 65 is a plan view of the protection transistor element for static electricity countermeasure according to the present invention.
FIG. 66 is a plan view of the protection transistor element for static electricity countermeasure according to the present invention.
FIG. 67 is a plan view of the protection transistor element for static electricity countermeasures of the present invention.
FIG. 68 is a plan view of a lateral electric field type thin film semiconductor element of the present invention.
FIG. 69 is a plan view of a lateral electric field type thin film semiconductor element of the present invention.
FIG. 70 is a plan view of a protection transistor element for preventing static electricity according to the present invention.
FIG. 71 is a plan view of a protection transistor element for static electricity countermeasures according to the present invention.
FIG. 72 is a plan view of the protection transistor element for static electricity countermeasure according to the present invention.
FIG. 73 is a plan view of the protection transistor element for preventing static electricity according to the present invention.
FIG. 74 is a plan view of a vertical electric field mode thin film semiconductor element of the present invention.
FIG. 75 is a plan view of a vertical electric field mode thin film semiconductor element of the present invention.
FIG. 76 is a plan view of the protection transistor element for static electricity countermeasures according to the present invention.
FIG. 77 is a plan view of the protection transistor element for static electricity countermeasure according to the present invention.
FIG. 78 is a plan view of the protection transistor element for static electricity countermeasure according to the present invention.
FIG. 79 is a plan view of the protection transistor element for static electricity countermeasure according to the present invention.
FIG. 80 is a plan view of a lateral electric field type thin film semiconductor element of the present invention.
FIG. 81 is a plan view of a lateral electric field mode thin film semiconductor element of the present invention.
FIG. 82 is a plan view of the protection transistor element for static electricity countermeasures of the present invention.
FIG. 83 is a plan view of the protection transistor element for static electricity countermeasures according to the present invention.
FIG. 84 is a plan view of the protection transistor element for static electricity countermeasures according to the present invention.
FIG. 85 is a plan view of the protection transistor element for static electricity countermeasures according to the present invention.
FIG. 86 is a plan view of a lateral electric field type thin film semiconductor element of the present invention.
FIG. 87 is a plan view of a lateral electric field type thin film semiconductor element of the present invention.
FIG. 88 is a plan view of the protection transistor element for static electricity countermeasure according to the present invention.
FIG. 89 is a plan view of the protection transistor element for static electricity countermeasure according to the present invention.
FIG. 90 is a plan view of the protection transistor element for static electricity countermeasure according to the present invention.
FIG. 91 is a plan view of a protection transistor element for static electricity countermeasures according to the present invention.
FIG. 92 is a plan view of a locally deposited region of the gate insulating film according to the present invention.
FIG. 93 is a plan view of a gate insulating film local deposition region of the present invention;
FIG. 94 is a plan view of the transmitted light amount adjustment photomask of the present invention.
FIG. 95 is a plan view of the transmitted light amount adjustment photomask of the present invention.
FIG. 96 is a plan view of a lateral electric field type thin film semiconductor substrate of the present invention.
FIG. 97 is a sectional view of a unit pixel of a lateral electric field type thin film semiconductor substrate of the present invention.
FIG. 98 is a sectional view of a unit pixel of a lateral electric field type thin film semiconductor substrate of the present invention.
FIG. 99 is a cross-sectional view of a unit pixel of a lateral electric field type thin film semiconductor substrate of the present invention.
FIG. 100 is a plan view of a lateral electric field type thin film semiconductor element of the present invention.
FIG. 101 is a plan view of a lateral electric field type thin film semiconductor element of the present invention.
FIG. 102 is a cross-sectional view of a unit pixel of a lateral electric field type thin film semiconductor substrate of the present invention.
FIG. 103 is a sectional view of a unit pixel of a lateral electric field type thin film semiconductor substrate of the present invention.
FIG. 104 is a sectional view of a unit pixel of a lateral electric field type thin film semiconductor substrate of the present invention.
FIG. 105 is a cross-sectional view of a unit pixel of a lateral electric field type thin film semiconductor substrate of the present invention.
FIG. 106 is a plan view of a lateral electric field type thin film semiconductor element of the present invention.
FIG. 107 is a plan view of a lateral electric field type thin film semiconductor element of the present invention.
[Explanation of symbols]
1 …… Glass substrate
2. Scanning line (gate electrode)
3. Scanning line terminal
4 ... Gate insulation film
5. Thin film semiconductor layer (non-doped layer)
6 ... n doped with phosphorus ⁺ Semiconductor layer
7 …… Video signal wiring
8 …… Drain electrode
9 …… Video signal wiring terminal
10: Pixel electrode contact hole
11 …… Scanning line terminal contact hole
12 …… Video signal wiring contact hole
13. Scanning line terminal drive IC junction electrode (transparent electrode)
14 …… Pixel electrode (transparent electrode)
15 …… Video signal wiring terminal drive IC junction electrode (transparent electrode)
16. Passivation film
17 …… Horizontal electric field type liquid crystal drive electrode (pixel electrode)
18 …… Common electrode for horizontal electric field system
19. Scanning line terminal drive IC junction electrode (metal electrode)
20 …… Scanning line base insulating film
21 …… Etching stopper insulating film
22 …… Quartz glass substrate for photomask
23 …… Translucent photomask region
24 …… Semi-permeable membrane region
25 …… Photomask metal (Cr or Mo)
26 …… Video signal wiring photomask complete blocking area
27 …… Drain electrode photomask complete blocking region
28 …… Transistor region of transistor / channel
29 …… Transistor film for transistor and channel
30 …… Positive resist UV exposure complete film thickness after development
31 …… Positive resist UV exposure Translucent film thickness after development
32 …… Positive resist
33 …… First-layer scanning line (aluminum or aluminum alloy)
34 …… Second-layer scanning line (cap electrode)
35 …… First layer common electrode (aluminum or aluminum alloy)
36 …… Second layer common electrode (pixel common electrode)
37 …… Second layer lower scanning line
38 ... Second layer upper scanning line
39 …… Second layer lower common electrode (pixel common electrode)
40 …… Second layer upper common electrode (pixel common electrode)
41 …… Base scanning line
42 …… Copper or copper alloy scanning line
43 …… Cap gate electrode
44 …… Common electrode for copper or copper alloy
45 …… Base common electrode
46 …… Cap common electrode (pixel common electrode)
47 …… Scanning line and common electrode cutting position
48 …… Video wiring cutting position
49 …… Base video signal wiring
50 …… Low-resistance video signal wiring
51 …… Cap video signal wiring
52 …… Etching stopper video signal wiring
53 …… Gate insulating film local deposition region
54 …… Passivation film local deposition region
55 …… Protective active element for static electricity countermeasures
56 …… Effective pixel area peripheral common electrode
57 …… Liquid crystal cell seal line
58 …… Etched region of thin film transistor channel
59 …… Semiconductor layer around effective pixel area
A: Distance from the gate insulating film deposition boundary to the end of the scanning line terminal
B: Distance from passivation film deposition boundary to end of scanning line terminal
C: Distance from the gate insulating film deposition boundary to the end of the junction terminal of the protective active element for static electricity countermeasures
60 …… Common electrode terminal

Claims (30)

A pair of substrates at least one of which is transparent, a liquid crystal composition layer sandwiched between the substrates, and a plurality of scanning lines arranged in a matrix on the facing surface of one of the substrates; In a liquid crystal display device comprising a video signal line, a pixel electrode paired with a common electrode, and an active element connected to the pixel electrode, the scanning line, and the video signal line, a gate insulating film of the active element is a substrate When depositing on the active element, the active element semiconductor layer and the passivation protective film layer are partially deposited only in the local area of the substrate including the effective pixel area and the active element for protecting against static electricity formed around the effective pixel area. Is a manufacturing method characterized by depositing on the entire surface of the substrate. A pair of substrates at least one of which is transparent, a liquid crystal composition layer sandwiched between the substrates, a plurality of scanning lines and video signals arranged in a matrix on the facing surface of one of the substrates In a liquid crystal display device comprising a pixel electrode paired with a wiring and a common electrode, and an active element connected to the pixel electrode, the scanning line, and the video signal wiring, a gate insulating film of the active element, and a semiconductor layer When depositing on the substrate, it is partially deposited only on the local area of the substrate including the effective pixel region and the active element for protecting against static electricity formed around the effective pixel region, and the passivation protection layer is formed on the entire surface of the substrate. A manufacturing method characterized by depositing. A pair of substrates at least one of which is transparent, a liquid crystal composition layer sandwiched between the substrates, and a plurality of scanning lines arranged in a matrix on the facing surface of one of the substrates; In a liquid crystal display device comprising a pixel electrode paired with a video signal line and a common electrode, and an active element connected to the pixel electrode, the scanning line and the video signal line, a gate insulating film and a passivation of the active element When the protective film is deposited on the substrate, the protective film is partially deposited only in the local region of the substrate including the effective pixel region and the protective active device for preventing static electricity formed around the effective pixel region, and the semiconductor layer of the active device Is a manufacturing method characterized by depositing on the entire surface of the substrate. 4. The method of manufacturing a liquid crystal display device having an active element according to claim 3, wherein the effective pixel area and the local area of the substrate including the protective active element for preventing static electricity formed around the effective pixel area are partially A manufacturing method characterized in that the passivation film region is deposited wider than the deposited gate insulating film. A pair of substrates at least one of which is transparent, a liquid crystal composition layer sandwiched between the substrates, a plurality of scanning lines and video signals arranged in a matrix on the facing surface of one of the substrates In a liquid crystal display device comprising a pixel electrode paired with a wiring and a common electrode, and an active element connected to the pixel electrode, the scanning line, and the video signal wiring, a gate insulating film and a semiconductor layer of the active element When the passivation protection film layer is deposited on the substrate, it is partially deposited only on the local region of the substrate including the effective pixel region and the protective active element for preventing static electricity formed around the effective pixel region. Manufacturing method. 6. A liquid crystal display device having an active element according to claim 5, wherein the gate is partially deposited only in a local area of the substrate including the effective pixel area and the protective active element for static electricity countermeasures formed around the effective pixel area. A manufacturing method characterized in that the passivation film region is deposited wider than the insulating film. 7. The liquid crystal display device manufactured by the manufacturing method according to claim 1, wherein a protection active element for preventing static electricity that connects the common electrode and the scanning line, and the common electrode and the video signal wiring are connected. A liquid crystal display device, wherein the protective active element for preventing static electricity is completely covered with a passivation film layer. 7. The liquid crystal display device manufactured by the manufacturing method according to claim 1, wherein a protection active element for preventing static electricity that connects the common electrode and the scanning line, and the common electrode and the video signal wiring are connected. Active protection elements for static electricity countermeasures on at least two sides around the boundary of the gate insulating film deposited in the local area of the substrate including the active pixel area and the active protection element for static electricity countermeasures formed around the effective pixel area A liquid crystal display device characterized by being arranged. 7. A liquid crystal display device manufactured by the manufacturing method according to claim 1, wherein a connection portion of a protection active element for preventing static electricity connecting the common electrode and the scanning line, the common electrode, and the video signal wiring. The region of the gate insulating film deposited in the local region of the substrate including the effective active region for static electricity countermeasures formed around the effective pixel region, where the connecting portion of the active protective device for static electricity countermeasures connecting the active pixels is connected A liquid crystal display device characterized by being outside. 7. A liquid crystal display device manufactured by the manufacturing method according to claim 1, wherein a seal region in which two substrates are bonded to form a liquid crystal cell is formed around the effective pixel region and the effective pixel region. A liquid crystal display characterized by being present on a peripheral boundary of a gate insulating film deposited in a local region of a substrate including a protective active element for countermeasures , or outside a region of the gate insulating film and in a passivation film deposition region apparatus. According to the third, fourth, fifth and sixth aspects, after depositing the metal film for forming the video signal wiring and the pixel electrode, the video signal wiring and the pixel electrode are formed simultaneously. Then, after removing the metal film and the n ⁺ layer in the channel portion of the thin film transistor, the passivation film is partially applied to the local region of the substrate including the effective pixel region and the protective active element for preventing static electricity formed around the effective pixel region. A method of manufacturing a liquid crystal display device, comprising depositing a liquid crystal. According to claims 3, 4, 5, and 6, when the video signal wiring and the drain electrode are simultaneously formed, the transparent pixel electrode is deposited, and when the video signal wiring and the pixel electrode are patterned, Remove the n ⁺ layer. Thereafter, a passivation film is partially deposited on the local region of the substrate including the effective pixel region and the protective active element for preventing static electricity formed around the effective pixel region . Regarding the second, fifth and sixth aspects, after partially depositing the gate insulating film and the semiconductor layer on the local region of the substrate including the effective pixel region and the protective active element for preventing static electricity formed around the effective pixel region , The video signal wiring and the pixel electrode are formed simultaneously. Then, after removing the n ⁺ layer exposed on the surface, a passivation film is partially applied to the entire region of the substrate or to a local region of the substrate including the protective active element for preventing static electricity formed around the effective pixel region and the effective pixel region. accumulate. Thereafter, an excess passivation film and a semiconductor layer are removed to form a channel portion of the thin film transistor, a video signal wiring, and a pixel electrode. According to the first, third, and fourth aspects, the gate insulating film is partially deposited on the local region of the substrate including the effective pixel region and the protective active element for preventing static electricity formed around the effective pixel region . Thereafter, after forming the video signal wiring and the pixel electrode at the same time, the n ⁺ layer exposed on the surface is removed. Next, a passivation film is partially deposited on the entire surface of the substrate or on a local region of the substrate including the active pixel region and the protective active element for preventing static electricity formed around the effective pixel region . Thereafter, an excess passivation film and a semiconductor layer are removed to form a channel portion of the thin film transistor, a video signal wiring, and a pixel electrode. According to the thirteenth and fourteenth aspects, after the video signal wiring and the drain electrode are formed simultaneously, the n ⁺ layer exposed on the surface is removed. Next, a passivation film is partially deposited on the entire surface of the substrate or on a local region of the substrate including the active pixel region and the protection active element for preventing static electricity formed around the effective pixel region . Thereafter, a transparent pixel electrode is formed after removing an extra passivation film and a semiconductor layer to form a channel portion of a thin film transistor, a video signal wiring, and a drain electrode. 5. The thin film transistor channel portion according to claim 5, wherein a gate insulating film and a semiconductor layer are deposited on a local region of a substrate including an effective pixel region and a protective active element for preventing static electricity formed around the effective pixel region. To pattern. Thereafter, the video signal wiring and the pixel electrode are formed at the same time, and then the n ⁺ layer in the channel portion of the thin film transistor is removed. Then, a passivation film is deposited on a local region of a substrate including an effective pixel region and a protective active element for preventing static electricity formed around the effective pixel region . 3. The semiconductor layer is formed on the substrate after the gate insulating film is partially deposited on the local region of the substrate including the effective pixel region and the protective active element for preventing static electricity formed around the effective pixel region. Deposits on the entire surface. Thereafter, after patterning the channel portion of the thin film transistor, the video signal wiring and the pixel electrode are formed simultaneously. Then, after removing the n ⁺ layer of the channel portion of the thin film transistor, a passivation film is deposited on the local region of the substrate including the effective pixel region and the protective active element for preventing static electricity formed around the effective pixel region. A method for manufacturing a liquid crystal display device. The semiconductor layer is formed on the substrate after the gate insulating film is partially deposited on the local region of the substrate including the effective pixel region and the protective active element for preventing static electricity formed around the effective pixel region. It is partially deposited on the entire region or a local region of the substrate including the active pixel region and the active pixel protection active element formed around the effective pixel region . Then, after patterning the channel portion of the thin film transistor, the video signal wiring and the pixel electrode are formed simultaneously. Next, after removing the n ⁺ layer in the channel portion of the thin film transistor, a passivation film is deposited on the entire surface of the substrate. Thereafter, a contact hole is formed in the terminal portion for connection with the driving IC. 7. The thin film transistor according to claim 5, wherein a gate insulating film and a semiconductor layer are partially deposited on a local region of a substrate including an effective pixel region and a protective active element for preventing static electricity formed around the effective pixel region. Pattern the channel part of. Next, after forming the video signal wiring and the pixel electrode at the same time, after removing the n ⁺ layer of the channel portion of the thin film transistor, a passivation film is formed around the effective pixel region and the effective pixel region. It is partially deposited on a local area of the substrate containing the element . Thereafter, the common electrode is formed on the passivation film. A pair of substrates at least one of which is transparent, a liquid crystal composition layer sandwiched between the substrates, and a plurality of scanning lines and an image arranged in a matrix on the facing surface of one of the substrates In a liquid crystal display device including a signal wiring and a pixel electrode paired with a common electrode, and an active element connected to the pixel electrode, the scanning line, and the video signal wiring, a gate insulating film of the active element is used as an effective pixel. After partially depositing on a local region of the substrate including the static active protective active element formed around the region and the effective pixel region , the semiconductor layer and the etching stopper layer may be the entire surface of the substrate or the effective pixel region. An n ⁺ layer for depositing and making ohmic contact is formed in a local region of the substrate including the protective active element for preventing static electricity formed around the effective pixel region. When ion implantation is performed, partial implantation is performed in the local region of the substrate including the effective pixel region and the protective active element for preventing static electricity formed around the effective pixel region . When the n ⁺ layer is deposited by the plasma CVD method, the n ⁺ layer is partially deposited on the entire surface of the substrate or a local region of the substrate including the active pixel region and the protective active element for preventing static electricity formed around the effective pixel region. The manufacturing method characterized by the above-mentioned. 21. The channel of the thin film transistor device according to claim 20, wherein after patterning the video signal wiring and the pixel electrode at the same time, both the n ⁺ layer exposed on the surface and the semiconductor layer under the n ⁺ layer are removed. A method of manufacturing a liquid crystal display device, wherein the portion, the video signal wiring, and the pixel electrode are independently and separately formed. 23. The substrate of claim 20, wherein the image signal wiring and the pixel electrode are formed at the same time, and then the passivation film is formed on the entire surface of the substrate or around the effective pixel region and the effective pixel region. Partially deposits in local areas . Next, a method for manufacturing a liquid crystal display device is characterized in that an extra passivation film, an n ⁺ layer, and a semiconductor layer on the connection terminal portion are removed for connection with the drive circuit IC. A horizontal electric field mode liquid crystal display device manufactured by the manufacturing method according to claim 1. A twisted nematic liquid crystal display device, a ferroelectric liquid crystal display device, or a vertically aligned liquid crystal display device manufactured by the manufacturing method according to claim 15. 23. The scanning line according to claim 1, wherein the scanning line has a two-layer structure of aluminum (or aluminum alloy) and titanium (or titanium alloy), or aluminum (or aluminum alloy) and titanium (or titanium alloy). The common electrode facing the pixel electrode is made of a three-layer structure of molybdenum (or molybdenum alloy) or a three-layer structure of aluminum (or aluminum alloy), chromium (or chromium alloy), and molybdenum (or molybdenum alloy). Single layer structure of (or titanium alloy), two layer structure of titanium (or titanium alloy) and molybdenum (or molybdenum alloy), or two layer structure of chromium (or chromium alloy) and molybdenum (or molybdenum alloy) Liquid crystal display device characterized in that 23. The scanning line according to claim 1, wherein the scanning line is a three-layer structure of titanium (or titanium alloy), copper (or copper alloy) and titanium (or titanium alloy), or chromium (or chromium alloy) and copper ( Or a three-layer structure of copper alloy) and molybdenum (or molybdenum alloy), or a three-layer structure of titanium (or titanium alloy), copper (or copper alloy), and molybdenum (or molybdenum alloy), facing the pixel electrode The common electrode is a single layer structure of titanium (or titanium alloy), or a two-layer structure of titanium (or titanium alloy) and molybdenum (or molybdenum alloy), or of chromium (or chromium alloy) and molybdenum (or molybdenum alloy) A liquid crystal display device using a two-layer structure. 23. The two-layer structure of titanium (or titanium alloy) and aluminum (or aluminum alloy) or the two-layer structure of titanium (or titanium alloy) and molybdenum (or molybdenum alloy) in the video signal wiring according to claim 1. Or a two-layer structure of chromium (or chromium alloy) and molybdenum (or molybdenum alloy). 23. The video signal wiring according to claim 1, wherein a three-layer structure of titanium (or titanium alloy), aluminum (or aluminum alloy) and titanium (or titanium alloy), or titanium (or titanium alloy) and aluminum ( Or an aluminum alloy) and molybdenum (or molybdenum alloy) three-layer structure, or titanium (or titanium alloy), aluminum (or aluminum alloy) and chromium (or chromium alloy) three-layer structure, or titanium (or titanium alloy) A three-layer structure of molybdenum (or molybdenum alloy) and titanium (or titanium alloy) or a three-layer structure of titanium (or titanium alloy), chromium (or chromium alloy) and molybdenum (or molybdenum alloy) is used. Liquid crystal display device. The liquid crystal display device manufactured by the manufacturing method according to claim 1, wherein a region where the gate insulating film is deposited is formed around the effective pixel region, the terminal region of the video signal wiring, and the effective pixel region. A liquid crystal display device, characterized in that it is limited to a local region of the substrate including the protective active element for use . 7. A liquid crystal display device manufactured by the manufacturing method according to claim 1, wherein the distance from the gate insulating film deposition boundary to the scanning line terminal end and the junction of the gate insulating film deposition active protective element for static electricity countermeasures. A liquid crystal display device, wherein the distance to the terminal end is 2 mm or more.

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