KR20020056111A - array panel of liquid crystal display and manufacturing method thereof - Google Patents

Abstract

The present invention relates to an array substrate for a liquid crystal display device and a method of manufacturing the same.

Since the liquid crystal display forms and arranges the lower array substrate and the upper color filter substrate, respectively, problems such as light leakage may occur. In addition, the array substrate is manufactured using several masks, and it is desirable to reduce the manufacturing cost by reducing the number of masks.

In the present invention, a photolithography process using a mask having a fine pattern, such as a slit, may be used to reduce the manufacturing cost by etching an array of layers at once and manufacturing an array substrate using four masks. By forming a light shielding pattern and overlapping the pixel electrode, the adhesion margin can be improved to prevent light leakage.

Description

Array substrate for liquid crystal display device and manufacturing method thereof

The present invention relates to an array substrate for a liquid crystal display device and a method of manufacturing the same.

In general, a liquid crystal display device arranges two substrates on which electrodes are formed so that the surfaces on which the two electrodes are formed face each other, injects a liquid crystal material between the two substrates, and applies a voltage to the two electrodes to generate an electric field. By moving the liquid crystal molecules, the image is expressed by the transmittance of light that varies accordingly.

Liquid crystal displays may be formed in various forms. Currently, an active matrix LCD (AM-LCD) having a thin film transistor and pixel electrodes connected to the thin film transistors arranged in a matrix manner has excellent resolution and video performance. It is most noticed.

The liquid crystal display has a structure in which a pixel electrode is formed on a lower array substrate and a common electrode is formed on a color filter substrate, which is an upper substrate, and drives liquid crystal molecules by an electric field in a direction perpendicular to an up and down substrate. to be. This is excellent in characteristics such as transmittance and aperture ratio, and the common electrode of the upper plate serves as a ground, thereby preventing the destruction of the liquid crystal cell due to static electricity.

The upper substrate of the liquid crystal display may further include a black matrix to prevent light leakage occurring in portions other than the pixel electrode.

The array substrate, which is a lower substrate of the liquid crystal display, is formed by repeatedly depositing a thin film and performing a photolithography process using a mask several times. Typically, 5 to 6 masks are used, and the number of masks is an array substrate. The process water which manufactures this is shown.

Hereinafter, a conventional array substrate for a liquid crystal display device and a method of manufacturing the same will be described with reference to the accompanying drawings.

1 is a plan view of a conventional array substrate for a liquid crystal display device, and FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1.

1 and 2, in the array substrate for a liquid crystal display device, a gate wiring 21 having a horizontal direction and a gate electrode 22 extending from the gate wiring 21 are disposed on the transparent insulating substrate 10. Formed.

The gate insulating film 30 is formed on the gate wiring 21 and the gate electrode 22, and the active layer 41 and the ohmic contact layers 51 and 52 are sequentially formed thereon.

The data electrode 61 orthogonal to the gate wiring 21 on the ohmic contact layers 51 and 52, the source electrode 62 extending from the data wiring 61, and the source electrode 62 centering on the gate electrode 22. The capacitor electrode 65 which overlaps with the drain electrode 63 and the gate wiring 21 which opposes is formed.

The data line 61, the source and drain electrodes 62 and 63, and the capacitor electrode 65 are covered with a protective layer 70, and the protective layer 70 connects the drain electrode 63 and the capacitor electrode 65. Respectively, the first and second contact holes 71 and 72 are exposed.

The pixel electrode 81 is formed on the passivation layer 70 of the pixel area defined by the gate line 21 and the data line 61 intersecting. The pixel electrode 81 is formed of the first and second contact holes ( 71 and 72 are connected to the drain electrode 62 and the capacitor electrode 65, respectively.

In such an array substrate, when a voltage is applied to the gate electrode 22 through the gate wiring 21, electrons are concentrated in the active layer 41 and a conductive channel is formed between the source and drain electrodes 62 and 63. Current can flow, and the image signal transmitted from the data line 61 reaches the pixel electrode 81 through the source electrode 62 and the drain electrode 63.

3A to 3E illustrate a manufacturing process of such an array substrate for a liquid crystal display, and correspond to a cross section taken along line II-II of FIG. 1. Next, a method of manufacturing a conventional array substrate for a liquid crystal display device will be described with reference to FIGS. 3A to 3E.

As shown in FIG. 3A, the gate wiring 21 and the gate electrode 22 are formed by depositing a metal material on the substrate 10 and patterning the same using a first mask.

Next, as shown in FIG. 3B, the gate insulating layer 30, amorphous silicon, and amorphous silicon containing impurities are sequentially deposited, and then the active layer 41 and the impurities are subjected to a photolithography process using a second mask. The semiconductor layer 53 is formed.

Subsequently, as shown in FIG. 3C, a metal layer is deposited and patterned using a third mask, thereby forming the data wiring (61 of FIG. 1), the source electrode 62, the drain electrode 63, and the capacitor electrode 65. The impurity semiconductor layer 53 exposed between the source electrode 62 and the drain electrode 63 is etched to complete the ohmic contact layers 51 and 52.

Next, as shown in FIG. 3D, the protective layer 70 is deposited and the protective layer 70 and the gate insulating film 30 are patterned using a fourth mask to thereby form the drain electrode 63 and the capacitor electrode 65. The exposed first and second contact holes 71 and 72 are formed.

Next, as illustrated in FIG. 3E, the transparent conductive material is deposited and patterned using a fifth mask, thereby forming a drain electrode 63 and a capacitor electrode 65 through the first and second contact holes 71 and 72. The pixel electrode 81 in contact is formed.

As described above, an array substrate may be manufactured by a photolithography process using five masks. The photolithography process involves various processes such as cleaning, photoresist coating, exposure and development, and etching. Therefore, shortening the photolithography process only once can significantly reduce the manufacturing time, reduce the manufacturing cost, and reduce the incidence of defects. Therefore, it is desirable to manufacture the array substrate by reducing the number of masks.

4 is a cross-sectional view of such an array substrate and an upper color filter substrate, corresponding to a cross section taken along the line II-II of FIG. 1, and for convenience of description, only the black matrix is illustrated on the upper substrate.

As shown in FIG. 4, the black matrix 91 is disposed to correspond to a portion other than the pixel electrode 81, but misalignment may occur when the array substrate and the color filter substrate are disposed, thereby preventing light leakage due to misalignment. In order to do this, the black matrix 91 and the pixel electrode 81 partially overlap each other. Here, the pixel electrode 81 on the capacitor electrode 65 does not overlap the black matrix 91, which means that the capacitor electrode 65 and the gate wiring 21 overlap with one end of the pixel electrode 81. This is because it serves to block.

Here, the width A at which the black matrix 91 and the pixel electrode 81 overlap is determined by the bonding margin, and the size thereof is generally about 5 μm.

However, when the color filter substrate and the array substrate are bonded to each other and the subsequent process is performed, the size of the substrate may vary depending on the temperature of the process. At this time, since the color filter substrate and the array substrate are different types, the degree of change in the size of the substrate is also different. In addition, even if an error occurs during the process, and thus the black matrix and the pixel electrode are formed to overlap, the black matrix and the pixel electrode are misaligned at a portion adjacent to the gate wiring, causing light leakage.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide an array substrate for a liquid crystal display device and a method of manufacturing the same, which can reduce a manufacturing process and prevent light leakage.

1 is a plan view of an array substrate for a general liquid crystal display device.

FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1. FIG.

3A to 3E are cross-sectional views showing a process of manufacturing a conventional array substrate for a liquid crystal display device.

4 is a cross-sectional view of a conventional liquid crystal display device.

5 is a plan view of an array substrate for a liquid crystal display device according to the present invention;

6 is a cross-sectional view taken along the line VI-VI in FIG. 5.

7A-7D are cross-sectional views illustrating a process of fabricating an array substrate in accordance with the present invention.

8 is a cross-sectional view showing a mask according to the present invention.

9 is a cross-sectional view of a liquid crystal display device according to the present invention.

In the liquid crystal display according to the present invention for achieving the above object, a plurality of gate wirings having one direction and gate electrodes connected to the gate wirings are formed on a substrate, and a gate insulating film is formed thereon. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer, and a data wiring orthogonal to the gate wiring, a source electrode extending from the data wiring, and a drain electrode positioned opposite the source electrode are formed thereon. Further, a light shielding pattern made of the same material as the data wiring and extending in a direction parallel to the gate wiring is formed. Subsequently, a protective layer is formed on the data line, the source and drain electrodes, and a contact hole exposing a part of the drain electrode over the light blocking pattern. Next, a pixel electrode connected to the drain electrode and overlapping a part of the light blocking pattern is formed on the passivation layer.

Here, the ohmic contact layer may have the same shape as the data line, the source and the drain electrode, and the semiconductor layer may have the same shape as the data line, the source and the drain electrode except between the source and the drain electrode.

A portion of the light blocking pattern that does not overlap the pixel electrode may have a width of 2 μm.

In addition, the light blocking pattern may be connected to the drain electrode.

The array substrate for a liquid crystal display according to the present invention may further include a capacitor electrode made of the same material as the data line, partially overlapping the gate line, and connected to the pixel electrode.

Meanwhile, in the method of manufacturing an array substrate for a liquid crystal display device according to the present invention, a substrate is provided, a metal material is deposited on the substrate, and patterned with a first mask to form a gate wiring and a gate electrode. Subsequently, a gate insulating film, an amorphous silicon layer, an impurity amorphous silicon layer, and a metal layer are sequentially deposited on the gate wiring. Next, the metal layer, the impurity amorphous silicon layer, and the amorphous silicon layer are sequentially patterned with a second mask to form a semiconductor layer, an ohmic contact layer, a data line, a source electrode and a drain electrode, and a light shielding pattern. Next, an insulating material is deposited on the data line, and a protective layer having a contact hole exposing a part of the drain electrode is formed by a patterning process using a third mask. Subsequently, a transparent conductive material is deposited on the passivation layer and patterned with a fourth mask to form a pixel electrode connected to the drain electrode through the contact hole and partially overlapping the light blocking pattern.

Here, the light blocking pattern may be connected to the drain electrode.

In addition, the second mask may have a plurality of slit patterns at portions corresponding between the source and drain electrodes.

As described above, in the present invention, manufacturing costs can be reduced by fabricating an array substrate using four masks, and a process margin is formed by forming a light shielding pattern in a direction parallel to the gate wiring using a material such as data wiring and partially overlapping the pixel electrode. It is possible to prevent light leakage by improving the

Hereinafter, an array substrate for a liquid crystal display device and a method of manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, FIG. 5 is a plan view of an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 5.

5 and 6, the gate wiring 121 in one direction and the gate electrode 122 extending from the gate wiring 121 are formed on the substrate 110.

A gate insulating layer 130 is formed on the gate wiring 121 to cover the gate wiring 121 and the gate electrode 122.

Subsequently, semiconductor layers 141 and 145 are formed on the gate insulating layer 130, and ohmic contact layers 151, 152 and 155 are formed thereon. Here, the semiconductor layer 141 on the gate electrode 122 becomes an active layer of the thin film transistor.

The data line 161, the source and drain electrodes 162 and 163, the light blocking pattern 164, and the capacitor electrode 165 are formed on the ohmic contact layers 151, 152, and 155. The data line 161 defines a pixel area orthogonal to the gate line 121, the source electrode 162 extends from the data line 161, and the drain electrode 163 is separated from the source electrode 162. The gate electrode 122 faces the source electrode 162. The light blocking pattern 164 connected to the drain electrode 163 extends in a direction parallel to the gate wiring 121, and the capacitor electrode 165 partially overlaps the gate wiring 121 to be together with the gate wiring 121. Form a storage capacitor.

Here, the ohmic contact layers 151 and 152 have the same shape as the data line 161 and the source and drain electrodes 162 and 163, and the semiconductor layer 141 is formed between the source and drain electrodes 162 and 163. Except for the portion corresponding to the channel of the thin film transistor, it has the same shape as the data line 161, the source and drain electrodes 162 and 163.

Next, a passivation layer 170 is formed on the data line 161, the source and drain electrodes 162 and 163, and the capacitor electrode 165 to cover the passivation layer 170. First and second contact holes 171 and 172 exposing the capacitor electrode 165, respectively.

Next, a pixel electrode 181 made of a transparent conductive material is formed in the pixel area, and the pixel electrode 181 is connected to the drain electrode 163 through the first contact hole 171. The capacitor electrode 165 partially overlaps the capacitor electrode 165 and is connected to the capacitor electrode 165 through the second contact hole 172, and partially overlaps the light blocking pattern 164.

Here, the light blocking pattern 164 is to prevent light leakage by increasing the bonding margin of the liquid crystal display.

Hereinafter, a manufacturing process of the array substrate for a liquid crystal display will be described in detail with reference to FIGS. 7A to 7D.

First, as shown in FIG. 7A, a metal material is deposited on the transparent substrate 110 and patterned using a first mask, thereby extending the gate electrode 122 and the gate electrode 122 extending from the gate wiring 121 in one direction. ).

Subsequently, as shown in FIG. 7B, the gate insulating layer 130, the amorphous silicon layer, and the amorphous silicon layer doped with impurities are sequentially deposited, and the metal layer is deposited by the same method as sputtering, followed by a photolithography process using a second mask. The patterned data line (161 of FIG. 5), the source and drain electrodes 162 and 163, the light shielding pattern 164, the capacitor electrode 165, and the ohmic contact layers 151, 152 and 155 and the semiconductor layer 141 are formed. 145).

At this time, in the photolithography process, several layers of films are etched at once by using diffraction exposure. In order to use the diffraction phenomenon, the second mask includes a slit pattern. This second mask is shown in FIG. 8.

As shown, the second mask includes a region D where light is blocked, a diffraction exposure region E, and a region F through which light is transmitted. The region D where light is blocked corresponds to a region where the data line 161, the source and drain electrodes 162 and 163, the light shielding pattern 164, and the capacitor electrode 165 are formed, and the diffraction exposure region E ) Corresponds to the portion where the channel between the source and drain electrodes 162 and 163 is formed, and the region F through which light is transmitted corresponds to the remaining portion. Here, in the diffraction exposure area E, a plurality of slits are formed at intervals smaller than the resolution of the exposure machine in order to diffract the light.

Next, as illustrated in FIG. 7C, first, a silicon nitride film, a silicon oxide film, or an organic insulating film is deposited, and then patterned by a photolithography process using a third mask to expose the drain electrode 163 and the capacitor electrode 165, respectively. The protective layer 170 having the second contact holes 171 and 172 is formed.

Subsequently, as illustrated in FIG. 7D, a transparent conductive material such as indium-tin-oxide (ITO) is deposited and the pixel electrode 181 is formed by a photolithography process using a fourth mask. One end is connected to the drain electrode 163 through the first contact hole 171, and one end parallel to the gate wiring 121 is overlapped with the capacitor electrode 165 to be connected to the capacitor electrode 165 through the second contact hole 172. The other end is partially overlapped with the light shielding pattern 164.

Thus, the manufacturing process can be reduced by manufacturing the array substrate for liquid crystal display devices using four masks.

FIG. 9 is a cross-sectional view of a liquid crystal display using an array substrate manufactured by the above method, and for convenience of description, only a black matrix is shown on the top.

As shown in FIG. 9, the black matrix 211 is disposed to correspond to a portion other than the pixel electrode 181 and overlaps the pixel electrode 181 at a predetermined interval. As mentioned above, the width B where the black matrix 211 and the pixel electrode 181 overlap is about 5 μm in consideration of the bonding margin. In this case, the pixel electrode 181 of the portion adjacent to the gate wiring 121 overlaps the light blocking pattern 164 parallel to the gate wiring 121, but the width of the light blocking pattern 164 not overlapping with the pixel electrode 181. (C) is about 2 μm in consideration of the gap between the gate wiring 121 and the pixel electrode 181.

This width C prevents light leakage from the black matrix 211 and the pixel electrode 181 in a portion adjacent to the gate wiring 121. Therefore, the bonding margin is increased from the conventional 5 mu m to 7 mu m.

In the liquid crystal display array substrate according to the present invention, manufacturing costs can be reduced by manufacturing using four masks, and a light shielding pattern in a direction parallel to the gate wiring is formed of a material such as data wiring to partially overlap the pixel electrode. Improve process margins Therefore, the light leakage defect can be prevented.

Claims (8)

Board; A plurality of gate lines having one direction on the substrate and a gate electrode connected to the gate lines; A gate insulating film formed over the gate wiring and the gate electrode; A semiconductor layer formed on the gate insulating layer; An ohmic contact layer formed on the semiconductor layer; A data wire formed on the ohmic contact layer and orthogonal to the gate wire, a source electrode extending from the data wire, and a drain electrode disposed opposite the source electrode; A light blocking pattern made of the same material as the data line and extending in a direction parallel to the gate line; A protective layer formed on the data line, the source and drain electrodes, and the light shielding pattern, and having a contact hole partially exposing the drain electrode; A pixel electrode formed on the passivation layer and connected to the drain electrode and overlapping a part of the light blocking pattern; Array substrate for a liquid crystal display device comprising a. The method of claim 1, The ohmic contact layer has the same shape as the data line, the source and drain electrodes, and the semiconductor layer has the same shape as the data line, the source and drain electrodes except between the source and drain electrodes. Array substrate for. The method of claim 1, And a width of a portion of the light blocking pattern not overlapping with the pixel electrode is 2 μm. The method of claim 1, And the light blocking pattern is connected to the drain electrode. The method of claim 1, And a capacitor electrode made of the same material as the data line and partially overlapping with the gate line and connected to the pixel electrode. Providing a substrate; Depositing a metal material on the substrate and patterning with a first mask to form a gate wiring and a gate electrode; Sequentially depositing a gate insulating film, an amorphous silicon layer, an impurity amorphous silicon layer, and a metal layer on the gate wiring; Patterning the metal layer, the impurity amorphous silicon layer, and the amorphous silicon layer with a second mask in sequence to form a semiconductor layer, an ohmic contact layer, a data line, a source electrode and a drain electrode, and a light shielding pattern; Depositing an insulating material on the data line and forming a protective layer having a contact hole partially exposing the drain electrode through a patterning process using a third mask; Depositing a transparent conductive material on the passivation layer and patterning the semiconductor layer by using a fourth mask to form a pixel electrode connected to the drain electrode through the contact hole and partially overlapping the light blocking pattern Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 6, The light blocking pattern is connected to the drain electrode. The method of claim 6, And the second mask has a plurality of slit patterns in a portion corresponding to the source and drain electrodes.