KR101006474B1 - array substrate for liquid crystal display device and manufacturing method of the same - Google Patents

Abstract

The present invention relates to an array substrate for a liquid crystal display device and a method of manufacturing the same.

The array substrate for a liquid crystal display device is formed by depositing a thin film and performing a photolithography process. Since the photolithography process involves several processes, the photolithography process can be reduced, thereby reducing manufacturing costs and reducing the incidence of defects.

The array substrate for a liquid crystal display device according to the present invention can be manufactured using three masks, thereby reducing manufacturing costs and shortening process time. In addition, the failure rate can be reduced to improve the production yield.

Description

Array substrate for liquid crystal display device and manufacturing method thereof             

1 is a plan view of a conventional array substrate for a liquid crystal display device.

2A to 2F are cross-sectional views illustrating a conventional manufacturing process of an array substrate for a liquid crystal display device, and correspond to a cross section taken along the line II-II of FIG. 1.

3A to 3F are cross-sectional views illustrating a manufacturing process of a conventional array substrate for a liquid crystal display device, and correspond to a cross section taken along line III-III of FIG. 1.

4A to 4F are cross-sectional views illustrating a conventional manufacturing process of an array substrate for a liquid crystal display device, and correspond to a cross section taken along line IV-IV in FIG. 1.

5 is a plan view of an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

6A to 6F are cross-sectional views illustrating a manufacturing process of an array substrate for a liquid crystal display device according to the present invention, which corresponds to a cross section taken along a line VI-VI in FIG. 5.

7A to 7F are cross-sectional views illustrating a manufacturing process of an array substrate for a liquid crystal display device according to the present invention, which corresponds to a cross section taken along the line VII-VII in FIG. 5.

8A to 8F are cross-sectional views illustrating a manufacturing process of an array substrate for a liquid crystal display device according to the present invention, which corresponds to a cross section taken along the line VIII-VIII in FIG. 5.

<Description of Symbols for Main Parts of Drawings>

112: gate wiring 114: gate electrode

116: gate pad 122: active layer

132: date wiring 134: source electrode

136; Drain Electrode 138: Data Pad

139: capacitor electrode 150: protective layer

152: opening 154: gate pad contact hole

156: data pad contact hole 162: pixel electrode

164: gate pad terminal 166: data pad terminal

T: thin film transistor P: pixel region

The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device and a manufacturing method thereof.

In general, a liquid crystal display device is formed by arranging two substrates having electrodes formed on one surface thereof so that the surfaces on which the two electrodes are formed face each other, injecting a liquid crystal material between the two substrates, and then applying a voltage to the two electrodes. By moving the liquid crystal molecules by an electric field, the device expresses an image by the transmittance of light that varies accordingly.

A liquid crystal display can be formed in various forms. Currently, an active matrix liquid crystal display (AM-LCD) having a thin film transistor and pixel electrodes connected to the thin film transistor in a matrix manner has excellent resolution and video performance. It is the most noticeable.

The liquid crystal display device has a structure in which pixel electrodes are formed on a lower array substrate, and a common electrode is formed on a color filter substrate, which is an upper substrate, and drives liquid crystal molecules by an electric field perpendicular to a substrate that is vertically stretched. to be. This is excellent in characteristics such as transmittance and aperture ratio, and the common electrode of the upper plate serves as a ground, thereby preventing the destruction of the liquid crystal cell due to static electricity.

The upper substrate of the liquid crystal display device further includes a black matrix to prevent light leakage occurring in portions other than the pixel electrode.

On the other hand, the array substrate, which is the lower substrate of the liquid crystal display device, is formed by repeatedly depositing a thin film and performing a photolithography process using a mask. The number of masks represents the number of processes for manufacturing the array substrate. Typically, 5 to 6 masks are used, and a method of reducing the production cost by manufacturing a lower substrate using four masks is known and used.

Hereinafter, a conventional array substrate for a liquid crystal display device and a method of manufacturing the same will be described with reference to the accompanying drawings.

1 is a plan view of a conventional array substrate for a liquid crystal display device.

As shown in FIG. 1, the gate wiring 12 extends in the horizontal direction, and the data wiring 32 extends in the vertical direction. The gate line 12 and the data line 32 cross each other to define the pixel region P. As shown in FIG. The gate pad 16 is formed at one end of the gate wiring 12, and the data pad 38 is formed at one end of the data wiring 32.

The thin film transistor T is formed at the intersection of the gate wiring 12 and the data wiring 32. The thin film transistor T includes the gate electrode 14 connected to the gate wiring 12 and the data wiring 32. Source electrode 34 connected to the source electrode 34, the drain electrode 36 facing the source electrode 34 with respect to the gate electrode 14, and the gate electrode 14 and the source and drain electrodes 34, 36. ) And an active layer 22 positioned between them.

In the pixel region P, a pixel electrode 62 connected to the thin film transistor T is formed. The pixel electrode 62 overlaps a portion of the drain electrode 36, and a drain contact hole is disposed at the portion where the pixel electrode 62 and the drain electrode 36 overlap with each other so that the pixel electrode 62 and the drain electrode 36 contact each other. 52 is located. In addition, the pixel electrode 62 overlaps the gate wiring 12 of the front end to form a storage capacitor.

Meanwhile, the gate pad terminal 64 and the data pad terminal 66 overlap the gate pad 16 and the data pad 38, respectively, and the gate pad contact is formed on the gate pad terminal 64 and the data pad terminal 66. The hole 54 and the data pad contact hole 56 are formed, respectively, so that the gate pad terminal 64 and the data pad terminal 66 are connected to the gate pad 16 and the data pad 38, respectively.

The manufacturing process of the array substrate for the liquid crystal display device is illustrated in FIGS. 2A to 2F, 3A to 3F, and 4A to 4F. 2A to 2F correspond to a cross section taken along line II-II in FIG. 1, and FIGS. 3A to 3F correspond to a cross section taken along line III-III in FIG. 1, and FIGS. 4A to 4F are FIG. 1. Corresponds to the section taken along line IV-IV at.

2A, 3A, and 4A, the gate wiring 14, the gate electrode 12, and the gate pad 16 are deposited by depositing a metal material on the substrate 10 and patterning using a first mask. Form.

Next, as shown in FIGS. 2B, 3B, and 4B, the gate insulating film 20, the pure amorphous silicon layer 26, the amorphous silicon layer 27 doped with impurities, and the metal layer 28 are sequentially deposited. After the photoresist film is applied thereon, the photosensitive film pattern 29 is formed by exposure and development using a second mask. The photoresist pattern 29 may include a first thickness 29a corresponding to a portion where the data line and the source and drain electrodes and a data pad are to be formed, and a portion between the source and drain electrodes and smaller than the first thickness 29a. It has two thicknesses 29b. The photoresist pattern 29 may be formed using a mask including a plurality of slits or a semi-transmissive layer in a portion corresponding to the second thickness 29b.

As shown in FIGS. 2C, 3C, and 4C, the amorphous silicon layer 27 and the pure amorphous silicon layer 26 including the metal layer 28 and impurities are masked using the photoresist pattern 29 of FIGS. 2B, 3B, and 4B. Patterning to form a data line (not shown) and a source / drain pattern 28a connected to the data line, a data pad 38 positioned at one end of the data line, an impurity semiconductor pattern 24a, and an active layer 22. do. Meanwhile, a pure amorphous silicon pattern 26a and an amorphous silicon pattern 27a doped with impurities are formed under the data pad 38. Subsequently, the photoresist pattern 29b of the second thickness is removed using a method such as ashing to expose the source / drain pattern 28a. At this time, the photosensitive film pattern 29a of the 1st thickness is also removed, and thickness becomes thin.

Next, as shown in FIGS. 2D, 3D, and 4D, the source / drain pattern 28a and the impurity semiconductor pattern 24a below are removed to remove the source and drain electrodes 34 and 36 and the ohmic contact layer 24. ), The remaining photoresist pattern 29a is removed.

Next, as shown in FIGS. 2E, 3E, and 4E, a silicon nitride film, a silicon oxide film, or an organic insulating film is formed, and then patterned by a photolithography process using a third mask to form a drain contact hole 52 and a gate pad contact hole 54. And a protective layer 50 having the data pad contact hole 56. The drain contact hole 52, the gate pad contact hole 54, and the data pad contact hole 56 expose the drain electrode 36, the gate pad 16, and the data pad 38, respectively.

Subsequently, as illustrated in FIGS. 2F, 3F, and 4F, a transparent conductive material such as indium-tin-oxide (ITO) is deposited, and the pixel electrode 62 and the pixel electrode 62 are subjected to a photolithography process using a fourth mask. Gate pad terminal 64 and data pad terminal 66 are formed. The pixel electrode 62 is connected to the drain electrode 36 through the drain contact hole 52, and overlaps the gate wiring 12 to form a storage capacitor. The gate pad terminal 64 is connected to the gate pad 16 through the gate pad contact hole 54, and the data pad terminal 66 is connected to the data pad 38 through the data pad contact hole 56.

As such, the array substrate may be manufactured by a photolithography process using four masks. However, since the photolithography process involves various processes such as cleaning, application of photoresist, exposure, development, and etching, it is still required to reduce the number of masks to manufacture the array substrate, thereby reducing the manufacturing cost and manufacturing time and reducing the incidence of defects. It is becoming.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an array substrate for a liquid crystal display device and a method of manufacturing the same, which can reduce a manufacturing process and manufacturing cost and improve a production yield. will be.

According to an exemplary embodiment of the present invention, an array substrate for a liquid crystal display device includes a substrate, a gate wiring, a gate electrode and a gate pad formed on the substrate, and an upper portion of the gate wiring, a gate electrode, and a gate pad. A gate insulating film, an active layer formed on the gate insulating film, an ohmic contact layer formed on the active layer, a data wiring and a source electrode, a drain electrode, and a data pad formed on the ohmic contact layer, and the data wiring And a gate pad contact hole and a data pad formed on the source electrode, the drain electrode, and the data pad, the opening corresponding to the pixel area defined by the gate wiring and the data wiring, and exposing the opening and the gate pad to expose the drain electrode. Exposed data pad contact hole A protective layer, a pixel electrode formed in the opening, a gate pad terminal formed in the gate pad contact hole, and a data pad terminal formed in the data pad contact hole, wherein the data pad terminal includes the data pad. Make side contact with

The data pad terminal may contact the substrate.

In addition, the pixel electrode is in side contact with the drain electrode and may be in contact with the substrate.

The present invention may further include a capacitor electrode formed of the same material as the data line on the gate line. In this case, the opening may expose the side surface of the capacitor electrode, and the pixel electrode may be in side contact with the capacitor electrode.

A method of manufacturing an array substrate for a liquid crystal display according to the present invention includes forming a gate wiring, a gate electrode, and a gate pad on a substrate, a gate insulating film, an amorphous silicon layer, and an impurity amorphous layer on the gate wiring, the gate electrode, and the gate pad. Sequentially depositing a silicon layer and a metal layer; patterning the metal layer, the impurity amorphous silicon layer, and the amorphous silicon layer in a single photolithography process to form an active layer, an ohmic contact layer, a data line, a source electrode, a drain electrode, and data Forming a pad, depositing and patterning an insulating material over the data line to expose an opening corresponding to the pixel area defined by the gate line and the data line and a gate pad contact hole exposing the gate pad and the data pad; Data pad contact hole Forming a protective layer; depositing and patterning a transparent conductive material to form a pixel electrode positioned in the opening, a gate pad terminal located in the gate pad contact hole, and a data pad terminal located in the data pad contact hole. And the data pad terminal is in side contact with the data pad.

The forming of the pixel electrode, the gate pad terminal, and the data pad terminal may use a lift-off method.

The forming of the passivation layer may include a dry etching method, and the forming of the passivation layer may include removing the data pad and the gate insulating layer corresponding to the data pad contact hole. In addition, the forming of the protective layer may include removing the drain electrode, the ohmic contact layer, the active layer, and the gate insulating layer corresponding to the opening.

The forming of the active layer and the ohmic contact layer, the data line, the source electrode, the drain electrode, and the data pad may include forming a capacitor electrode overlapping the gate line. In this case, the forming of the protective layer may include exposing the side surface of the capacitor electrode by removing the capacitor electrode corresponding to the opening.

As described above, in the present invention, the manufacturing cost can be reduced by manufacturing the array substrate using three masks, the process time can be shortened, and the production yield can be improved.

Hereinafter, an array substrate for a liquid crystal display device and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, FIG. 5 is a plan view of an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention. As shown in FIG. 5, the gate wiring 112 extends in the horizontal direction, and the data wiring 132 extends in the vertical direction. The gate line 112 and the data line 132 intersect to define the pixel area P. FIG. A gate pad 116 is formed at one end of the gate line 112, and a data pad 138 is formed at one end of the data line 132.

The thin film transistor T is formed at the intersection of the gate wiring 112 and the data wiring 132. The thin film transistor T includes the gate electrode 114 connected to the gate wiring 112 and the data wiring 132. The source electrode 134 connected to the source electrode 134, the drain electrode 136 spaced apart from the source electrode 134, facing the gate electrode 114, and the gate electrode 114 and the source and drain electrodes 134. And an active layer 122 positioned between 136. In addition, a capacitor electrode 139 is formed, and the capacitor electrode 139 overlaps the gate wiring 112 to form a storage capacitor.

On the other hand, a protective layer 150 is formed on the entire surface of the substrate, and the protective layer 150 has an opening 152 in the pixel region P, and gate pad contacts on the gate pad 116 and the data pad 138. It has a hole 154 and a data pad contact hole 156, respectively.

Next, the pixel electrode 162 is formed in the opening 152 of the pixel region P, and the gate pad terminal 164 and the data pad are formed in the gate pad contact hole 154 and the data pad contact hole 156. Contact holes 166 are formed respectively. The pixel electrode 162 is in lateral contact with the drain electrode 136 and the capacitor electrode 139, respectively, and the data pad terminal 166 is in lateral contact with the data pad 138.

6A to 6F, 7A to 7F, and 8A to 8F illustrate a manufacturing process of an array substrate for a liquid crystal display according to the present invention. 6A to 6F correspond to a cross section taken along line VI-VI in FIG. 5, and FIGS. 7A to 7F correspond to a cross section taken along line VII-VII in FIG. 5, and FIGS. 8A to 8F are FIG. 5. Corresponds to the section taken along line VIII-VIII at.

6A, 7A, and 8A, the gate wiring 114 and the gate electrode 112 are deposited by depositing a conductive material such as a metal on the insulating substrate 110 and patterning the same through a photolithography process using a first mask. ) And the gate pad 116. The gate wiring 114 extends in one direction, the gate electrode 112 protrudes from the gate wiring 114, and the gate pad 116 is positioned at one end of the gate wiring 112.                     

Next, as illustrated in FIGS. 6B, 7B, and 8B, the gate insulating layer 120, the pure amorphous silicon layer 126, the amorphous silicon layer 127 doped with impurities, and the metal layer 128 are sequentially deposited. After the photoresist is coated, the first photoresist pattern 129 is formed by exposure and development using a second mask. The first photoresist layer pattern 129 may correspond to a portion between the source line and the drain electrode and a first thickness 129a corresponding to a portion where a data line and a source and drain electrode, a capacitor electrode, and a data pad are to be formed. Have a second thickness 129b smaller than 129a. The first photoresist layer pattern 129 may be formed using a mask including a plurality of slits or a semi-transmissive layer in a portion corresponding to the second thickness 129b.

As shown in FIGS. 6C, 7C and 8C, the first photoresist layer pattern 129 of FIGS. 6B, 7B and 8B is an etch mask, and the amorphous silicon layer 127 and the pure amorphous silicon layer including the metal layer 128 and impurities are etched. Patterned 126 is a data wiring (not shown) and a source / drain pattern 128a connected to the data wiring, a data pad 138 positioned at one end of the data wiring, and a capacitor electrode positioned on the gate wiring 112. 139 and the impurity semiconductor pattern 124a and the active layer 122 positioned on the gate electrode 114 are formed. The first pure amorphous silicon pattern 126a and the amorphous silicon pattern 127a doped with the first impurity are formed under the data pad 138, and the second pure amorphous silicon pattern 126b under the capacitor electrode 139. ) And the amorphous silicon pattern 127b doped with the second impurity are formed. Although not shown, a semiconductor pattern having the same shape as that of the data line and consisting of pure amorphous silicon and amorphous silicon doped with impurities is formed under the data line. Subsequently, the first photoresist pattern (129b of FIG. 6B) of the second thickness is removed using a method such as ashing to expose the source / drain pattern 128a. At this time, the first photosensitive film pattern 129a of the first thickness is also removed to reduce the thickness.

Next, the source / drain electrodes 134 and 136 are removed by removing the source / drain patterns (128a of FIG. 6C) and the impurity semiconductor pattern (124a of FIG. 6C) that are exposed as shown in FIGS. 6D, 7D, and 8D. After the ohmic contact layer 124 is completed, the remaining first photoresist pattern 129a is removed.

Next, as shown in FIGS. 6E, 7E, and 8E, a silicon nitride film or a silicon oxide film is deposited or an organic insulating film is applied to form a protective layer 150. After the photosensitive film is applied, exposure and development are performed using a third mask. The second photosensitive film pattern 190 is formed. Subsequently, the lower protective layer 150 and the gate insulating layer 116 are etched using the second photoresist pattern 190 as a mask to form the opening 152, the gate pad contact hole 154, and the data pad contact hole 156. do. Here, the protective layer 150 is etched by a dry etching method, and may be removed together when the source and drain electrodes 134 and 136 are formed of a material such as molybdenum (Mo). Thus, as shown, the drain electrode 136 corresponding to the opening 152, the ohmic contact layer 124 and the active layer 122 below, and the capacitor electrode 139 and the second pure amorphous below it The silicon pattern 126b and the amorphous silicon pattern 127b doped with the second impurity are also removed to expose the side surface of the drain electrode 136 and the capacitor electrode 139 and the substrate 110. In addition, the data pad 138 corresponding to the data pad contact hole 156, the first pure amorphous silicon pattern 126a and a lower portion of the amorphous silicon pattern 127a doped with the first impurity are also removed. Expose the side of 138 and the substrate 110. In this case, the gate pad 116 is not etched, and the gate pad contact hole 154 exposes the surface of the gate pad 116.

Subsequently, a transparent conductive material such as indium-tin-oxide (ITO) is deposited and a second photoresist pattern (190 of FIGS. 6E, 7E, and 8E) is formed by using a lift-off method. Remove Accordingly, as illustrated in FIGS. 6F, 7F, and 8F, the pixel electrode 162 located in the opening 152 and the gate pad terminal 164 and the data pad contact hole 156 located in the gate pad contact hole 154 may be provided. Forming a data pad terminal 166 located therein. The pixel electrode 162 is in side contact with the drain electrode 136 and the capacitor electrode 139, and is also in contact with the substrate 165. The gate pad terminal 164 is in contact with the exposed surface of the gate pad 116, and the data pad terminal 166 is in side contact with the data pad 138 and is also in contact with the substrate 110.

As such, by manufacturing the array substrate for the liquid crystal display using three masks, the manufacturing process and the cost can be reduced, and the production yield can be improved.

The present invention is not limited to the above embodiments, and various changes and modifications can be made without departing from the spirit of the present invention.

The array substrate for a liquid crystal display device according to the present invention can be manufactured using three masks, thereby reducing manufacturing costs and shortening the processing time. In addition, the failure rate can be reduced to improve the production yield.

Claims (14)

Board; A gate wiring, a gate electrode, and a gate pad formed on the substrate; A gate insulating film formed over the gate wiring, the gate electrode, and the gate pad; An active layer formed on the gate insulating layer; An ohmic contact layer formed on the active layer; A data line, a source electrode, a drain electrode, and a data pad formed on the substrate including the ohmic contact layer; An opening formed on the data line, the source electrode, the drain electrode, and the data pad, and etched together with the gate insulating layer to correspond to the pixel area defined by the gate line and the data line and to expose a side surface of the drain electrode; A protective layer having a gate pad contact hole exposing the gate pad and a data pad contact hole penetrating the data pad to expose a side surface of the data pad and the substrate; A pixel electrode formed in the opening, a gate pad terminal formed in the gate pad contact hole, and a data pad terminal formed in the data pad contact hole. Including; And the data pad terminal is in side contact with the data pad. The method of claim 1, And the data pad terminal is in contact with the substrate. The method of claim 1, And the pixel electrode is in side contact with the drain electrode. The method of claim 3, wherein And the pixel electrode is in contact with the substrate. The method of claim 1, And a capacitor electrode formed of the same material as the data line on the gate line. The method of claim 5, And the opening portion exposes a side surface of the capacitor electrode. The method of claim 6, And the pixel electrode is in side contact with the capacitor electrode. Forming a gate wiring, a gate electrode, and a gate pad on the substrate; Sequentially depositing a gate insulating film, an amorphous silicon layer, an impurity amorphous silicon layer, and a metal layer on the gate wiring, the gate electrode, and the gate pad; Patterning the metal layer, the impurity amorphous silicon layer, and the amorphous silicon layer in a single photolithography process to form an active layer, an ohmic contact layer, a data line, a source electrode, a drain electrode, and a data pad; An insulating material is deposited on the data line, the source electrode, the drain electrode, and the data pad, and patterned together with the gate insulating layer to correspond to the pixel area defined by the gate line and the data line, and the side surface of the drain electrode. Forming a protective layer having an opening to expose the gate pad, a gate pad contact hole to expose the gate pad, and a data pad contact hole to penetrate the data pad to expose a side surface of the data pad and the substrate; Depositing and patterning a transparent conductive material to form a pixel electrode located in the opening, a gate pad terminal located in the gate pad contact hole, and a data pad terminal located in the data pad contact hole Including; And the data pad terminal is in side contact with the data pad. The method of claim 8, And forming the pixel electrode, the gate pad terminal, and the data pad terminal using a lift-off method. The method of claim 8, Forming the protective layer is a method of manufacturing an array substrate for a liquid crystal display device using a dry etching method. The method of claim 10, The forming of the passivation layer includes removing the data pad and the gate insulating layer corresponding to the data pad contact hole. The method of claim 10, The forming of the passivation layer includes removing the drain electrode, the ohmic contact layer, the active layer, and the gate insulating layer corresponding to the opening. The method of claim 8, And forming an active layer, an ohmic contact layer, a data line, a source electrode, a drain electrode, and a data pad include forming a capacitor electrode overlapping the gate line. The method of claim 13, The forming of the protective layer includes removing the capacitor electrode corresponding to the opening to expose a side surface of the capacitor electrode.

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