KR100968562B1 - Liquid crystal display - Google Patents

Abstract

       The thin film transistor array panel according to the exemplary embodiment of the present invention may include at least a portion of an insulating substrate, a gate line formed on the insulating substrate, a gate line having a gate electrode, a gate insulating film formed on the gate line, a semiconductor layer formed on the gate insulating film, and a semiconductor layer. An overlapping source electrode, a data line connected to the source electrode and having a portion intersecting the gate line and a bent portion, a drain electrode facing the source electrode with the center of the gate electrode at least partially overlapping the semiconductor layer, a protective film covering the semiconductor layer, And a pixel electrode formed on the passivation layer and electrically connected to the drain electrode and positioned adjacent to the data line at a predetermined distance from the data line.

       Thin film transistor, curved data line, sustain electrode line

Description

       Liquid Crystal Display {LIQUID CRYSTAL DISPLAY}

       1 is a layout view of a thin film transistor array panel according to a first exemplary embodiment of the present invention.

       2 is a layout view of a color filter display panel according to a first exemplary embodiment of the present invention;

       3 is a layout view of a liquid crystal display according to a first exemplary embodiment of the present invention;

       4 is a cross-sectional view taken along the line IV-IV ′ of FIG. 3,

       5A, 6A, 7A, and 8A are layout views in an intermediate step of manufacturing a thin film transistor array panel for a liquid crystal display according to a first embodiment of the present invention.

       5B is a cross-sectional view taken along the line Vb-Vb ′ of FIG. 5A.

       FIG. 6B is a sectional view at the next step of FIG. 6B,

       FIG. 7B is a cross sectional view at the next step of FIG. 6B;

       FIG. 8B is a cross sectional view at the next step of FIG. 7B;

       9 is a layout view of a thin film transistor array panel according to a second exemplary embodiment of the present invention.

       10 is a cross-sectional view taken along the line IX-IX ′ of FIG. 9,

       13A, 17A, and 18A are layout views in an intermediate step of manufacturing a thin film transistor array panel for a liquid crystal display according to a second embodiment of the present invention.                 

       FIG. 13B is a cross-sectional view taken along the line XIIIb-XIIIb ′ of FIG. 13A,

       14 is a sectional view at the next step of FIG. 13B,

       FIG. 15 is a sectional view at the next step of FIG. 14;

       16 is a sectional view at the next step of FIG. 15,

       FIG. 17B is a sectional view at the next stage of FIG. 16;

       FIG. 18B is a sectional view at the next step in FIG. 17B.

       Description of the Related Art [0002]

       110, 210: insulated substrate 121: gate line

       140: gate insulating film 151: semiconductor layer

       161, 165: ohmic contact layer

       171, 173: data line 175: drain electrode

       190 pixel electrode 220 shading pattern

       230R, 230G, 230B: Red, Green, Blue Color Filter

       The present invention relates to a thin film transistor array panel, and more particularly, to a thin film transistor array panel for a liquid crystal display device.

       In general, a liquid crystal display device injects a liquid crystal material between an upper display panel on which a common electrode, a color filter, and the like are formed, and a lower display panel on which a thin film transistor and a pixel electrode are formed. By applying a different potential to form an electric field to change the arrangement of the liquid crystal molecules, and through this to control the light transmittance is a device that represents the image.

       However, it is an important disadvantage that the liquid crystal display device has a narrow viewing angle. In order to overcome these disadvantages, various methods for widening the viewing angle have been developed. Among them, liquid crystal molecules are oriented vertically with respect to the upper and lower display panels, and a method of forming a constant incision pattern or forming protrusions on the pixel electrode and the common electrode that is opposite thereto. This is becoming potent.

       However, in the method of forming the protrusions or the incision pattern, the opening ratio is lowered due to the protrusions or the incision pattern portion. In order to compensate for this, an ultra-high-aperture structure that forms the pixel electrode as wide as possible has been devised. However, since the distance between adjacent pixel electrodes is very close, a lateral field formed between the pixel electrodes is strongly formed. Accordingly, the liquid crystals positioned at the edges of the pixel electrodes are affected by the lateral electric field, and thus the alignment is disturbed, resulting in texture or light leakage.

       In addition, when the storage electrode line for increasing the storage capacitance of the pixel is formed, the liquid crystal is disturbed by the influence of the lateral electric field caused by the storage electrode line. Thus, the sustain electrode line is completely covered by the pixel electrode to minimize the influence of the lateral electric field due to the sustain electrode line. In this case, since the black matrix of the upper panel is formed to cover not only the data line but also the boundary line of the pixel electrode, the aperture ratio of the pixel is reduced and the luminance is reduced.

       SUMMARY OF THE INVENTION The present invention provides a thin film transistor array panel capable of reducing light leakage generated at an edge of a pixel electrode and increasing an aperture ratio of a pixel.

       In order to solve this problem, the present invention provides the following thin film transistor array panel.

       Specifically, the thin film transistor array panel according to the exemplary embodiment of the present invention may include an insulating substrate, a gate line having a gate electrode formed on the insulating substrate, a gate insulating film formed on the gate line, a semiconductor layer formed on the gate insulating film, and a semiconductor layer; A source electrode having at least a portion overlapping the source electrode, a data line having a portion intersecting the gate line and a bent portion, a drain electrode opposing the source electrode with the gate electrode at least partially overlapping the semiconductor layer, and a semiconductor layer And a pixel electrode formed over the passivation layer and over the passivation layer, the pixel electrode being electrically connected to the drain electrode and positioned adjacent to the data line.

       The semiconductor device may further include a storage electrode line extending in a direction parallel to the gate line and a storage electrode line, the first and second storage electrodes being formed in the pixel area and parallel to the curved portion of the data line. It is preferable that a portion of the silver pixel electrode overlap with each other.                     

       In this case, the data line and the drain electrode preferably have the same planar pattern as the ohmic contact layer, and the ohmic contact layer is preferably formed in the same plane pattern except for the channel portion between the drain electrode and the source electrode.

       A portion of the storage electrode line overlaps the drain electrode, and is preferably formed to be larger than the width of the storage electrode line.

       Further, the curved portion of the data line preferably includes a portion that forms a 45 degree angle with respect to the gate line and a portion which forms a -45 degree angle with respect to the gate line. At this time, the protective film is preferably formed of an inorganic material.

       DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

       In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

       [First Embodiment]

       1 is a layout view of a thin film transistor array panel according to a first exemplary embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line II-II ′ of FIG. 1, and FIG. 3 is a thin film transistor according to the first exemplary embodiment of the present invention. 4 is a layout view of a display panel, and FIG. 4 is a layout view of a color filter display panel according to a first exemplary embodiment of the present invention.

       Next, a thin film transistor array panel according to a first exemplary embodiment of the present invention will be described with reference to FIGS. 1, 2, and 3.

       In the thin film transistor array panel according to the first exemplary embodiment of the present invention, a gate line 121 extending in one direction is formed on the transparent insulating substrate 110. A portion of the gate line 121 or a branched portion is used as the gate electrode 124 of the thin film transistor. One end 129 of the gate line 121 is used to receive a signal transmitted from a gate driving circuit (not shown) and may have a width wider than the width of the gate line 121.

       In order to increase the storage capacitance of the pixel, the storage electrode line 131 extending in parallel with the gate line 121 is formed. In this case, the storage electrode line 131 overlaps the drain electrode 175 in order to minimize the decrease of the aperture ratio of the pixel.

       A gate insulating layer 140 formed of silicon nitride, silicon oxide, or the like is formed on the substrate 110 to cover them 121, 124, and 131.

       A semiconductor layer 151 made of amorphous silicon without doping impurities is formed in a predetermined region of the gate insulating layer 140. The semiconductor layer 151 extends along the data line 171 under the data line 171 to be described later, and is linearly formed under the drain electrode 175 to be described later.                     

       In addition, ohmic contacts 161 and 165 including amorphous silicon or silicide doped with impurities are formed on the semiconductor layer 151. The ohmic contacts 161 and 165 are islands facing the portion of the linear portion 161 around the linear portion 161 and the gate electrode 124 extending along the data line 171 together with the semiconductor layer 151. It consists of a mold 165. The island portion 165 is formed at a predetermined distance away from the linear portion 161, and they have the same planar pattern as the semiconductor layer 151 except for a predetermined region of the semiconductor layer 151. The predetermined region of the semiconductor layer 151 is a channel portion that forms a channel of the thin film transistor.

       A data line 171 is formed on the gate insulating layer 140 and the ohmic contact layer 161 to cross the gate line 121 to define a pixel area. The data line 171 is branched and has a source electrode 173 overlapping the semiconductor layer 151. In this case, the data line 171 is formed such that a repeatedly curved portion and a vertically extending portion appear with a length of the pixel. In this case, the curved portion of the data line 171 is composed of two straight portions, one of the two straight portions forms 45 degrees with respect to the gate line 121, and the other portion with respect to the gate line 121. Achieve -45 degrees. The source electrode 173 is connected to a vertically extending portion of the data line 171, and the portion crosses the gate line 121 and the storage electrode line 131. Accordingly, the pixel region formed by the intersection of the gate line 121 and the data line 171 has a curved band shape.

       One end 179 of the data line may be wider than the width of the data line 171 to receive a signal transmitted from a data driving circuit (not shown).                     

       A drain electrode 175 is formed on the ohmic contact layer 165 facing the source electrode 173 at a predetermined distance from the gate electrode 124 and partially overlapping the semiconductor layer 151. In this case, the data line 171 is in contact with the linear portion 161 of the ohmic contact layer and the drain electrode 175 is in contact with the island portion 165.

       In the data line 171, a portion of the data line 171 connected to the pixel electrode 190 overlaps the storage electrode line 131. A constant voltage is applied to the storage electrode line 131 to form a storage capacitor between the storage electrode line 133, the storage electrodes 133a and 133b, and the drain electrode 175.

       The passivation layer 180 made of an inorganic insulating material such as silicon nitride is formed on the substrate 110 to cover the semiconductor layer 151 that is not covered by the data lines 171, 173, and 179 and the drain electrode 175. have.

       The passivation layer 180 is provided with contact holes 183 exposing the drain electrode 175, contact holes 181 and 182 exposing one end portions of the gate line 121 and the data line 171, respectively.

       The pixel electrode 190 is formed on the passivation layer 180 through the contact hole 183 and is connected to the drain electrode 175 and has a bent portion along the shape of the pixel region. In this case, the edge of the pixel electrode 190 is formed a predetermined distance away from the data line 171 and overlaps the sustain electrodes 133a and 133b. In addition, contact auxiliary members 81 and 82 are formed on the passivation layer 180 and are connected to the gate lines 121 and one ends 129 and 179 of the data line 171 through the contact holes 181 and 182. It is.                     

       Here, the pixel electrode 190 and the contact auxiliary members 81 and 82 are made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the contact auxiliary members 81 and 82 are connected to the outside. It is intended to complement the adhesiveness and is not essential and should be selected as necessary.

       An alignment film 11 is formed on the pixel electrode 190 to align the liquid crystal 3 vertically.

       Now, the color filter display panel will be described with reference to FIGS. 1, 2, and 4.

       A black matrix 220 and red, green, and blue color filters 230R, 230G, and 230B are formed on the lower surface of the upper substrate 210 made of a transparent insulating material such as glass, and the color filter. An overcoat film 250 made of an organic material is formed on the 230R, 230G, and 230B. On the overcoat layer 250, a common electrode 270 made of a transparent conductive material such as ITO or IZO and having domain dividing means 271 is formed. The domain dividing means 271 can be formed with cutouts or protrusions (not shown).

       The black matrix 220 may include a linear portion corresponding to the curved portion of the data line 171, a vertically extending portion of the data line 171, and a portion corresponding to the thin film transistor portion. The color filter 230 is formed vertically long along the pixel column defined by the black matrix 220, and is periodically bent along the shape of the pixel.

       The domain dividing means 271 of the common electrode 270 is also bent so as to divide the curved pixel region from side to side. The alignment layer 21 is formed on the common electrode 290. The alignment layer 21 vertically aligns the liquid crystal with the alignment layer 21.

       When the liquid crystal layer 3 is formed by combining the thin film transistor array panel and the color filter display panel having the above structure and injecting liquid crystal therebetween, the liquid crystal display device according to the first embodiment of the present invention is formed (FIGS. 1 and 2). Reference). At this time, the pixel electrode 190 is aligned to exactly overlap the color filters 230R, 230G, and 230B.

       The liquid crystal molecules included in the liquid crystal layer 3 are aligned such that their directors are perpendicular to the display panels 100 and 200 without an electric field applied between the pixel electrode 190 and the common electrode 270.

       In this way, the pixel region is divided into a plurality of domains by the domain dividing means 271. At this time, the pixel region is divided into left and right sides by the domain dividing means 271, but is divided into four domains in which the alignment directions of the liquid crystals are different from each other up and down around the bent portion of the pixel.

       The liquid crystal display is formed by disposing elements such as a polarizing plate (not shown) and a backlight (not shown) on both sides of the basic panel. In this case, one polarizer is disposed on each side of the base panel, and the transmission axis thereof is arranged to be parallel to or perpendicular to the gate line 121.

       When the liquid crystal display device is formed as described above, when an electric field is applied to the liquid crystal, the liquid crystal in each domain is inclined in a direction perpendicular to the long side of the domain. However, since this direction is perpendicular to the data line 171, the direction coincides with the direction in which the liquid crystal is inclined by a lateral electric field formed between two adjacent pixel electrodes 190 with the data line 171 therebetween. As a result, the lateral electric field assists the liquid crystal alignment of each domain.

       In this case, since the pixel electrode 190 and the data line 171 are formed at a predetermined distance, there is almost no coupling between the pixel electrode 190 and the data line 171.

       As such, since the liquid crystal at the edge of the pixel electrode 190 can be perfectly controlled by using the lateral electric field, light leakage or the like does not occur at the edge of the pixel electrode 190. Therefore, since the width of the black matrix of the upper panel can be minimized, the aperture ratio of the pixel can be improved to provide a high brightness liquid crystal display device.

       A method of manufacturing a thin film transistor array panel having such a structure will be described.

       5A, 6A, 7A, and 8A are layout views in an intermediate step of manufacturing a thin film transistor array panel for a liquid crystal display according to a first embodiment of the present invention, and FIG. 5B is a line Vb-Vb 'of FIG. 5A, FIG. 6B is a cross-sectional view taken along the line VIb-VIb 'of FIG. 6A, FIG. 7B is a line VIIb-VIIb' of FIG. 7A, and FIG. 8B is a line VIIIb-VIIIb 'of FIG. 8A.

       First, as shown in FIGS. 5A and 5B, chromium (Cr), molybdenum (Mo), aluminum (Al), silver (Ag), or alloys thereof are deposited by sputtering to form a gate metal film. The gate metal layer is dry or wet etched by a photolithography process using a mask to form the gate lines 121, 124, and 129 and the storage electrode lines 131.

       In this case, the metal film may be formed in a plurality of layers in order to reduce the resistance of the wiring, and the cross-sections of the gate lines 121, 124, and 129 and the storage electrode line 131 may be tapered during wet etching to increase adhesion to the upper layer. .

       Next, as shown in FIGS. 6A and 6B, the gate insulating layer 140, the hydrogenated amorphous silicon film, and the amorphous silicon film doped with a high concentration of n-type impurities such as phosphorus (P) are continuously deposited by chemical vapor deposition. The resistive contact layer 160 and the semiconductor layer 151 to which the channel part is connected are formed by patterning the doped amorphous silicon film and the amorphous silicon film in a photolithography process using a mask.

       7A and 7B, chromium, molybdenum, aluminum, silver, or alloys thereof are deposited by sputtering to form a data metal film, and the data metal film is dried or dried by a photolithography process using a mask. The wet etching process forms the data lines 171 and 173 and the drain electrode 175.

       In this case, the metal film may be formed in a plurality of layers in order to reduce the resistance of the wiring, and end surfaces of the gate lines 121, 124, and 129, the storage electrode lines 131, and the storage electrodes 133a and 133b may be tapered during wet etching. To improve adhesion to the top layer.

       Subsequently, the ohmic contact layer 160 that is not covered by the source electrode 173 and the drain electrode 175 is etched to expose the semiconductor layer 154 between the source electrode 173 and the drain electrode 175, and separated from each other. The ohmic contacts 163 and 165 are formed.

       Subsequently, as shown in FIGS. 8A and 8B, the passivation layer 180 is formed of an inorganic material such as silicon nitride, and then etched by a photolithography process through a mask to form one end portion of the gate line 121 and the data line 179. The contact holes 181 and 182 exposing () and the contact holes 183 exposing the drain electrode 175 are formed.

       In this case, the contact hole 181 exposing one end portion of the gate line is formed over the passivation layer 180 and the gate insulating layer 140.

       1 and 2, a transparent conductive film such as indium tin oxide (ITO) or indium zinc oxide (IZO) is formed on the entire surface of the substrate 110, and then patterned by a photolithography process to form the pixel electrode 190. ) And contact aid members 81, 82.

       Second Embodiment

       FIG. 9 is a layout view of a thin film transistor array panel according to a second exemplary embodiment of the present invention, and FIG. 10 is a cross-sectional view taken along the line IX-IX ′ of FIG. 9.

       In the second embodiment, unlike the first embodiment, the storage electrodes 133a and 133b are further formed on the storage electrode lines 131 by branches. The storage electrodes 133a and 133b are formed in parallel with the data line 171 at a predetermined distance apart. In this case, the boundary line of the pixel electrode 190 is formed on the sustain electrodes 133a and 133b.

       The storage electrodes 133a and 133b prevent light leakage that may occur between the data line 171 and the pixel electrode 190.

        Third Embodiment

       FIG. 11 is a layout view of a thin film transistor array panel according to a third exemplary embodiment of the present invention, and FIG. 12 is a cross-sectional view taken along the line XII-XII ′ of FIG. 11.

       In the third exemplary embodiment, the contact layers 161 and 165 are formed under the data lines 171, 173, and 179 and the drain electrode 175 in a substantially same pattern, and the source electrode 173 and the drain electrode 175 are formed. The semiconductor layer 151 also has substantially the same pattern as the data lines 171, 173, and 179 and the drain electrode 175 except that the channel portion between the two portions is connected. The third embodiment can form a thin film transistor array panel using fewer masks than the first embodiment.

       In addition, in the third embodiment, when the storage capacitance is not sufficient, a sustain electrode (not shown) may be formed as in the second embodiment.

       Next, a method of manufacturing a thin film transistor array panel having such a structure and method features will be described.

       13A, 17A, and 18A are layout views in an intermediate step of manufacturing a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 13B is cut along the line XIIIb-XIIIb ′ of FIG. 13A. 14 is a sectional view at the next step of FIG. 13B, FIG. 15 is a sectional view at the next step of FIG. 14, FIG. 16 is a sectional view at the next step of FIG. 15, and FIG. 17B is a next step of FIG. 16. 18B is a cross-sectional view at the next step in FIG. 17B.

       First, as shown in FIGS. 13A and 13B, a metal such as chromium, molybdenum, aluminum, silver, or an alloy thereof is deposited on the transparent insulating substrate 110 by sputtering to form a single layer or a plurality of gate metal layers. do. Thereafter, the metal film is dry or wet etched by a photolithography process to form gate lines 121, 124, and 129, storage electrode lines 131, and storage electrodes 133a and 133b on the substrate 110. In wet etching, the side surfaces of these 121, 124, 129, 131, 133a, and 133b are tapered, and the tapered shape allows the layers formed thereon to closely adhere to each other.

       14, an insulating material such as silicon nitride is deposited to cover the gate lines 121, 124, and 129, the storage electrode lines 131, and the storage electrode lines 133a and 133b to form the gate insulating layer 140. To form.

       The amorphous silicon film 150 doped with impurities and the amorphous silicon film 160 doped with impurities are sequentially stacked by depositing amorphous silicon without impurities and amorphous silicon doped with impurities on the gate insulating layer 140. do. The amorphous silicon film 150 not doped with impurities is formed of hydrogenated amorphous silicon, and the like, and the amorphous silicon film 160 doped with impurities is heavily doped with an n-type impurity such as phosphorus (P). It is formed of silicon or silicide.

       After depositing a metal such as aluminum, silver, chromium, molybdenum or an alloy thereof by sputtering on the amorphous silicon film 160 doped with impurities in succession to form a single layer or a plurality of metal films 170, A photosensitive material is coated on the metal layer 170 to form a photoresist film, and then exposed and developed to form photoresist patterns 52 and 54 having different thicknesses.

       As described above, there may be various methods of varying the thickness of the photoresist film according to the position, and the transparent mask and the light blocking area as well as the translucent area may be provided in the exposure mask. Yes. The translucent region is provided with a slit pattern, a lattice pattern, or a thin film having a medium transmittance or a medium thickness. When using the slit pattern, it is preferable that the width of the slit or the distance between the slits is smaller than the resolution of the exposure machine used for the photographic process. Another example is to use a photoresist film that can be reflowed. That is, a thin portion is formed by forming a reflowable photoresist pattern with a normal mask having only a transparent region and a light shielding region and then reflowing so that the photoresist film flows into an area where no photoresist remains.

       Given the appropriate process conditions, the underlying layers may be selectively etched due to the difference in thickness of the photoresist pattern 52, 54. Therefore, a plurality of data lines 171 and a plurality of drain electrodes 175 each including a plurality of source electrodes 173 as shown in FIG. 9 are formed through a series of etching steps, and a plurality of protrusions 163 are formed. A plurality of linear ohmic contacts 161, a plurality of island-like ohmic contacts 165, and a plurality of linear semiconductors 151 including a plurality of protrusions are formed.

       For convenience of description, a portion of the conductor layer 170 positioned at the portion where the wiring is to be formed, the amorphous silicon layer 160 doped with impurities, and the amorphous silicon layer 150 without doping impurities are referred to as the wiring portion A. The portion of the conductor layer 170, the impurity doped amorphous silicon layer 160 and the impurity doped amorphous silicon layer 150 located at the portion where the channel is formed is called a channel portion B, and the channel and wiring portions A portion of the conductor layer 170, the amorphous silicon layer 160 doped with impurities, and the amorphous silicon layer 150 not doped with impurities is located in the other region (C).

       One example of the order of forming such a structure is as follows.

       First, (1) removing the conductor layer 170, the impurity amorphous silicon layer 160 and the amorphous silicon layer 150 located in the other portion (C), (2) removing the photoresist film 54 located in the channel portion (B). , (3) removing the conductor layer 170 and the impurity amorphous silicon layer 160 located in the channel portion B, and (4) removing the photosensitive film 52 located in the wiring portion A.

       Other methods include (1) removing the conductor layer 170 located in the other portion (C), (2) removing the photosensitive film 54 located in the channel portion (B), and (3) impurity amorphous in the other portion (C). Removal of the silicon layer 160 and the amorphous silicon layer 150, (4) removal of the conductor layer located in the channel portion B, (5) removal of the photosensitive film 52 located in the wiring region A, and (6) channel portion. It may also proceed in order to remove the impurity amorphous silicon layer 160 located in (B).

       This section describes the first example.

       First, as illustrated in FIG. 15, the conductive layer 170 exposed to the other region C is removed by wet etching or dry etching, and the other portion C of the amorphous silicon layer 160 doped with impurities underneath it. Expose

       The data line 171 and the drain electrode 175 are still attached. In the case of using dry etching, the upper portions of the photoresist films 52 and 54 may be cut to a certain thickness.

       As shown in FIG. 16, the channel portion B may be removed by removing the amorphous silicon layer 160 doped with impurities located in the other portion C and the amorphous silicon layer 150 not doped with impurities below. The photosensitive film 54 is removed to expose the lower conductor 170.

       Removal of the photoresist of the channel portion B may be performed simultaneously with or separately from the removal of the amorphous silicon layer 160 doped with impurities in the other region C and the amorphous silicon layer 150 without the impurities. Residue of the photoresist film 54 remaining in the channel region B is removed by ashing. In this step, the semiconductor layer 151 is completed.

       Here, when the conductor layer 170 is a material that can be dry etched, the manufacturing process may be performed by continuously dry etching the amorphous silicon layer 160 doped with impurities below and the amorphous silicon layer 150 doped with impurities. In this case, it may or may not be performed in an in-situ manner in which dry etching is sequentially performed on the three layers 170, 160, and 150 in the same etching chamber.

       Next, as shown in FIGS. 17A and 17B, the conductor 170 located in the channel portion B and the amorphous silicon layer 160 doped with impurities are etched and removed. In addition, the photosensitive film 52 of the remaining wiring portion A is also removed.

       In this case, the upper portion of the amorphous silicon layer which is not doped with impurities in the channel portion B may be partially removed to reduce the thickness, and the photoresist layer 52 of the wiring portion A may be etched to some extent.

       In this way, each of the conductors 174 is completed while being separated into one data line 171 and a plurality of drain electrodes 175, and the amorphous silicon layer 160 doped with impurities also includes the linear ohmic contact layer 161. Completed by dividing into island resistive contact layer 165

       The data lines 171, 173, 179 and the drain electrode 175 may also be formed in a tapered shape like the gate lines 121, 124, and 129 to increase adhesion to the upper layer.

       Next, as shown in FIGS. 18A and 18B, the passivation layer 180 is formed on the substrate 110 using an inorganic material such as silicon nitride. Then, contact holes 181, 182, and 183 are formed in the passivation layer 180 by a photolithography process using a mask.

       11 and 12, a transparent conductive material such as ITO or IZO is deposited on the passivation layer 180, and is etched by a photolithography process using a mask to drain the electrode 175 through the contact hole 183. Contact auxiliary members 81 and 82 connected to one end portions 129 and 179 of the gate line and the data line, respectively, through the pixel electrode 190 and the contact holes 181 and 182 connected to each other. In this case, an edge of the pixel electrode 190 is positioned on the sustain electrodes 133a and 133b.

       Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, when the data line is refracted to form the pixel region in an oblique band shape, the lateral electric field between adjacent pixels acts in a direction to help the domain formation, thereby stably forming the domain. A sustain electrode is further formed between the pixel electrode and the data line to prevent light leakage between the pixel electrode and the data line, and the aperture ratio of the pixel region can be increased by overlapping the pixel electrode with the sustain electrode, thereby providing a high brightness thin film transistor array panel. .

Claims (7)

Insulation board, A gate line formed on the insulating substrate and having a gate electrode, A data line intersecting the gate line and including a bent portion; A thin film transistor connected to the gate line and the data line, A thin film transistor array panel including a pixel electrode connected to the thin film transistor, An opposite display panel including a common electrode facing the thin film transistor array panel, A liquid crystal layer positioned between the opposing display panel and the thin film transistor array panel Including, And a curved portion of the data line includes a portion that forms an angle of 45 degrees with respect to the gate line and a portion that forms an angle of -45 degrees with respect to the gate line.       In claim 1,        A storage electrode line extending in a direction parallel to the gate line;        First and second storage electrodes connected to the storage electrode lines and parallel to the curved portions of the data lines;        The first and second storage electrodes overlap with a boundary line of the pixel electrode. The method of claim 1 or 2, The common electrode includes domain dividing means extending in parallel with the bent portion of the data line, And the domain dividing means divides the pixel electrode left and right. delete        In claim 2,        And the storage electrode line overlaps the drain electrode and is formed to be larger than the width of the storage electrode line.        4. The method of claim 3,        The protective film is formed of an inorganic material.        4. The method of claim 3,        The pixel electrode has a portion bent along the data line.

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