KR20050010444A - Thin film transistor array panel and liquid crystal display include the same - Google Patents

Abstract

PURPOSE: A TFT display substrate and an LCD including the same are provided to overlap pixel electrodes by neighboring maintenance electrode lines for preventing the leakage of light and texture around gate lines. CONSTITUTION: A TFT display substrate includes gate lines(121) formed on an insulating substrate with gate electrodes, a gate insulating film formed on the gate lines, and a semiconductor layer(151) formed on the insulating film. Source electrodes overlap the semiconductor layer at least partially. Data lines(171) are formed with bent portions connected to the source electrodes and the other parts intersecting the gate lines. Drain electrodes face the source electrodes with respect to the gate electrodes and overlap the semiconductor layers at least partially. A protecting film covers the semiconductor layer. Pixel electrodes are connected to the drain electrodes and formed in pixel areas defined by the gate and data lines. The pixel electrodes have bent portions corresponding to bent portions of the data lines, and cutaway parts for dividing the pixel areas into upper and lower parts. Maintenance electrode lines(131) are in parallel to the gate lines. First and second maintenance electrodes(133a,133b) are formed in the pixel areas to be connected to the maintenance electrode lines. The first and second maintenance electrodes are in parallel to the bent portions of the data lines.

Description

Thin film transistor array panel and liquid crystal display including the same

The present invention relates to a thin film transistor array panel and a liquid crystal display device including the same.

In general, a liquid crystal display device injects a liquid crystal material between an upper display panel on which a common electrode, a color filter, and the like are formed, and a lower display panel on which a thin film transistor and a pixel electrode are formed. By applying a different potential to form an electric field to change the arrangement of the liquid crystal molecules, and through this to control the light transmittance is a device that represents the image.

However, it is an important disadvantage that the liquid crystal display device has a narrow viewing angle. In order to overcome these disadvantages, various methods for widening the viewing angle have been developed. Among them, liquid crystal molecules are oriented vertically with respect to the upper and lower display panels, and a method of forming a constant incision pattern or forming protrusions on the pixel electrode and the common electrode that is opposite thereto. There is this.

However, in the method of forming the protrusions or the incision pattern, the opening ratio is lowered due to the protrusions or the incision pattern portion. In order to compensate for this, an ultra-high-aperture structure that forms the pixel electrode as wide as possible has been devised. However, since the distance between adjacent pixel electrodes is very close, a lateral field formed between the pixel electrodes is strongly formed. Accordingly, the liquid crystals positioned at the edges of the pixel electrodes are affected by the lateral electric field, and thus the alignment is disturbed, resulting in texture or light leakage, thereby degrading display characteristics.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a thin film transistor array panel and a liquid crystal display including the same.

1 is a layout view illustrating a structure of a liquid crystal display according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the liquid crystal display of FIG. 1 taken along the line II-II ′,

3 is a cross-sectional view of the liquid crystal display of FIG. 1 taken along line III-III ′,

4 is a layout view of a thin film transistor array panel according to a first exemplary embodiment of the present invention.

5 is a layout view of a color filter display panel according to a first exemplary embodiment of the present invention;

6A, 7A, 8A, and 9A are layout views in an intermediate step of manufacturing a thin film transistor array panel according to a first exemplary embodiment of the present invention.

6B and 6C are cross-sectional views taken along the lines VIb-VIb ′ and VIc-VIc ′ of FIG. 6A, respectively.

7B and 7C are cross-sectional views at the next stage of FIGS. 6B and 6C,

8B and 8C are cross-sectional views at the next stage of FIGS. 7B and 7C;

9B and 9C are cross-sectional views at the next stage of FIGS. 8B and 8C;

10 is a layout view of a thin film transistor array panel according to a second exemplary embodiment of the present invention.

11 and 12 are cross-sectional views taken along the lines XI-XI ′ and XII-XII ′ of FIG. 11, respectively.

13 is a layout view of a thin film transistor array panel according to a third exemplary embodiment of the present invention.

14 and 15 are cross-sectional views taken along the lines XIV-XIV ′ and XV-XV ′ of FIG. 13, respectively.

16A, 19A, and 20A are layout views in an intermediate step of manufacturing a thin film transistor array panel according to a third exemplary embodiment of the present invention.

16B and 16C are cross-sectional views taken along lines XVIb-XVIb ′ and XVIc-XVIc ′ of FIG. 16A, respectively.

17A and 17B are layout views in an intermediate step of manufacturing a thin film transistor array panel according to a third exemplary embodiment of the present invention.

18A and 18B are cross-sectional views at the next stage of FIGS. 17A and 17B,

19B and 19C are cross-sectional views at the next step of FIGS. 18A and 18B,

20B and 20C are cross-sectional views at the next stage of FIGS. 19B and 19C,

FIG. 21 is a cross-sectional view of the liquid crystal display according to the fourth exemplary embodiment, taken along the line II-II ′ of FIG. 1.

FIG. 22 is a cross-sectional view of the liquid crystal display according to the fourth exemplary embodiment, taken along the line III-III ′ of FIG. 1.

* Description of symbols on the main parts of the drawings *

110, 210: insulated substrate 121: gate line

140: gate insulating film 151: semiconductor layer

161, 165: ohmic contact layer

171 and 173: data line 175: drain electrode

190: pixel electrode 230R, 230G, 230B: red, green, blue color filter

270 common electrode

In order to solve this problem, the present invention provides the following thin film transistor array panel and liquid crystal display device.

Specifically, an insulating substrate, a gate line formed on the insulating substrate and having a gate electrode, a gate insulating film formed on the gate line, a semiconductor layer formed on the gate insulating film, a source electrode at least partially overlapping the semiconductor layer, and a source electrode; A data line having a bent portion and a portion intersecting the gate line, a drain electrode facing the source electrode centering around the gate electrode and overlapping at least a portion of the semiconductor layer, a protective film covering the semiconductor layer, and a drain electrode And a pixel electrode having a bent shape along the curved portion of the data line in the pixel region divided by the line and the data line, and having a cutout that divides the pixel region up and down.

The storage electrode line extending in a direction parallel to the gate line and the storage electrode line may further include first and second storage electrodes formed in the pixel area and parallel to the curved portions of the data line.

In this case, it is preferable that the pixel electrode extends in the data line direction and at least partially overlaps the storage electrode line disposed in the neighboring pixel region. A portion of the storage electrode line overlaps the drain electrode, and is preferably formed to be larger than the width of the storage electrode line.

It is also desirable to have an ohmic contact layer formed over the semiconductor layer and having the same planar pattern as the semiconductor layer except for the channel between the source and drain electrodes.

In addition, the data line and the drain electrode preferably have the same planar pattern as the ohmic contact layer.

The liquid crystal display device for solving the above problems is a thin film transistor, a thin film transistor electrically connected to a gate line and a data line, a gate line and a data line to insulate and intersect the first insulating substrate, the first insulating substrate and define a pixel area. An upper display panel connected to the transistor and having a first cutout formed in a direction in which the gate line extends to divide the pixel region up and down, a second insulating substrate facing the first insulating substrate, and formed on the first or second insulating substrate And a red, green, blue color filter, and a color filter extending along a pixel column separated by data lines, and having a common electrode extending along the shape of the data line and having a first division part for dividing pixels from side to side. A lower panel, and a liquid crystal filled between the upper panel and the lower panel, and the data line crosses the gate line. It is desirable to have a portion to be filled and a bent portion.

The common electrode may further include a second division part formed in a direction parallel to the gate line and connected to the first division part.

And it is preferable that a part of a 2nd division part overlaps with a 1st incision part.

In addition, it is preferable to further include a storage electrode line extending in a direction parallel to the gate line, the first and second storage electrodes connected to the storage electrode line and formed in the pixel area and parallel to the curved portion of the data line.

In this case, it is preferable that the pixel electrode is formed to extend in the direction in which the data line extends and at least partially overlap the neighboring storage electrode line.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

[First Embodiment]

1 is a layout view of a liquid crystal display according to a first exemplary embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line II-II ′ of FIG. 1, and FIG. 3 is a liquid crystal according to the first exemplary embodiment of the present invention. 4 is a layout view of a thin film transistor array panel of a display device, and FIG. 4 is a layout view of a color filter display panel of a liquid crystal display device according to a first exemplary embodiment of the present invention.

In the liquid crystal display according to the first exemplary embodiment of the present invention, the thin film transistor array panel 100, the color filter panel 200 facing each other, and the liquid crystal molecules injected between and included in the two display panels 100 and 200. The major axis of is made of the liquid crystal layer 3 which is oriented perpendicular to these display panels.

Next, the thin film transistor array panel according to the first exemplary embodiment of the present invention will be described with reference to FIGS. 1 to 4.

In the thin film transistor array panel according to the first exemplary embodiment of the present invention, a gate line 121 extending in one direction is formed on the transparent insulating substrate 110. A portion of the gate line 121 or a branched portion is used as the gate electrode 124 of the thin film transistor. One end 129 of the gate line 121 is used to receive a signal transmitted from a gate driving circuit (not shown) and may have a width wider than the width of the gate line 121.

In order to increase the storage capacitance of the pixel, the storage electrode line 131 extending in parallel with the gate line 121 is formed. In this case, in order to minimize the reduction of the aperture ratio of the pixel, the pixel is disposed at an edge of the pixel area, and a part of the storage electrode line 131 overlaps the drain electrode 175. In addition, the storage electrode line 131 has the storage electrodes 133a and 133b extending in a direction parallel to the data line 171. In order to sufficiently secure the storage capacitor, a portion of the storage electrode line 131 overlapping the drain electrode 175 may have a wider width than other portions.

A gate insulating layer 140 formed of silicon nitride, silicon oxide, or the like is formed on the substrate 110 to cover the gate line 121 and the storage electrode line 131.

A semiconductor layer 151 made of amorphous silicon without doping impurities is formed in a predetermined region of the gate insulating layer 140. The semiconductor layer 151 extends along the data line 171 under the data line 171, which will be described later, and has a linear shape. The semiconductor layer 151 is extended to the bottom of the drain electrode 175, which will be described later in a protruding form 154. have.

In addition, ohmic contacts 161 and 165 including amorphous silicon or silicide doped with impurities are formed on the semiconductor layer 151. The ohmic contacts 161 and 165 are islands facing the portion of the linear portion 161 around the linear portion 161 and the gate electrode 124 extending along the data line 171 together with the semiconductor layer 151. It consists of a mold 165. The island portion 165 is formed at a predetermined distance away from the linear portion 161, and they have the same planar pattern as the semiconductor layer 151 except for a predetermined region of the semiconductor layer 154. The predetermined region of the semiconductor layer 154 is a channel portion that forms a channel of the thin film transistor.

A data line 171 is formed on the gate insulating layer 140 and the ohmic contact layer 161 to cross the gate line 121 to define a pixel area. The data line 171 is branched and has a source electrode 173 overlapping the semiconductor layer 151. In this case, the data line 171 is formed such that a repeatedly curved portion and a vertically extending portion appear with a length of the pixel. In this case, the curved portion of the data line 171 is composed of two straight portions, one of the two straight portions forms 45 degrees with respect to the gate line 121, and the other portion with respect to the gate line 121. Achieve -45 degrees. The source electrode 173 is connected to a vertically extending portion of the data line 171, and the portion crosses the gate line 121 and the storage electrode line 131. Accordingly, the pixel region formed by the intersection of the gate line 121 and the data line 171 has a curved band shape.

One end 179 of the data line may be wider than the width of the data line 171 to receive a signal transmitted from a data driving circuit (not shown).

A drain electrode 175 is formed on the ohmic contact layer 165 facing the source electrode 173 at a predetermined distance from the gate electrode 124 and partially overlapping the semiconductor layer 151. In this case, the data line 171 is in contact with the linear portion 161 of the ohmic contact layer and the drain electrode 175 is in contact with the island portion 165.

In the data line 171, a portion of the data line 171 connected to the pixel electrode 190 overlaps the storage electrode line 131. A constant voltage is applied to the storage electrode line 131 to form a storage capacitor between the storage electrode line 131, the storage electrodes 133a and 133b, and the drain electrode 175.

The passivation layer 180 made of an inorganic insulating material such as silicon nitride is formed on the substrate 110 to cover the semiconductor layer 151 that is not covered by the data lines 171, 173, and 179 and the drain electrode 175. have.

The passivation layer 180 is provided with contact holes 183 exposing the drain electrode 175, contact holes 181 and 182 exposing one end portions of the gate line 121 and the data line 171, respectively.

The pixel electrode 190 is formed on the passivation layer 180 through a contact hole 183 and is connected to the drain electrode 175 and has a band shape that is bent along the shape of the pixel area. The pixel electrode 190 has a cutout 191 formed in the curved portion of the data line 171 to divide the pixel up and down. The pixel electrode 190 extends in the direction in which the data line 171 extends to overlap the storage electrode line 131 of the adjacent pixel row.

here. The passivation layer 180 may be formed of a low dielectric constant organic material having a dielectric constant of 4.0 or less. In this case, since the passivation layer 180 is thicker than that of the inorganic material, the passivation layer 180 may be formed between the pixel electrode 190 and the data line 171. Since the coupling phenomenon does not occur, the edge ratio of the pixel electrode 190 may be overlapped with the data line 171 to maximize the aperture ratio of the pixel, which will be described later in detail with reference to another embodiment.

In addition, contact auxiliary members 81 and 82 are formed on the passivation layer 180 and connected to one end portions 129 and 179 of the gate line 121 and the data line 171 through the urging 181 and 182. .

Here, the pixel electrode 190 and the contact auxiliary members 81 and 82 are made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the contact auxiliary members 81 and 82 are connected to the outside. It is intended to compensate for the adhesion, especially when mounted on the substrate 110 or a flexible circuit board (not shown) in the form of a chip. When the driving circuit is made of a thin film transistor or the like directly on the substrate 110, the contact hole 181 and the contact auxiliary member 181 are not required as shown in FIGS. 10 and 11.

An alignment layer 11 is formed on the pixel electrode 190.

Now, an upper display panel including a color filter will be described with reference to FIGS. 1 to 3 and 5.

A black matrix 220 is formed on the upper substrate 210 made of a transparent insulating material such as glass to prevent light leakage. The black matrix 220 is formed in a portion corresponding to the thin film transistor portion. Of course, the black matrix 220 may be formed not only in the thin film transistor but also in a portion corresponding to the data line 171 depending on the presence or absence of light leakage around the data line 171.

The red, green, and blue color filters 230R, 230G, and 230B are formed on the black matrix 220. The color filters 230R, 230G, and 230B are formed lengthwise along the pixel columns separated by the data lines 171 except for the data lines and the end portions 129 and 179 of the gate lines that are bonded to the external circuit. The color filters 230R, 230G, and 230B are periodically bent along the shape of the pixel, and the adjacent color filters 230R, 230G, and 230B overlap each other with the data line 171 to prevent light leakage around the data line 171.

An overcoat layer 250 made of an organic material is formed on the color filters 230R, 230G, and 230B. The overcoat layer 250 is to protect the common electrode 270 from the color filters 230R, 230B, and 230 and to planarize the substrate, and may not be formed as necessary.

On the overcoat layer 250, a common electrode 270 made of a transparent conductive material such as ITO or IZO and having domain dividing means 271 is formed. The domain dividing means 271, 272 of the common electrode 270 is formed of a cutout, and may be formed of a protrusion. The domain dividing means 271 and 272 are bent along the shape of the pixel and are connected to the first dividing portion 271 and the first dividing portion 271 for dividing the pixel area from side to side and bent portions of the data line 171. And a second division part 272 corresponding to the cutout 191 of the lower panel.

In this case, the first division part 271 extends to the portion where the pixel electrode 190 of the lower display panel extends over the gate line 121 to be formed on the adjacent storage electrode line 131.

When the domain dividing means 271 and 272 are used as protrusions, a thin film made of an insulating material on the common electrode 270 and having a tapered structure having an inclination angle is used.

An alignment layer 21 is formed on the common electrode 270 including the domain dividing means 271 and 272.

When the liquid crystal layer is formed by combining the thin film transistor array panel and the color filter display panel having the above structure and injecting liquid crystal therebetween, the liquid crystal display according to the first embodiment of the present invention is formed. At this time, the pixel electrode 190 is aligned to exactly overlap the color filters 230R, 230G, and 230B.

The liquid crystal molecules included in the liquid crystal layer 3 are aligned such that their directors are perpendicular to the display panel without an electric field applied between the pixel electrode 190 and the common electrode 270.

In this way, the plurality of domains is divided by the domain dividing means 271 and 272 of the upper panel 200 and the cutout 191 of the lower panel 100. In this case, the pixel area is divided into left and right sides by the first dividing unit 271, but is divided into four domains because the alignment directions of the liquid crystals are different from each other in the vertical direction with respect to the bent portion of the pixel.

The liquid crystal display is formed by disposing elements such as a polarizing plate (not shown), a backlight (not shown), and a compensation plate (not shown) on both sides of the basic display panel. In this case, one polarizer is disposed on each side of the base panel, and the transmission axis thereof is arranged to be parallel to or perpendicular to the gate line 121.

When the liquid crystal display device is formed as described above, when an electric field is applied to the liquid crystal, the liquid crystal in each domain is inclined in a direction perpendicular to the long side of the domain. However, since the direction is perpendicular to the data line 171, the direction coincides with the direction in which the liquid crystal is inclined by the lateral electric field formed between two adjacent pixel electrodes 190 with the data line 171 therebetween. As a result, the lateral electric field assists the liquid crystal alignment of each domain.

At this time, in the bent portion of the data line 171 where the domain is changed, a fringe field is formed at the boundary between the cutout 191 and the second dividing portion 272 to easily determine the alignment of the liquid crystal located in the portion. This can prevent textures from occurring. In addition, since the pixel electrode 190 extends to the neighboring storage electrode line 131 and the first division part 271 of the upper panel also extends to the portion where the pixel electrode 190 is extended, the pixel electrode 190 It is also possible to form a domain even at the edge of the) to prevent the texture from occurring.

A method of manufacturing a thin film transistor array panel having such a structure will be described.

6A, 7A, and 8A are layout views in an intermediate step of manufacturing a thin film transistor array panel according to a first exemplary embodiment of the present invention, and FIGS. 6B and 6C are VIb-VIb 'and VIc-Vic' of FIG. 6A, respectively. 7B and 7C are cross-sectional views taken in the next step of FIGS. 6B and 6C, and FIGS. 8B and 8C are cross-sectional views taken in the next step of FIGS. 7B and 7C, and FIGS. 9B and 7C. 9C is a cross sectional view at the next step in FIGS. 8B and 8C.

First, as shown in FIGS. 6A to 6B, Cr, Mo, Al, Ag, or alloys thereof are deposited by a method such as sputtering to form a gate metal film, and the gate metal film is dried by a photolithography process using a mask. Alternatively, wet etching may be performed to form the gate lines 121, 124, and 129 and the storage electrode line 131.

In this case, the metal film may be formed in a plurality of layers in order to reduce the resistance of the wiring, and end surfaces of the gate lines 121, 124, and 129 and the storage electrode line 131 may be tapered to increase adhesion to the upper layer.

Next, as shown in FIGS. 7A to 7B, the gate insulating layer 140, the hydrogenated amorphous silicon film, and the amorphous silicon film doped with a high concentration of n-type impurities such as phosphorus (P) are continuously deposited by chemical vapor deposition. In addition, the doped amorphous silicon film and the amorphous silicon film are patterned in a photolithography process using a mask to form the ohmic contact layers 160 and the semiconductor layers 151 and 154 to which the channel parts are connected.

Thereafter, as shown in FIGS. 8A to 8C, Cr, Mo, Al, Ag, or alloys thereof are deposited by a sputtering method to form a data metal film, and the data metal film is dried or dried by a photolithography process using a mask. The wet etching process forms the data lines 171 and 173 and the drain electrode 175.

In this case, the metal film may be formed in a plurality of layers in order to reduce the resistance of the wiring, and end faces of the data line 171 and the drain electrode 175 may be tapered to increase adhesion to the upper layer.

Subsequently, the ohmic contact layer 160 that is not covered by the source electrode 173 and the drain electrode 175 is etched to expose the semiconductor layer 154 between the source electrode 173 and the drain electrode 175, and separated from each other. The ohmic contacts 163 and 165 are formed.

Subsequently, as shown in FIGS. 9A to 9C, the passivation layer 180 is formed of an inorganic material such as silicon nitride and then etched by a photolithography process through a mask to form contact holes 181, 182, and 183. .

Next, as shown in FIGS. 2 to 4, a transparent conductive layer such as indium tin oxide (ITO) or indium zinc oxide (IZO) is formed on the entire surface of the substrate 110, and then patterned by a photolithography process to form a pixel electrode ( 190, contact auxiliary members 81 and 82 are formed. The pixel electrode 190 is formed at regular intervals to prevent a coupling phenomenon between the data line 171 and the pixel electrode 190. Preferably, the edge of the pixel electrode 190 is positioned on the sustain electrodes 133a and 133b.

Second Embodiment

FIG. 10 is a layout view of a thin film transistor array panel according to another exemplary embodiment, and FIG. 11 is a cross-sectional view taken along the line XI-XI ′ of FIG. 10.

10 and 11, in the second embodiment, unlike the first embodiment, the passivation layer 180 is formed of an organic material having a low dielectric constant of 4.0 or less. Except for the passivation layer 180, it has the same single-layer structure as in the first embodiment.

In the case of an organic material, the passivation layer 180 may be formed thick to prevent coupling between the data line 171 and the pixel electrode 190. Therefore, the pixel electrode 190 formed later may be formed using the data line 171. It can be enlarged to the upper portion to maximize the aperture ratio of the pixel region.

Here, the gate driving circuit (not shown) is formed together with the thin film transistor of the display area, so that a contact hole and a contact auxiliary member exposing one end portion of the gate line 1210 are not formed.

Except for the parts described above, they are formed in the same structure as the first embodiment.

Third Embodiment

12 is a layout view of a thin film transistor array panel according to a third exemplary embodiment of the present invention, FIG. 13 is a cross-sectional view taken along line XIII-XIII 'of FIG. 12, and FIG. 14 is taken along line XIV-XIV ′ of FIG. 12. It is a cut section.

The single layer structure of the thin film transistor array panel according to the third embodiment is the same as that of FIGS. 1 and 2. That is, the gate line 121 is formed on the insulating substrate 110, the gate insulating layer 140 is formed to cover the gate line 121, and the semiconductor layer 151 and the ohmic contact are formed on the gate insulating layer 140. The layers 161 and 165 are formed, and the data line 171 and the drain electrode 175 are formed on the ohmic contact layers 161 and 165, and the passivation layer 180 covers the 171 and 175. The pixel electrode 190 connected to the drain electrode 175 is formed on the passivation layer 180.

However, unlike the first and second embodiments, in the third embodiment, the contact layers 161 and 165 are formed under the data lines 171, 173 and 179 and the drain electrode 175 in substantially the same pattern. The semiconductor layer 151 also has substantially the same pattern as the data lines 171, 173, and 179 and the drain electrode 175 except that the channel portion between the source electrode 173 and the drain electrode 175 is connected. The third embodiment can form a thin film transistor array panel using fewer masks than the first embodiment.

Next, a method of manufacturing a thin film transistor array panel having such a structure and method features will be described.

15A, 18A, and 19A are layout views in an intermediate step of manufacturing a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIGS. 15B and 15C are XIIIb-XIIIb 'of FIG. 15A, respectively. 16A and 16B are cross-sectional views taken along the line XIIIc-XIIIc ', and FIGS. 16A and 16B are cross-sectional views taken in the next step of FIGS. 15B and 13C, and FIGS. 17A and 17B are cross-sectional views taken in the next step in FIGS. 18A and 18B are sectional views at the next stage of FIGS. 17A and 17B, and FIGS. 19A and 19B are sectional views at the next stage of FIGS. 18A and 18B.

First, as shown in FIGS. 15A and 15B, a metal such as chromium, molybdenum, aluminum, silver, or an alloy thereof is deposited on the transparent insulating substrate 110 by sputtering to form a single layer or a plurality of gate metal layers. do. Thereafter, the metal film is dry or wet etched by a photolithography process to form gate lines 121, 124, and 129, storage electrode lines 131, and storage electrodes 133a and 133b on the substrate 110. In wet etching, the sidewalls of these 121, 124, 129, 131, 133a, and 133b are tapered, and the tapered shape allows the layers formed thereon to closely adhere to each other.

16A to 16C, an insulating material such as silicon nitride is deposited to cover the gate lines 121, 124, and 129, the storage electrode lines 131, and the storage electrode lines 133a and 133b. 140 is formed.

The amorphous silicon film 150 doped with impurities and the amorphous silicon film 160 doped with impurities are sequentially stacked by depositing amorphous silicon without impurities and amorphous silicon doped with impurities on the gate insulating layer 140. do. The amorphous silicon film 150 not doped with impurities is formed of hydrogenated amorphous silicon, and the like, and the amorphous silicon film 160 doped with impurities is heavily doped with an n-type impurity such as phosphorus (P). It is formed of silicon or silicide.

After depositing a metal such as aluminum, silver, chromium, molybdenum or an alloy thereof by sputtering on the amorphous silicon film 160 doped with impurities in succession to form a single layer or a plurality of metal films 170, A photosensitive material is coated on the metal layer 170 to form a photoresist film, and then exposed and developed to form photoresist patterns 52 and 54 having different thicknesses.

As described above, there may be various methods of varying the thickness of the photoresist film according to the position, and the transparent mask and the light blocking area as well as the translucent area may be provided in the exposure mask. Yes. The translucent region is provided with a slit pattern, a lattice pattern, or a thin film having a medium transmittance or a medium thickness. When using the slit pattern, it is preferable that the width of the slits and the interval between the slits are smaller than the resolution of the exposure machine used for the photographic process. Another example is to use a photoresist film that can be reflowed. That is, a thin portion is formed by forming a reflowable photoresist pattern with a normal mask having only a transparent region and a light shielding region and then reflowing so that the photoresist film flows into an area where no photoresist remains.

Given the appropriate process conditions, the underlying layers may be selectively etched due to the difference in thickness of the photoresist patterns 52 and 54. Therefore, a plurality of data lines 171 and a plurality of drain electrodes 175 each including a plurality of source electrodes 173 as shown in FIG. 9 are formed through a series of etching steps, and a plurality of protrusions 163 are formed. A plurality of linear semiconductor contacts 161 including a plurality of linear ohmic contact members 161, a plurality of island type ohmic contact members 165, and a plurality of protrusions 154 are formed.

For convenience of description, a portion of the conductor layer 170 positioned at the portion where the wiring is to be formed, the amorphous silicon layer 160 doped with impurities, and the amorphous silicon layer 150 without doping impurities are referred to as the wiring portion A. The portion of the conductor layer 170, the impurity doped amorphous silicon layer 160 and the impurity doped amorphous silicon layer 150 located at the portion where the channel is formed is called a channel portion B, and the channel and wiring portions A portion of the conductor layer 170, the amorphous silicon layer 160 doped with impurities, and the amorphous silicon layer 150 not doped with impurities is located in the other region (C).

One example of the order of forming such a structure is as follows.

First, (1) removing the conductor layer 170, the impurity amorphous silicon layer 160 and the amorphous silicon layer 150 located in the other portion (C), (2) removing the photoresist film 54 located in the channel portion (B). , (3) removing the conductor layer 170 and the impurity amorphous silicon layer 160 located in the channel portion B, and (4) removing the photosensitive film 52 located in the wiring portion A.

Other methods include (1) removing the conductor layer 170 located in the other portion (C), (2) removing the photosensitive film 54 located in the channel portion (B), and (3) impurity amorphous in the other portion (C). Removal of the silicon layer 160 and the amorphous silicon layer 150, (4) removal of the conductor layer located in the channel portion B, (5) removal of the photosensitive film 52 located in the wiring region A, and (6) channel portion. It may also proceed in order to remove the impurity amorphous silicon layer 160 located in (B).

This section describes the first example.

Next, as shown in FIGS. 17A and 17B, the conductive layer 170 exposed to the other region C is removed by wet etching or dry etching, and the other portion of the amorphous silicon layer 160 doped with impurities underneath it. Expose (C).

The data line 171 and the drain electrode 175 are still attached. In the case of using dry etching, the upper portions of the photoresist films 52 and 54 may be cut to a certain thickness.

Subsequently, the amorphous silicon layer 160 doped with impurities in the other portion C and the amorphous silicon layer 150 not doped with impurities below are removed, and the photoresist film 54 of the channel portion B is removed. It removes to expose the lower conductor 170.

Removal of the photoresist of the channel portion B may be performed simultaneously with or separately from the removal of the amorphous silicon layer 160 doped with impurities in the other region C and the amorphous silicon layer 150 without the impurities. Residue of the photoresist film 54 remaining in the channel region B is removed by ashing. In this step, the semiconductor layer 151 is completed.

Here, when the conductor layer 170 is a material that can be dry etched, the manufacturing process may be performed by continuously dry etching the amorphous silicon layer 160 doped with impurities below and the amorphous silicon layer 150 doped with impurities. In this case, it may or may not be performed in an in-situ manner in which dry etching is sequentially performed on the three layers 170, 160, and 150 in the same etching chamber.

Next, as shown in FIGS. 16A, 18A, and 18B, the conductor 170 located in the channel portion B and the amorphous silicon layer 160 doped with impurities are etched and removed. In addition, the photosensitive film 52 of the remaining wiring portion A is also removed.

In this case, the upper portion of the amorphous silicon layer which is not doped with impurities in the channel portion B may be partially removed to reduce the thickness, and the photoresist layer 52 of the wiring portion A may be etched to some extent.

In this way, each of the conductors 174 is completed while being separated into one data line 171 and a plurality of drain electrodes 175, and the amorphous silicon layer 160 doped with impurities also includes the linear ohmic contact layer 161. Completed by dividing into island resistive contact layer 165

The data lines 171, 173, 179 and the drain electrode 175 may also be formed in a tapered shape like the gate lines 121, 124, and 129 to increase adhesion to the upper layer.

Next, as shown in FIGS. 20A to 20C, the passivation layer 180 is formed on the substrate 110 using an inorganic material such as silicon nitride. Then, contact holes 181, 182, and 183 are formed in the passivation layer 180 by a photolithography process using a mask.

12 to 14, a transparent conductive material such as ITO or IZO is deposited on the passivation layer 180, and is etched by a photolithography process using a mask to drain the electrode 175 through the contact hole 183. Contact auxiliary members 81 and 82 connected to one end portions 129 and 179 of the gate line and the data line, respectively, through the pixel electrode 190 and the contact holes 181 and 182 connected to each other. In this case, an edge of the pixel electrode 190 is positioned on the sustain electrodes 133a and 133b.

When the passivation layer 180 is formed of an organic material, the pixel electrode 190 overlaps the data line 171 to increase the aperture ratio of the pixel.

Fourth Embodiment

21 and 22 are cross-sectional views of a liquid crystal display according to a fourth exemplary embodiment of the present invention. FIG. 21 is a cross-sectional view taken along the line II-II 'of the first embodiment, and FIG. It is sectional drawing cut in the same position.

As shown, unlike the first to third embodiments, red, green, and blue color filters 230R, 230G, and 230B are formed on the lower panel 100 together with the thin film transistors.

The boundary lines of the color filters 230R, 230G, and 230B are formed to be positioned above the data line 171, and the boundary lines of neighboring color filters 230R, 230G, and 230B are formed to overlap. As such, when the color filters 230R, 230G, and 230B are formed to overlap each other, light leakage around the data line 171 can be sufficiently prevented even if the black matrix 220 is not formed at the portion corresponding to the data line 171. .

As described above, the color filter is formed on the lower panel, so that only the black matrix 220 and the common electrode 270 are formed on the insulating substrate 210 on the upper panel 200.

Except for the color filters 230R, 230B, and 230G described above, they are formed in the same structure as in the first embodiment. Of course, it can be formed to have the same structure as the second embodiment.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, the pixel electrode is formed to overlap the neighboring storage electrode line to prevent light leakage and texture around the gate line. In addition, when forming a data line having a bent portion, a cutout that divides the pixel up and down in the bent portion may be formed in the pixel electrode to completely prevent texture.

Claims (13)

Insulation board, A gate line formed on the insulating substrate and having a gate electrode, A gate insulating film formed on the gate line, A semiconductor layer formed on the gate insulating film, A source electrode overlapping at least a portion of the semiconductor layer; A data line connected to the source electrode and having a bent portion and a portion crossing the gate line; A drain electrode facing the source electrode with respect to the gate electrode and at least partially overlapping the semiconductor layer; A protective film covering the semiconductor layer, A pixel electrode connected to the drain electrode and having a bent shape along a curved portion of the data line in a pixel region partitioned by the gate line and the data line and having a cutout that divides the pixel region up and down; Thin film transistor array panel comprising a. In claim 1, A storage electrode line extending in a direction parallel to the gate line; And a first and second storage electrodes connected to the storage electrode lines and formed in the pixel area and parallel to the curved portions of the data lines. In claim 2, And the pixel electrode extends in the data line direction and at least partially overlaps the storage electrode line disposed in a neighboring pixel region. In claim 3, A portion of the storage electrode line overlaps the drain electrode, and is formed to be larger than the width of the storage electrode line. The method of claim 1 or 2, And a resistive contact layer formed on the semiconductor layer and having the same planar pattern as the semiconductor layer except for a channel between the source electrode and the drain electrode. In claim 5, And the data line and the drain electrode have the same planar pattern as the ohmic contact layer. First insulating substrate, A gate line and a data line insulated from and intersecting the first insulating substrate to define a pixel area; A thin film transistor electrically connected to the gate line and the data line, An upper panel connected to the thin film transistor and having a first cutout formed in a direction in which the gate line extends to divide the pixel region up and down; A second insulating substrate facing the first insulating substrate, A red, green, and blue color filter formed on the first or second insulating substrate and extending along a column of pixels separated by the data lines; A lower panel formed on the color filter and having a common electrode extending along a shape of the data line and having a first division part dividing the pixel from side to side; A liquid crystal filled between the upper panel and the lower panel; And the data line has a portion intersecting the gate line and a curved portion. In claim 7, The common electrode further includes a second divider formed in a direction parallel to the gate line and connected to the first divider. In claim 8, The second division part overlaps with the first cutout part. In claim 7 or 8, A storage electrode line extending in a direction parallel to the gate line; And first and second storage electrodes connected to the storage electrode lines and formed in the pixel area and parallel to the curved portions of the data lines. In claim 10, And the pixel electrode extends in a direction in which the data line extends so that at least a portion of the pixel electrode overlaps the neighboring storage electrode line. In claim 11, And the first dividing portion extends to the neighboring storage electrode line. In claim 7 or 8, The first and second division parts may be one of protrusions formed in a shape protruding from the common electrode, or one of cutouts in which a part of the common electrode is removed.