KR101054337B1 - Thin Film Transistor Display Panels for Display Devices - Google Patents

Abstract

A gate line including a gate electrode is formed on the insulating substrate. An ohmic contact layer of a doped amorphous silicon is formed on the gate insulating layer covering the gate insulating layer. A source electrode in contact with the data line and the ohmic contact layer insulated from and intersecting the gate line is formed on the gate insulating film, and a drain electrode facing the source electrode is formed. The pixel electrode which is connected to the drain electrode through the contact hole is formed in the upper part of the protective film which covers these. At this time, the gate line and the data line cross each other to form a pixel area. In particular, thin film transistors including a gate electrode, a semiconductor layer, an ohmic contact layer, a source electrode, a drain electrode, and the like are formed by alternately changing their positions according to pixel rows, and the data lines are positioned to the left and right with respect to the pixel electrode. Let's do it.

LCD, parasitic capacitance, pixel electrode, data line

Description

Thin film transistor array panel for display device {THIN FILM TRANSISTOR ARRAY PANEL FOR DISPLAY DEVICE}

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to a first exemplary embodiment of the present invention.

2 and 3 are cross-sectional views taken along line II-II 'and III-III' of the TFT panel for the liquid crystal display according to the first exemplary embodiment of the present invention.

4 is a layout view of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view of the thin film transistor array panel of FIG. 4 taken along the line VV ′.

6 is a layout view of a thin film transistor array panel for a liquid crystal display according to a third exemplary embodiment of the present invention.

FIG. 7 is a cross-sectional view of the thin film transistor array panel of FIG. 6 taken along the line VII-VII ′. FIG.

Explanation of symbols on the main parts of the drawings

121 gate line, 123 gate electrode,

131 sustain electrode,                 

151, 154 amorphous silicon layer,

171 data lines, 173 source electrodes,

175 drain electrodes, 190 pixel electrodes,

240 protuberances, 270 reference electrodes

The present invention relates to a thin film transistor array panel for a liquid crystal display device.

In general, a liquid crystal display device injects a liquid crystal material between an upper display panel on which a common electrode and a color filter are formed, and a lower display panel on which a thin film transistor and a pixel electrode are formed. By applying a different voltage to form an electric field to change the arrangement of the liquid crystal molecules, and through this to adjust the transmittance of light to represent the image.

In the method of manufacturing a display panel for a liquid crystal display device, a pattern such as a wiring or a contact hole is formed by patterning by a photolithography process using a mask, and a plurality of display panels for display devices are made on a single mother glass. After the pattern is completed through an etching process, the mother substrate is separated into display panels.

In the photolithography process, when the active area in which the pattern is formed on the mother substrate is larger than the mask size, a step and repeat process is performed by dividing the active area to form a pattern in the active area. Split exposure is required. in this case Distortions such as shifts, rotations, and distortions of the mask cause distortions in the exposed areas, resulting in differences in parasitic capacitance between the wires and the pixel electrodes between the exposed areas. Or there is a difference in the pattern position. On the other hand, in the photolithography process, when the positions are not aligned correctly between the stacked layers, the parasitic capacitance difference between the electrodes is caused. This difference in parasitic capacitance and pattern position leads to differences in electrical properties and aperture ratios in each area, and results in a difference in screen brightness at the boundary between exposure areas, resulting in poor horizontal or vertical streaks or flicker. It causes poor visibility.

An object of the present invention is to provide a thin film transistor array panel for a display device capable of minimizing visibility defects such as vertical streaks or flicker.

In order to solve this problem, in the present invention, the thin film transistors are formed in different positions according to the pixel rows, and the signal lines are positioned to the left and right by dividing the pixel lines.

More specifically, in the thin film transistor array panel according to the exemplary embodiment of the present invention, a first signal line is formed on an insulating substrate, and a second signal line is formed to insulate and cross the first signal line to define a pixel. A pixel electrode is formed for each pixel, and a thin film transistor having three terminals electrically connected to each of the first signal line, the second signal line, and the pixel electrode is formed. In this case, the thin film transistors of each pixel row are formed to be different from each other in the positions of the thin film transistors adjacent to the pixel rows up and down, and the second signal line is positioned to the left and right with respect to the pixel electrode.

In addition, the pixel electrode may have protrusions or cutouts that divide the pixel into at least two or more.

In the thin film transistor array panel according to another exemplary embodiment, a gate line including a gate electrode is formed on an insulating substrate, and a gate insulating layer is formed on the gate line. The semiconductor layer and the ohmic contact layer are formed on the gate insulating film. A data line defining a pixel is formed on the gate insulating layer to intersect the gate line, at least a portion of which is formed on the ohmic contact layer, and at least a portion of which is formed on the ohmic contact layer, and a drain electrode facing the source electrode. Formed. The pixel electrode is formed on the passivation film covering the semiconductor layer.

In this case, thin film transistors including a gate electrode, a semiconductor layer, an ohmic contact layer, a source electrode, and a drain electrode are formed in each pixel area, and the thin film transistors of each pixel row are left and right opposite to the thin film transistors of the adjacent pixel row. The data lines are formed by changing their positions, and the data lines are positioned by dividing them left and right with respect to the pixel electrode. The semiconductor layer below the data line preferably has the same planar shape as the data line. The pixel electrode may have protrusions or cutouts that divide the pixel into at least two or more.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Next, a structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a layout view illustrating a structure of a thin film transistor array panel according to a first exemplary embodiment of the present invention, FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along line II-II ′, and FIG. 1 is a cross-sectional view taken along the line III-III 'of the TFT panel.

The gate line 121 transmitting the gate signal on the insulating substrate 110 mainly extends in the horizontal direction. In addition, another portion of each gate line may protrude downward and have a plurality of expansions.

The gate line 121 preferably includes two or more films having different physical properties. One conductive film has a low resistivity metal such as aluminum (Al) or aluminum alloy, copper (Cu) or copper alloy, silver (Ag) or silver alloy to reduce the delay or voltage drop of the gate signal. It is composed of metals, and other conductive films have excellent physical, chemical and electrical contact properties with other materials, especially indium zinc oxide (IZO) or indium tin oxide (ITO), such as molybdenum (Mo) and molybdenum alloys. Molybdenum-tungsten (MoW) alloy], chromium (Cr) and the like. Examples of the combination include chromium / aluminum-neodymium (Nd) alloys and aluminum / molybdenum, aluminum-neodymium (Nd) alloys / molybdenum, and the like. Sides of the gate lines 121 are inclined, respectively, and the inclination angle is about 20-80 ° with respect to the surface of the substrate 110.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate line 121.

A plurality of linear semiconductors 151 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) and the like are formed on the gate insulating layer 140. The linear semiconductor 151 mainly extends in the longitudinal direction, from which a plurality of extensions 154 extend toward the gate electrode 123. In addition, the linear semiconductor 151 is formed along the data line 171 to be formed later. The linear semiconductor 151 increases in width near the point where it meets the gate line 121 to cover a large area of the gate line 121.

On the semiconductor 151, a plurality of linear and island ohmic contacts 161 and 165 made of a material such as n + hydrogenated amorphous silicon doped with high concentration of silicide or n-type impurities are formed. It is. The linear contact member 161 has a plurality of protrusions 163, and the protrusions 163 and the island contact members 165 are paired and positioned on the protrusions 154 of the semiconductor 151.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the ohmic contacts 161 and 165 and the gate insulating layer 140, respectively.

The data line 171 extends in a vertical direction in a zigzag form with respect to the pixel electrode 190 to be described later. The data line 171 crosses the gate line 121 and transmits a data voltage. . A plurality of branches extending from the data line 171 toward the drain electrode 175 forms a source electrode 173. The pair of source electrode 173 and the drain electrode 175 are separated from each other and positioned opposite to the gate electrode 124. The gate electrode 123, the source electrode 173, and the drain electrode 175 form a thin film transistor (TFT) together with the protrusion 154 of the semiconductor 151, and the channel of the thin film transistor is a source. A protrusion 154 is formed between the electrode 173 and the drain electrode 175. At this time, the data line 171 passes through the pixel electrode 190 to be described later through the bends 176 and 177, and the thin film transistors of each pixel row are positioned upside down from the thin film transistors of neighboring pixel rows. Is formed.

The data line 171 and the drain electrode 175 also preferably include a conductive film such as molybdenum (Mo), molybdenum alloy, chromium (Cr), and an aluminum-based metal disposed thereon.

Like the gate line 121, the data line 171 and the drain electrode 175 are also inclined at an angle of about 30-80 °.

The ohmic contacts 161 and 165 exist only between the semiconductor 151 below and the data line 171 and the drain electrode 175 above and serve to lower the contact resistance. The linear semiconductor 151 has an exposed portion between the source electrode 173 and the drain electrode 175 and is not covered by the data line 171 and the drain electrode 175, and in most places, the linear semiconductor 151 is provided. Although the width of is smaller than the width of the data line 171, as described above, the width becomes larger at the portion that meets the gate line 121 to strengthen the insulation between the gate line 121 and the data line 171. On the data line 171, the drain electrode 175, and the exposed portion of the semiconductor 151, an organic material having excellent planarization characteristics and photosensitivity or plasma enhanced chemical vapor deposition (PECVD) is formed. A passivation layer 180 made of a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or the like is formed. In particular, the passivation layer 180 made of an organic material has a dielectric constant (ĸ) of 2.5 to 3.5, and may be deposited to a thickness of about 2 μm, and the passivation layer 180 which may be formed of a nitride film (SiNx) has a dielectric constant (ĸ). Is 6-7 and can be deposited to a thickness of about 0.45um. In addition, the passivation layer 180 may be formed of SiNx or It may be made of a combination of a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or an organic film.

In an embodiment in which the passivation layer 180 is made of an organic material, the passivation layer 180 may be formed to prevent the organic material of the passivation layer 180 from coming into contact with the portion of the semiconductor 151 exposed between the data line 171 and the drain electrode 175. An insulating film made of silicon nitride or silicon oxide may be added to the lower portion of the silver organic film.

In the passivation layer 180, a plurality of contact holes 185 and 182 exposing the drain electrode 175, the end portion 129 of the gate line 121, and the end portion 179 of the data line 171 are formed. It is. As described above, in the embodiment in which the passivation layer 180 has contact holes 181 and 182 exposing the gate lines 121 and the end portions 129 and 179 of the data line 171, an external data driving circuit may be formed using an anisotropic conductive film. The data line 171 has a contact portion for connecting to the gate line 121 and the data line 171, respectively, and the end portions 129 and 179 of the gate line 121 and the data line 171 are required as necessary. It may have a wider width than the gate line 121 and the data line 171. In another embodiment, the gate line 121 and the data line 171 may not have a contact portion at an end portion thereof. The structure further includes a structure in which end portions 129 and 179 of the gate line 121 and the data line 171 are directly connected to an output terminal of the gate driving circuit or the data driving circuit formed directly on the substrate.

The contact holes 185, 181, and 182 expose the drain electrode 175, the end portion 129 of the gate line 121, and the end portion 179 of the data line 171. The contact holes 185, 181, In 182, it is preferable that the aluminum-based conductive film is not exposed in order to secure contact characteristics with the conductive film of ITO or IZO formed later. In this case, the contact holes 185, 181, and 182 may expose boundary lines between the drain electrode 175, the end portion 129 of the gate line 121, and the end portion 179 of the data line 171.

A plurality of pixel electrodes 190 and a plurality of contact assistants 81 and 82 made of IZO or ITO are formed on the passivation layer 180.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 through the contact hole 185 to receive a data voltage from the drain electrode 175.

The pixel electrode 190 to which the data voltage is applied rearranges the liquid crystal molecules of the liquid crystal layer by generating an electric field together with a common electrode (not shown) of another display panel (not shown) to which a common voltage is applied. .

In particular, a thin film transistor including the gate electrode 123, the semiconductor layer 151, the ohmic contact layer 161, the source electrode 173, the drain electrode 175, and the like is formed by alternately changing positions of the thin film transistors along the pixel rows. The data line 171 is divided into left and right positions with respect to the pixel electrode 190.

In the structure according to the exemplary embodiment of the present invention, when the exposure process is performed in a step-and-repeat manner by dividing the active region in which the thin film pattern is formed in the manufacturing process into a plurality of regions, even if misalignment of the mask occurs, The parasitic capacitance generated between the pixel electrode 190 and the data line 171 is almost constant. Therefore, it is possible to minimize the difference in the screen brightness at the boundary between the exposure areas, it is possible to prevent poor visibility, such as vertical streak or flicker.

 In the manufacturing process, the parasitic capacitance generated between the gate electrode 123 and the source / drain electrodes 173 and 175 is almost constant. Therefore, it is possible to prevent visibility defects in which a horizontal line defect or the like occurs.

As described above, the pixel electrode 190 and the common electrode form a capacitor (hereinafter referred to as a "liquid crystal capacitor") to maintain the applied voltage even after the thin film transistor is turned off, thereby enhancing the voltage holding capability. Another capacitor is connected in parallel with the liquid crystal capacitor, which is referred to as a "storage electrode." The contact auxiliary members 81 and 82 are connected to the respective ends 129 and 179 of the gate line and the data line through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 are essential for complementing and protecting the adhesion between the respective ends 179 of the gate line 121 and the data line 171 and an external device such as a driving integrated circuit. It is not intended that they be applied.

Meanwhile, in another embodiment of the present invention, unlike the thin film transistor array panel illustrated in FIGS. 1 to 3 to reduce the manufacturing cost, The semiconductor 151 may have substantially the same planar shape as the data line 171, the drain electrode 175, and the ohmic contact 161, 165, and the lower portion except for the protrusion 154 in which the thin film transistor is located. The linear semiconductor 151 may include the source electrode 173 and the drain electrode 175 in addition to the portions of the data line 171 and the drain electrode 175 and the ohmic contacts 161 and 165 below the linear semiconductor 151. It may have an exposed portion between them.

In addition, the gate line 121 may not have a contact portion for connecting with the driving circuit. The same applies to the thin film transistor array panel in which two or more thin films are patterned by using a photosensitive film pattern including a portion having an intermediate thickness.

In another embodiment of the present invention, a transparent conductive polymer may be used as the material of the pixel electrode 190, and in the case of a reflective liquid crystal display, an opaque reflective metal may be used. In this case, the contact assistants 81 and 82 may be made of a material different from the pixel electrode 190, in particular, IZO or ITO.

4 is a layout view of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 4 taken along a line V-V ′.

4 and 5, a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention is a thin film transistor substrate for a color filter on array (COA) liquid crystal display in which a color filter is formed on the thin film transistor array. The same applies to the structure. The layered structure of the thin film transistor array panel for a liquid crystal display device according to the present embodiment is generally similar to the layered structure of the thin film transistor array panel for liquid crystal display devices shown in FIGS. 1 to 3.

That is, the plurality of gate lines 121 including the plurality of gate electrodes 123 are formed on the substrate 110, and the gate insulating layer 140, the plurality of linear semiconductors 151, and the plurality of linear ohmic contacts are formed thereon. The member 161 and the plurality of island resistive contact members 165 are sequentially formed. A plurality of source electrodes 173 and drain electrodes 175 are formed on the ohmic contacts 161 and 165 and the gate insulating layer 140. A plurality of data lines 171 having curved portions 176 and 177 and extending in the zigzag shape and passing through the pixel electrode 190 are formed. The thin film transistors including the gate electrode 123, the semiconductor layer 151, the ohmic contact layer 161, the source electrode 173, the drain electrode 175, and the like are formed by alternately shifting their positions along the pixel rows. have. In particular, in order to protect the channel layer of the thin film transistor, a passivation layer including a nitride film (SiNx) may be formed on the source electrode 173 and the drain electrode 175.

Here, unlike FIGS. 1 to 3 Red, green, and blue (R, G, B) color filters having a contact hole 185 exposing the drain electrode 175 are formed in the vertical direction. In addition, although the boundaries of the color filters of red, green, and blue (R, G, and B) are shown to correspond to the pixel areas, they overlap the top of the data line 171 to block light leakage between the pixel areas. It is possible to have it, and not formed at the end portions 129 and 179 of the gate line and the data line, respectively.

The protective layer 802 on the color filter of blue, green, and blue (R, G, B) has a contact hole for lifting the end portion 129 of the gate line and the end portion 179 of the data line together with the gate insulating layer 140. 181,182). In addition, a plurality of pixel electrodes 190 and a plurality of contact assistants 81 and 82 are formed on the passivation layer 802. In particular, the protective film 802 is composed of an organic material, the dielectric constant (ĸ) is 3.2 ~ 3.4 and the thickness is preferably 1.5um or less, in some cases, the protective film 802 may not be formed.

In addition, a black matrix 220 made of an organic material may be formed on the thin film transistor array panel.

In addition, the gate line 121 may not have a contact portion for connecting with the driving circuit.

In another embodiment of the present invention, unlike the thin film transistor array panel shown in FIGS. 4 to 5 to reduce the manufacturing cost, The semiconductor 151 has a planar shape substantially the same as that of the data line 171, the drain electrode 175, and the ohmic contacts 161 and 165, except for the protrusion 154 where the thin film transistor is located. . In detail, the linear semiconductor 151 may include the source electrode 173 and the drain electrode 175 in addition to the data line 171, the drain electrode 175, and the portions below the ohmic contacts 161 and 165. ) Has an exposed portion between them.

In addition, the gate line 121 may not have a contact portion for connecting with the driving circuit.

On the other hand, the pixel electrode may have a domain regulating means for the partial alignment of the liquid crystal molecules, this structure will be described in detail.

6 is a layout view of a thin film transistor substrate for a liquid crystal display according to a third exemplary embodiment of the present invention, and FIG. 7 is a cross-sectional view of the liquid crystal display of FIG. 6 taken along the line VII-VII ′.

In the liquid crystal display according to the third exemplary embodiment of the present invention, the thin film transistor array panel 100, the common electrode panel 200 facing each other, and the long axis of the liquid crystal molecules included between the two display panels are included in the display panel. It consists of a liquid crystal layer 300 oriented perpendicular to the.

First, a thin film transistor array panel according to a third exemplary embodiment of the present invention will be described in more detail with reference to FIGS. 6 and 7.

The gate line 121 is formed in the horizontal direction on the insulating substrate 110, and the gate electrode 123 is connected to the gate line 121. One end portion 129 of the gate line 121 is formed for connection with an external circuit. The storage electrode line 131 and the storage electrode 133 are formed on the insulating substrate 110. The storage electrode line 131 extends in the horizontal direction and the storage electrode 133 is connected to the storage electrode line 131 in a rhombic or rectangular shape, and is disposed adjacent to the gate electrode 123.

The gate line 121 and the storage electrode line 131 may be formed of a double layer of a first layer made of Cr or Mo alloy having excellent physical and chemical properties, and a second layer made of Al or Ag having low resistance or an alloy thereof. If necessary, it may consist of a single layer or triple layer or more.

A gate insulating layer 140 is formed on the gate line 121 and the storage electrode line 131, and a semiconductor layer 150 made of a semiconductor such as amorphous silicon is formed thereon. The semiconductor layer 150 includes a channel portion forming a channel of the thin film transistor, and the semiconductor layer 150 is made of a material such as n + hydrogenated amorphous silicon in which silicide or n-type impurities are heavily doped. An ohmic contact layer is formed. The ohmic contact layer includes a source electrode resistive member 162 and a drain electrode resistive member 163 around the gate electrode 123.

The data line 171 and the drain electrode 175 are formed on the ohmic contact layer and the gate insulating layer 140. The data line 171 extends long and intersects the gate line 121, is connected to the data line 171, and extends to an upper portion of the source resistive member 162. Has a source electrode 173. One end portion 179 of the data line 171 is formed to connect with an external circuit.

Here, the data line 171 has a bent portion, a vertically extending portion, and a portion crossing the pixel electrode 190 while repeatedly dividing the pixel area from side to side with a length of the pixel. At this time, the curved portion of the data line 171 consists of two straight portions, one of the two straight portions forms 45 degrees with respect to the gate line 121, and the other portion is formed on the gate line 121. To -45 degrees. The source electrode 173 is connected to a vertically extending portion of the data line 171, and the portion crosses the gate line 121. In addition, the crossing portion is formed in parallel with the gate line 121. Here, the light leakage phenomenon occurs between the data line 171 and the data line because it is not covered by the black matrix 220 formed on the common electrode display panel 200. In order to prevent this, the floating metal pattern 122 may be formed. The floating metal pattern 122 may be formed of the same material as the gate line 121 at the same time, and may be formed between adjacent data lines.

The pixel formed by the intersection of the gate line 121 and the data line 171 has a curved band shape. A portion of the drain electrode 175 connected to the pixel electrode 190 extends in a rectangular shape and overlaps the storage electrode 133. As described above, the drain electrode 175 overlaps only the storage electrode 133 and the gate insulating layer 140, thereby forming the storage capacitor more effectively.                     

A passivation layer 180 made of an organic insulating layer is formed on the data line 171 and the drain electrode 175. The passivation layer 180 is formed by exposing and developing the photosensitive organic material. If necessary, the passivation layer 180 may be formed by coating an organic material having no photosensitivity and performing a photolithography process. In addition, the passivation layer 180 may include an insulating layer made of silicon nitride or silicon oxide.

The passivation layer 180 includes a plurality of contact holes 185 and 182 exposing the drain electrode 175 and the end portion 179 of the data line 171, respectively, and the end portion 129 of the gate line 121. A plurality of contact holes 181 exposing part of the plurality of penetrating holes penetrate the gate insulating layer 140 and the passivation layer 180.

The pixel electrode 190 is formed on the passivation layer 180 through a contact hole 185 and is connected to the drain electrode 175 and has a band shape that is bent along the shape of the pixel. At this time, the pixel electrode 190 is formed so wide that the edge thereof overlaps the data line 171, thereby ensuring the maximum aperture ratio. The contact auxiliary members 81 and 82 are connected to the respective ends 129 and 179 of the gate line and the data line through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 are essential for complementing and protecting the adhesion between the respective ends 179 of the gate line 121 and the data line 171 and an external device such as a driving integrated circuit. It is not intended that they be applied.

 The pixel electrode 190 and the contact assistants 81 and 82 are made of a transparent conductor such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductor having excellent light reflection characteristics such as aluminum (Al). .                     

The common electrode display panel 200 will now be described with reference to FIGS. 6 and 7.

The black matrix 220 and the color filters 230 of red, green, blue (R, G, and B) are sequentially formed on the lower surface of the upper substrate 210 made of a transparent insulating material such as glass. The overcoat film 250 made of an organic material is formed on the color filter 230. A common electrode 270 made of a transparent conductive material such as ITO or IZO is formed on the overcoat layer 250, and a protrusion 240 made of an organic material is formed on the common electrode 270.

At this time, the projections 240 act as domain regulating means, and the width thereof is preferably between 5 µm and 10 µm. If the cutout is formed instead of the protrusion 240 in the common electrode 270 to form the fringe field by the domain regulating means, the width of the cutout is preferably 9 μm to 12 μm.

The black matrix 220 may include a linear portion corresponding to the curved portion of the data line 171, a vertically extending portion of the data line 171, and a portion corresponding to the thin film transistor portion.

The color filters 230 of red, green, and blue (R, G, B) are vertically long along the pixel column defined by the black matrix 220 and are periodically bent along the shape of the pixel.

The protrusion 240 is also bent to form a shape that divides the curved pixel from side to side, and the end of the protrusion 240 may have various shapes.                     

In the thin film transistor array panel 100 and the common electrode panel 200 according to the exemplary embodiment of the present invention, the alignment layers 13 and 23 are formed on the surfaces facing each other. In this case, each of the alignment layers 13 and 23 may or may not be a vertical alignment layer that orients the liquid crystal molecules perpendicularly to the substrate surface.

When the liquid crystal layer 300 is formed by combining the thin film transistor array panel 100 and the common electrode display panel 200 having the above structure and injecting liquid crystal therebetween, the liquid crystal display according to the third exemplary embodiment of the present invention The panel is made.

The liquid crystal molecules included in the liquid crystal layer 300 have their directors perpendicular to the lower substrate 110 and the upper substrate 210 when no electric field is applied between the pixel electrode 190 and the common electrode 270. Oriented so as to achieve negative dielectric anisotropy.

The lower substrate 110 and the upper substrate 210 are aligned such that the pixel electrode 190 accurately overlaps the color filter 230. In this way, the liquid crystal molecules 310 of the pixel are vertically oriented with respect to the inclined plane of the protrusion 240 formed by the protrusion 240, and are dividedly oriented into a plurality of domains. At this time, the pixels are divided into left and right by the projections 240, and are divided into four types of domains in which the alignment directions of the liquid crystals are different from each other on the top and the bottom of the curved portion of the pixel.

Although the color filter 230 is disposed on the common electrode panel 200 in the structure of the liquid crystal display device, the color filter 230 may be disposed on the thin film transistor array panel 100. In this case, the gate insulating layer 140 or the passivation layer 180 may be disposed. It may be formed at the bottom.

The liquid crystal display is formed by disposing elements such as a polarizer, a backlight, and a compensation plate on both sides of the basic panel. In this case, one polarizer is disposed on each side of the base panel, and the transmission axis thereof is disposed so that one of the two is parallel to the gate line 121 and the other is perpendicular to the gate line 121.

When the liquid crystal display device is formed as described above, when an electric field is applied to the liquid crystal, the liquid crystal in each domain is inclined in a direction perpendicular to the long side of the domain. However, since the direction is perpendicular to the data line 171, the direction coincides with the direction in which the liquid crystal is inclined by the lateral electric field formed between two adjacent pixel electrodes 190 with the data line 171 therebetween. As a result, the lateral electric field assists the liquid crystal alignment of each domain.

Since the liquid crystal display generally uses inversion driving methods such as point inversion driving, thermal inversion driving, and two-point inversion driving, which apply voltages having opposite polarities to pixel electrodes positioned on both sides of the data line 171, the lateral electric field is Almost always occurs and the direction is the direction that helps the liquid crystal alignment of the domain.

In addition, since the transmission axis of the polarizing plate is disposed in a direction perpendicular to or parallel to the gate line 121, the polarizing plate can be manufactured at low cost, and the alignment direction of the liquid crystal is 45 degrees with the transmission axis of the polarizing plate in all domains, thereby obtaining the highest luminance. Can be.

As described above, thin film transistors including a gate electrode, a semiconductor layer, an ohmic contact layer, a source electrode, a drain electrode, and the like are formed by alternately shifting positions of the thin film transistors according to the pixel rows. By positioning, the parasitic capacitance generated between the gate electrode and the source / drain or the parasitic capacitance generated between the pixel electrode and the data line can be formed almost uniformly, resulting in poor visibility such as horizontal streaks, vertical streaks or flicker. Can be prevented.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (29)

Insulation board, A first signal line formed on the insulating substrate, A second signal line having a bent portion insulated from and intersecting the first signal line, A thin film transistor connected to the first signal line and the second signal line, A pixel electrode connected to the thin film transistor Including; The second signal line overlaps the vertical side of the pixel electrode and connects the first small signal line and the second small signal line, which are located opposite to the bent portion, and connects the first small signal line and the second small signal line to each other. A third small signal line extending in the same direction as the first gate line and intersecting the pixel electrode; Thin film transistor array panel comprising a.   In claim 1, A corner of the pixel electrode includes an inclined side with respect to the first signal line, The curved portion has a thin film transistor array panel having a side parallel to the inclined side. In claim 1, The pixel electrode further includes a protrusion or cutout that divides the pixel. In claim 1, A thin film transistor array panel further comprising a color filter formed on the second signal line. Insulation board, A gate line formed on the insulating substrate and including a gate electrode; A gate insulating film formed on the gate line, A semiconductor layer formed on the gate insulating film, An ohmic contact layer formed on the semiconductor layer, A data line intersecting the gate line and including a source electrode formed on the ohmic contact layer and including a bent portion; A drain electrode formed on the ohmic contact layer and facing the source electrode; A protective film covering the semiconductor layer, A pixel electrode connected to the drain electrode Including; The data line overlaps a vertical side of the pixel electrode and connects a first small data line and a second small data line opposite to the curved portion, and connects the first small data line and the second small data line. A third small data line extending from the bend in the same direction as the first gate line and intersecting the pixel electrode; Thin film transistor array panel comprising a. The method of claim 5, A corner of the pixel electrode includes an inclined side with respect to the gate line, The curved portion has a thin film transistor array panel having a side parallel to the inclined side. The method of claim 5, The semiconductor layer under the data line has the same planar shape as the data line. The method of claim 5, The pixel electrode further includes a protrusion or cutout that divides the pixel. Insulation board, A gate line formed on the insulating substrate and including a gate electrode; A gate insulating film formed on the gate line, A semiconductor layer formed on the gate insulating film, An ohmic contact layer formed on the semiconductor layer, A data line intersecting the gate line and including a source electrode and a bent portion formed on the ohmic contact layer; A drain electrode formed on the ohmic contact layer and facing the source electrode; A color filter formed on the data line, the source electrode and the drain electrode; A pixel electrode formed on the color filter and connected to the drain electrode Including; The data line overlaps a vertical side of the pixel electrode and connects a first small data line and a second small data line opposite to the curved portion, and connects the first small data line and the second small data line. And a third small data line extending from the bend in the same direction as the first gate line and crossing the pixel electrode. The method of claim 9, A thin film transistor substrate further comprising a passivation layer disposed between the color filter and the pixel electrode.  The method of claim 9, And a passivation layer made of silicon nitride (SiNx) disposed between the color filter, the source electrode and the drain electrode, and the semiconductor layer. The method of claim 9, The data line is disposed on the left and right with respect to the pixel electrode. The method of claim 9, The thin film transistor array panel of claim 1, further comprising a black matrix formed on the source electrode, the drain electrode, and the semiconductor layer. The method of claim 9, A corner of the pixel electrode includes an inclined side with respect to the first signal line, The curved portion has a thin film transistor array panel having a side parallel to the inclined side. The method of claim 9, The pixel electrode further includes a protrusion or cutout that divides the pixel. Insulation board, A first signal line formed on the insulating substrate and extending in a first direction, A plurality of straight portions formed on the insulating substrate and intersecting the first signal lines, bent portions connecting adjacent straight portions, and connected to the bent portions and bisecting the bent portions, such as the first signal lines; A second signal line having a horizontal portion extending in the direction, A thin film transistor connected to the first signal line and the second signal line, A pixel electrode connected to the thin film transistor Including, The vertical side of the pixel electrode overlaps the straight portion and the curved portion. Thin film transistor display panel. The method of claim 16, The curved portion of the second signal line includes two straight portions, one of the two straight portions making up substantially 45 degrees with respect to the first signal line and the other substantially -45 degrees with respect to the first signal line. Thin film transistor array panel. The method of claim 16, And a third signal line extending in the first direction, wherein a terminal of the thin film transistor connected to the pixel electrode overlaps the third signal line to form a storage capacitor. Insulation board, A gate line formed on the insulating substrate and having a gate electrode, A gate insulating film formed on the gate line, A semiconductor layer formed on the gate insulating film, A horizontal portion formed on the gate insulating layer and extending in the same direction as the gate line from a position where the straight portion intersects the gate line, a curved portion connecting neighboring straight portions, and the curved portion and bisects the curved portion A data line with A source electrode connected to the data line and formed on the semiconductor layer; A drain electrode formed on the semiconductor layer and facing the source electrode on the gate electrode; A protective film covering the semiconductor layer, A pixel electrode electrically connected to the drain electrode Including; The vertical side of the pixel electrode overlaps the straight portion and the curved portion. The method of claim 19, A thin film transistor substrate positioned between the data line and the data line and having a floating metal pattern made of the same material as the gate line. The method of claim 19, The curved portion of the data line includes a first portion that is 45 degrees with the gate line and a second portion that is -45 degrees with the gate line. The method of claim 19, A storage electrode line formed to be parallel to the gate line and the storage electrode line and having a width wider than that of the storage electrode line, wherein the drain electrode has an extended width of a portion connected to the pixel electrode; A thin film transistor array panel in which a portion connected to the pixel electrode overlaps the storage electrode. The method of claim 19, And a sustain electrode line formed to be parallel to the gate line and the sustain electrode line and wider than the sustain electrode line, wherein the drain electrode has an extended width of a portion connected to the pixel electrode. A thin film transistor array panel having a portion overlapping with the sustain electrode and the sustain electrode line overlapping the cutout portion. The method of claim 19, Further comprising a color filter formed on the lower portion of the protective film, In the color filter, red, green, and blue color filters are formed long along the pixel columns separated by the data lines, and red, green, and blue colors appear repeatedly. Thin film transistor display panel. First insulating substrate, A first signal line formed on the first insulating substrate, A plurality of straight portions formed on the first insulating substrate and intersecting the first signal lines, bent portions connecting neighboring straight portions, and the first signal lines connected to the bent portions and bisecting the bent portions; A second signal line having a horizontal portion extending in the same direction as A thin film transistor connected to the first signal line and the second signal line, A pixel electrode connected to the thin film transistor, A second insulating substrate facing the first insulating substrate, A common electrode formed on the second insulating substrate, Liquid crystal layer injected between the first insulating substrate and the second insulating substrate Including, The liquid crystal molecules of the liquid crystal layer are divided and oriented into a plurality of domains by domain dividing means, and two long sides of the domain are parallel to the bent portion of the adjacent second signal line. Liquid crystal display.  The method of claim 25, And a floating metal pattern positioned between the second signal line and the second signal line on the first insulating substrate. The method of claim 25, The liquid crystal molecules included in the liquid crystal layer have negative dielectric anisotropy, and the liquid crystal has a long axis perpendicular to the first and second substrates. The method of claim 25, The liquid crystal molecules included in the liquid crystal layer have positive dielectric anisotropy, and the liquid crystal molecules are arranged in a long axis to be oriented parallel to the first and second substrate planes and to be twisted from the first substrate to the second substrate. Liquid crystal display. The method of claim 25, The domain dividing means is a protrusion formed on the common electrode or the pixel electrode, And a cutout formed in the common electrode or the pixel electrode.

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