KR101071254B1 - Thin film transistor panel and multi-domain liquid crystal display including the same - Google Patents

Abstract

  A gate line having a gate electrode formed on the insulating substrate, a semiconductor layer formed on the gate insulating film covering the gate line, a data line having a bent portion and a portion orthogonal to the gate line, having a source electrode formed on the semiconductor layer, and a gate A drain electrode facing the source electrode at an upper portion of the electrode, a passivation layer covering the exposed semiconductor layer, and a pixel electrode formed on the passivation layer, electrically connected to the drain electrode, and bent along the data line with a side adjacent to the data line; A thin film transistor array panel is prepared. In this case, the pixel is divided into two parts, and the pixel electrode includes a first pixel electrode and a second pixel electrode formed in the two subpixels. Further, the thin film transistor array panel is disposed on both sides of the data line and has a sustain electrode wiring including a sustain electrode partially overlapping the first and second pixel electrodes.

Domains, curved data lines, thin film transistors, sustain electrodes

Description

Thin film transistor array panel and multi-domain liquid crystal display including the same {THIN FILM TRANSISTOR PANEL AND MULTI-DOMAIN LIQUID CRYSTAL DISPLAY INCLUDING THE SAME}

1 is a layout view of a liquid crystal display including a thin film transistor array panel according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II-II 'of the liquid crystal display of FIG. 1.

3 is a layout view of a liquid crystal display including a thin film transistor array panel according to a second exemplary embodiment of the present invention.

FIG. 4 is a cross-sectional view taken along the line IV-IV 'of the liquid crystal display of FIG. 3.

5 is a layout view of a liquid crystal display including a thin film transistor array panel according to a third exemplary embodiment of the present invention.

6 is a cross-sectional view taken along the line VI-VI 'of the liquid crystal display of FIG. 5.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array panel and a liquid crystal display device including the same, and more particularly, to a liquid crystal display device having a vertical alignment method for dividing a pixel into a plurality of domains to obtain a wide viewing angle, and a thin film transistor array panel thereof.

In general, a liquid crystal display device injects a liquid crystal material between an upper display panel on which a common electrode, a color filter, and the like are formed, and a lower display panel on which a thin film transistor and a pixel electrode are formed. By applying a different potential to form an electric field to change the arrangement of the liquid crystal molecules, and through this to control the light transmittance is a device that represents the image.

However, it is an important disadvantage that the liquid crystal display device has a narrow viewing angle. In order to overcome these disadvantages, various methods for widening the viewing angle have been developed. Among them, liquid crystal molecules are oriented vertically with respect to the upper and lower substrates, and a method of forming a constant incision pattern or protrusion on the pixel electrode and the common electrode opposite thereto is performed. This is becoming potent.

However, in the method of forming the protrusions or the incision pattern, the opening ratio is lowered due to the protrusions or the incision pattern portion. In order to compensate for this, an ultra-high-aperture structure that forms the pixel electrode as wide as possible has been devised. However, since the distance between adjacent pixel electrodes is very close, a lateral field formed between the pixel electrodes is strongly formed. Accordingly, the liquid crystals positioned at the edges of the pixel electrodes are affected by the lateral electric field, which causes the alignment to be disturbed. As a result, texture or light leakage occurs, thereby degrading display characteristics.

In general, when the active area of the panel for the liquid crystal display device is larger than the mask size, the active area is divided to perform a step and repeat process in order to form a pattern in the active area. Exposure is necessary. In this case, the actual shot may cause distortion such as shift, rotation, and distortion of the mask, so that the shots are not aligned correctly, and thus the parasitic capacitance difference between each wiring and the pixel electrode between the shots is different. Or a pattern position difference occurs. Since the difference in parasitic capacitance and the difference in pattern position cause differences in electrical characteristics and aperture ratios of the regions, respectively, the difference in screen brightness at the boundary between shots results in a stitch failure.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a thin film transistor array panel that forms a stable multi-domain while securing an aperture ratio and a liquid crystal display including the same.

Another object of the present invention is to provide a thin film transistor array panel capable of minimizing stitch defects and a liquid crystal display including the same.

In order to solve this problem, the present invention provides the following thin film transistor array panel and liquid crystal display device.                     

In the thin film transistor array panel according to the exemplary embodiment of the present invention, a first signal line extending in a first direction is formed on an insulating substrate, and is insulated from and intersects with the first signal line, and has a curved portion and a portion extending in a second direction. The second signal line is formed. A pixel electrode is formed in each pixel defined by the intersection of the first signal line and the second signal line, and overlaps with the pixel electrode to form a storage capacitor, and is disposed at the edge of the pixel and extends in parallel to the second signal line. The branch has a third signal line formed therein. Each pixel is formed with a thin film transistor connected to a first signal line, a second signal line, and a pixel electrode.

In this case, the pixel is divided into at least two subpixels, and the curved portion and the portion extending in the second direction of the second signal line are repeatedly displayed based on the length of the pixel.

The subpixels are respectively located on both sides of the second signal line, and the pixel electrode includes first and second pixel electrodes that are cut and positioned respectively in the subpixel, and the thin film transistor is connected to the first and second pixel electrodes, respectively. And a second thin film transistor.

Branches of the third signal line are respectively disposed on both sides of the second signal line, and preferably overlap the edges of the first and second pixel electrodes, and the branch of the third signal line partially overlaps the first and second pixel electrodes. The boundary between the first and second pixel electrodes is preferably located at the branch of the third signal line.

In this case, the first and second pixel electrodes are connected to each other through the connection part, and the connection part preferably crosses the bent portion of the second signal line, and preferably the same layer as the pixel electrode or the first signal line.

Preferably, the bent portion of the second signal line includes two or more straight portions, and the two or more straight portions form substantially alternately ± 45 degrees with respect to the first signal line.

In a thin film transistor array panel according to another exemplary embodiment of the present invention, a gate line having a gate electrode is formed on an insulating substrate, and a semiconductor layer is formed on the gate insulating film formed on the gate line. On top of that, at least a portion has a source electrode positioned on the semiconductor layer, a data line having a bent portion and a portion orthogonal to the gate line is formed, at least a portion of which is positioned on the semiconductor layer and above the gate electrode, respectively. Opposite drain electrodes are formed, and a protective film covering the semiconductor layer is formed. A pixel electrode is formed on the passivation layer, the pixel electrode including first and second pixel electrodes electrically connected to the drain electrode, a side adjacent to the data line, and bent along the data line and divided into at least two parts. And a storage electrode wiring overlapping with the second pixel electrode to form a storage capacitor, and having the storage electrode extending parallel to the curved portion of the data line.

Preferably, the curved portion of the data line forms a ± 45 degree angle with the gate line. The first and second pixel electrodes are disposed on both sides of the data line, and the storage electrode is disposed on both sides of the data line. It is preferable to overlap the edge of the second pixel electrode. In this case, only a portion of the storage electrode overlaps the first and second pixel electrodes, and the boundary between the storage first and second pixel electrodes is positioned above the storage electrode.                     

The first and second pixel electrodes are connected to each other through a connection part. The connection part may be formed of the same layer as the first and second pixel electrodes, and the connection part may be formed of the same layer as the gate line. The connection part crosses the bent portion of the data line to connect the first and second pixel electrodes to each other.

The liquid crystal display according to the exemplary embodiment of the present invention includes a first insulating substrate, a first signal line formed on the first insulating substrate, a first signal line formed on the first insulating substrate, insulated from and intersecting the first signal line, and having a refractive portion. A pixel electrode formed for each pixel defined by the intersection of the two signal lines, the first signal line and the second signal line, and a third signal line having a branch overlapping with the pixel electrode to form a storage capacitor, and having a branch disposed in parallel with the second signal line; A thin film transistor connected to the first signal line, the second signal line and the pixel electrode, a second insulating substrate facing the first insulating substrate, a common electrode formed on the second insulating substrate, the first insulating substrate and the second insulating substrate; Domain dividing means formed on at least one side of the insulating substrate, and a liquid crystal layer injected between the first insulating substrate and the second insulating substrate. In this case, the pixel is divided into at least two subpixels, and the liquid crystal molecules of the liquid crystal layer are divided and oriented into a plurality of domains by domain dividing means, and long sides of the domains are substantially parallel to the refraction portions of the adjacent second signal lines.

It is preferable that the liquid crystal molecules contained in the liquid crystal layer have negative dielectric anisotropy, and the liquid crystal has its long axis oriented perpendicular to the first and second substrates. It may be a cutout formed in the pixel electrode or the common electrode.                     

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Next, a multi-domain thin film transistor array panel and a thin film transistor array panel including the same according to an exemplary embodiment of the present invention will be described with reference to the drawings.

1 is a layout view of a liquid crystal display including a thin film transistor array panel according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the liquid crystal display of FIG. 1 taken along the line II-II ′.

In the liquid crystal display according to the first exemplary embodiment of the present invention, the thin film transistor array panel 100, the common electrode panel 200 facing each other, and the long axis of the liquid crystal molecules contained therebetween are injected between the two display panels. It consists of a liquid crystal layer 300 oriented perpendicular to the.

First, the thin film transistor array panel according to the first embodiment of the present invention will be described in more detail with reference to FIGS. 1 and 2.

A plurality of gate lines 121 are formed on the insulating substrate 110 to transfer gate signals. The gate line 121 mainly extends in the horizontal direction, and a part of each gate line 121 forms a plurality of gate electrodes. In this case, the gate electrode includes first and second gate electrodes 124a and 124b. One end portion of the gate line 121 may be widened for connection with an external circuit, and in an embodiment of directly designing a gate driving circuit on the insulating substrate 110, the end portion of the gate line may be a gate driving circuit. It is connected to the output terminal of.

In addition, double sustain electrode lines 131a and 131b, first and second sustain electrodes 133a and 133b, and third sustain electrodes 134 and 135 are formed on the insulating substrate 110. It is. The storage electrode lines 131a and 131b extend in the horizontal direction, and the first and second storage electrodes 133a and 133b are connected to the storage electrode lines 131a adjacent to the gate line 121 in a rhombus or a rectangle, respectively. It is disposed adjacent to the first and second gate electrodes 124a and 124b. The third storage electrodes 134 and 135 connect the dual storage electrode lines 131a and 131b to each other and have a curved shape along the shape of the pixel. The portion 134 of the data line 171 is formed later. The remaining portions 135 are disposed between the subpixels Pa and Pb of pixels adjacent to each other.

The gate line 121 and the storage electrode wirings 131a, 131b, 133a, 133b, 134, and 135 may include two films having different physical properties, and may be formed of a single film. In the case of two conductive films, one film is made of a low resistivity metal such as aluminum (Al) or an aluminum alloy such as aluminum to reduce the delay or voltage drop of the gate signal. Membranes have excellent physical, chemical and electrical contact properties with other materials, especially indium zinc oxide (IZO) or indium tin oxide (ITO), such as molybdenum (Mo), molybdenum alloys (eg molybdenum-tungsten (MoW) alloys), It is preferably made of chromium (Cr) or the like.

The side edges of the gate line 121 and the sustain electrode wirings 131a, 131b, 133a, 133b, 134, and 135 are inclined, and the inclination angle is in the range of about 30 to 80 ° with respect to the surface of the substrate 110. A gate insulating layer 140 made of silicon nitride or the like is formed.

A plurality of semiconductors 151 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) and the like are formed on the gate insulating layer 140 of the first and second gate electrodes 124a and 124b. have. The semiconductor layer 151 includes a channel portion that forms a channel of the thin film transistor, and the channel portion includes a first channel portion disposed on the first gate electrode 124a and a second channel disposed on the second gate electrode 124b. Contains wealth. In this case, the semiconductor layer 154 may be linear along the data line 171 formed later, which will be described in another embodiment.

An ohmic contact made of a material such as n + hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration is formed on the semiconductor layer 154. The ohmic contact layer includes a source resistive contact member 163 positioned at the center of the first and second gate electrodes 124a and 124b and a first resistive contact member based on the first and second gate electrodes 124a and 124b. First and second drain resistive contact members 165a and 165b facing 163, respectively.

The data line 171 and the first and second drain electrodes 175a and 175b are formed on the ohmic contacts 163, 165a and 165b and the gate insulating layer 140. The data line 171 extends long and crosses the gate line 121, and has a source electrode 173 connected to the data line 171 and extending to an upper portion of the source ohmic contact 163. The first and second drain electrodes 175a and 175b are separated from the source electrode 173 and the first and second drain portions opposite to the source electrode 173 with respect to the first and second gate electrodes 124a and 124b. The resistive contact members 165a and 165b are positioned on the upper side, respectively. One end portion 179 of the data line 171 is extended in width to connect to an external circuit.

Here, the data line 171 has a portion that is repeatedly curved and a portion that extends vertically with a length of the pixel. At this time, the curved portion of the data line 171 consists of two straight portions, one of the two straight portions forms 45 degrees with respect to the gate line 121, and the other portion is formed on the gate line 121. To -45 degrees. The source electrode 173 is connected to a vertically extending portion of the data line 171, and the portion crosses the gate line 121.

At this time, the ratio of the lengths of the bent portion and the vertically extending portion of the data line 171 is between 1: 1 and 9: 1 (that is, the ratio of the bent portion of the data line 171 is between 50% and 90%). )to be.

Accordingly, the pixel formed by the intersection of the gate line 121 and the data line 171 has a curved band shape, and is divided into two subpixels Pa and Pb around the data line 171.

In addition, the first and second drain electrodes 175a and 175b have a rectangular shape in which portions connected to the first and second pixel electrodes 191a and 192b are widened in a rectangular shape so that the first and second storage electrodes 133a and 133b are extended. Nested with As described above, the first and second drain electrodes 175a and 175b overlap the first and second storage electrodes 133a and 133b with only the gate insulating layer 140 interposed therebetween to more effectively form the storage capacitor.

A-Si: C: O formed on the data line 171, the first and second drain electrodes 175a and 175b, and the exposed semiconductor layer 154 by plasma enhanced chemical vapor deposition (PECVD). A passivation layer 180 made of a low dielectric constant insulating material such as a-Si: O: F, or silicon nitride, which is an inorganic material, is formed.

The passivation layer 180 is formed with contact holes 185a and 185b exposing the first and second drain electrodes 175a and 175b and contact holes 182 exposing the end portions 179 of which the width of the data line is extended. . In addition, the passivation layer 180 may have a contact hole that exposes an end portion (not shown) of the gate line 121 together with the gate insulating layer 140.

At this time, as shown in FIG. 2, the sidewalls of the contact holes 185a and 185b have a gentle inclination between 30 degrees and 80 degrees with respect to the surface of the substrate 110, or have a stepped profile.

In addition, these contact holes (185a, 185b) may be formed in a variety of shapes having a flat or angled plane, the area is not more than 2mm × 60㎛, preferably 0.5mm × 15㎛ or more.

The passivation layer 180 is connected to the first and second drain electrodes 175a and 175b through the contact holes 185a and 185b, respectively, and has a band shape that is bent along the shape of the pixel. 191b) is formed in each of the subpixels Pa and Pb. In this case, the edges of the first and second pixel electrodes 191a and 191b overlap the third sustain electrodes 134 and 135, and the edges of the first and second pixel electrodes 191a and 191b have edges. 3 are positioned above the sustain electrodes 134 and 135. The first and second pixel electrodes 191a and 191b are connected to each other through the connection unit 192.

The data contact auxiliary member 82 is formed on the passivation layer 180 and is connected to the end portion 179 of the data line through the contact hole 182. Of course, the gate contact auxiliary member may be added to the end portion of the gate line 121. The pixel electrodes 191a and 191b and the contact auxiliary member 82 may be made of indium tin oxide (ITO) or indium zinc oxide (IZO).

A common electrode display panel will now be described with reference to FIGS. 1 and 2.

On the lower surface of the upper substrate 210 made of a transparent insulating material such as glass, a black matrix 220 and red, green, and blue color filters 230 are sequentially formed to prevent light leakage. ), An overcoat film 250 made of silicon nitride or an organic material is formed. A common electrode 270 made of a transparent conductive material such as ITO or IZO is formed on the overcoat layer 250, and a protrusion 240 made of an organic material is formed on the common electrode 270.

At this time, the projections 240 act as domain regulating means, and the width thereof is preferably between 5 µm and 10 µm. If the cutout is formed instead of the protrusion 240 in the common electrode 270 to form the fringe field by the domain regulating means, the width of the cutout is preferably 9 μm to 12 μm. The dispositional shape of the incision is similar to the protrusion 240.

The cutout may be formed on the pixel electrodes 190a and 190b as domain regulating means, and the protrusion 240 may also be disposed on the pixel electrodes 190a and 190b.

The black matrix 220 may include a linear portion corresponding to the curved portion of the data line 171, a vertically extending portion of the data line 171, and a portion corresponding to the thin film transistor portion.

The red, green, and blue color filters 230 are vertically elongated along the pixel columns partitioned by the black matrix 220, and periodically bent along the shape of the pixels.

The protrusions 240 are also bent to form a shape that bisects the curved subpixels from side to side, and the ends of the protrusions 240 may have various shapes.

In the thin film transistor array panel 100 and the common electrode panel 200 according to the exemplary embodiment of the present invention, the alignment layers 11 and 21 are formed on the surfaces facing each other. In this case, each of the alignment layers 11 and 21 may or may not be a vertical alignment layer that vertically aligns the liquid crystal molecules with respect to the substrate surface.                     

When the liquid crystal layer 300 is formed by combining the thin film transistor array panel 100 and the common electrode panel 200 having the above structure and injecting liquid crystal therebetween, the liquid crystal display according to the first exemplary embodiment of the present invention The panel is made.

The liquid crystal molecules included in the liquid crystal layer 300 have directors with respect to the lower substrate 110 and the upper substrate 210 when no electric field is applied between the pixel electrodes 191a and 191b and the common electrode 270. It is oriented perpendicularly and has negative dielectric anisotropy.

The lower substrate 110 and the upper substrate 210 are aligned such that the first and second pixel electrodes 191a and 191b accurately overlap with the color filter 230. In this way, the liquid crystal molecules 310 of the pixel are vertically oriented with respect to the inclined plane of the protrusion 240 formed by the protrusion 240, and are dividedly oriented into a plurality of domains. At this time, the subpixels are divided into left and right sides by the protrusions 240, and are divided into four types of domains in which the alignment directions of the liquid crystals are different from each other in the upper and lower directions with respect to the bent portion of the subpixel. In the drawing, the subpixels are arranged up and down with respect to one bent portion, and at least two or more bent portions may be arranged.

Although the color filter 230 is disposed on the common electrode panel 200 in the structure of the liquid crystal display device, the color filter 230 may be disposed on the thin film transistor array panel 100. In this case, the gate insulating layer 140 or the passivation layer 180 may be disposed. It may be formed at the bottom.

The liquid crystal display is formed by disposing elements such as a polarizer, a backlight, and a compensation plate on both sides of the basic panel. At this time, the polarizing plate is disposed one each on both sides of the base panel and the transmission axis is arranged so that one of the two side by side and the other is perpendicular to the gate line 121.

When the liquid crystal display device is formed as described above, when an electric field is applied to the liquid crystal, the liquid crystal in each domain is inclined in a direction perpendicular to the long side of the domain. However, since the direction is perpendicular to the data line 171, the liquid crystal is inclined by the lateral electric field formed between two adjacent pixel electrodes 191a and 191b with the data line 171 therebetween. As a match, the lateral electric field assists the liquid crystal alignment of each domain.

Since the liquid crystal display generally uses inversion driving methods such as point inversion driving, thermal inversion driving, and two-point inversion driving, which apply voltages having opposite polarities to pixel electrodes positioned on both sides of the data line 171, the lateral electric field is Almost always occurs and the direction is the direction that helps the liquid crystal alignment of the domain.

In addition, since the transmission axis of the polarizing plate is disposed in a direction perpendicular to or parallel to the gate line 121, the polarizing plate can be manufactured at low cost, and the alignment direction of the liquid crystal is 45 degrees with the transmission axis of the polarizing plate in all domains, thereby obtaining the highest luminance. Can be.

In the thin film transistor array panel according to the first exemplary embodiment of the present invention, each of the subpixel electrodes 190a and 190b overlaps with the third storage electrodes 134 and 135, but overlaps with the data line 171. Since parasitic capacitance is hardly generated between the subpixel electrodes 190a and 190b and the data line 171, even when misalignment occurs during the manufacturing process, the subpixel electrodes 190a and 190b are centered on the data line 171. It is arrange | positioned at both sides, and becomes a structure which compensates for parasitic capacitance. Therefore, the pixel voltage transmitted to the pixel electrode hardly causes distortion, thereby preventing spots from occurring when displaying an image, and preventing difference in screen brightness due to no difference in screen brightness at the boundary between shots. can do.

In the thin film transistor array panel according to the exemplary embodiment of the present invention, a storage capacitor is formed at a portion where the pixel electrodes 190a and 190b and the third storage electrodes 134 and 135 overlap with each other, thereby sufficiently securing the storage capacitor.

Also, in the liquid crystal display having the above structure, when an electric field is applied to the liquid crystal, the liquid crystal molecules adjacent to the thin film transistor array panel and positioned at the edges of the subpixels Pa and Pb among the liquid crystal molecules in each domain are first and second. The orientation is divided by the fringe field formed at the boundary between the pixel electrodes 191a and 191b. In this case, portions of the third storage electrodes 134 and 135 are exposed at lower edges of the first pixel electrode 191a and the second pixel electrode 191b, and the common electrode 270 is exposed to the third storage electrodes 134 and 135. The common voltage applied to the third voltage is transferred to the third sustain electrodes 134 and 135 to strengthen the fringe fields formed at the boundary between the first and second pixel electrodes 191a and 191b. An interval between the first pixel electrode 191a and the second pixel electrode 191b may be closely arranged, thereby maximizing the aperture ratio of the pixel.

In the liquid crystal display device having such a structure, a method of manufacturing a thin film transistor array panel will be briefly described.

First, a metal layer made of Cr or Mo alloy or the like or a metal layer made of Al or Ag alloy having low resistance is successively laminated by a sputtering method, and then dry or wet etched by the first photolithography process using a mask to form a gate line 121. ) And sustain electrode wirings 131a, 131b, 133a, 133b, 134, and 135.

Next, the gate insulating layer 140, the hydrogenated amorphous silicon layer, and the amorphous silicon layer doped with a high concentration of n-type impurities such as phosphorus (P) are respectively 1,500 kPa to 5,000 kPa, 500 kPa to 2,000 kPa using chemical vapor deposition. , The resistive contact layer and the amorphous silicon semiconductor layer 154 having the channel portion connected by successively depositing a thickness of 300 600 to 600 Å and patterning the doped amorphous silicon layer and the amorphous silicon layer by a photolithography process using a mask. To form.

Subsequently, a conductive film made of Cr or Mo alloy or the like or a conductive film made of Al or Ag alloy having low resistance is deposited by sputtering or the like, and then patterned by a photolithography process using a mask to form the data line 171 and the first and Second drain electrodes 175a and 175b are formed.

Subsequently, the ohmic contact layer that is not covered by the data line 171 and the first and second drain electrodes 175a and 17b is etched to form a gap between the source electrode 173 and the first and second drain electrodes 175a and 175b. The semiconductor layer 154 is exposed to form ohmic contacts 163, 165a, and 165b that are separated on both sides.

Next, the passivation layer 180 is formed, and the passivation layer 180 is patterned together with the gate insulating layer 140 to form contact holes 185a, 185b, and 182.

Next, as shown in FIGS. 1 and 2, ITO or IZO is deposited to 400 500 to 500 Å thickness and photo-etched to form the first and second pixel electrodes 191a and 191b and the contact auxiliary members 192 and 199. Form.

On the other hand, in the thin film transistor array panel according to the first embodiment of the present invention, the first and second pixel electrodes 191a and 191b are connected to each other through a connection part 192 formed of the same layer, but they are electrically conductive in different layers. It may be connected through a membrane, which will be described in detail with reference to the accompanying drawings.

3 is a layout view illustrating a structure of a liquid crystal display including a thin film transistor array panel according to a second exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view of the liquid crystal display of FIG. 3 taken along line IV-IV ′. .

As shown in FIGS. 3 and 4, most of the structures are the same as those of FIGS. 1 and 2.

However, unlike FIGS. 1 and 2, the third storage electrode 134 disposed adjacent to the data line 171 is separated from the bent portion of the pixel region, and the bent portion of the data line 171 is formed therein. And a subpixel electrode connection portion 128 that intersects with each other. In this case, the subpixel electrode connector 128 forms the same layer as the gate line 121 and is connected to the two subpixel electrodes 190a and 190b through the contact hole 188 of the passivation layer 180 and the gate insulating layer 140. The two subpixel electrodes 190a and 190b disposed on both sides of the data line 171 are electrically connected to each other.

The thin film transistor array panel according to the first and second embodiments of the present invention may be completed by a photolithography process using five masks, but the thin film transistor array panel may be completed using four masks. In this manufacturing method, the data line 171, the drain electrodes 175a and 175b, and the semiconductor layer 154 are formed by a photolithography process using one photoresist pattern, and the photoresist pattern corresponds to a channel portion of the thin film transistor. Has a thickness lower than that corresponding to other data lines and drain electrodes. In this case, the structure of the completed thin film transistor array panel is slightly different from that of FIGS. 1 to 4, which will be described in detail with reference to the accompanying drawings.

FIG. 5 is a layout view illustrating a structure of a liquid crystal display including a thin film transistor array panel according to a third exemplary embodiment. FIG. 6 is a cross-sectional view of the liquid crystal display of FIG. 5 taken along line VI-VI ′. to be.

As shown in Figs. 5 and 6, the layer structure of the thin film transistor array panel for liquid crystal display according to the present embodiment is generally the same as the layer structure of the thin film transistor array panel for liquid crystal display shown in Figs. That is, the plurality of gate lines 121 including the plurality of gate electrodes 124a and 124b are formed on the substrate 110, and the gate insulating layer 140, the plurality of semiconductors 154, and the plurality of ohmic contacts are formed thereon. The members 163, 165a, and 165b are formed in order. A plurality of data lines 171 including a plurality of source electrodes 173 and a plurality of first and second drain electrodes 175a and 175b are disposed on the ohmic contacts 163, 165a and 165b and the gate insulating layer 140. It is formed, and the protective film 180 is formed thereon. A plurality of contact holes 182, 185a, and 185b are formed in the passivation layer 180 and / or the gate insulating layer 140, and the plurality of subpixel electrodes 190a and 190b and the plurality of contact assistant members are disposed on the passivation layer 180. 82 is formed.

However, unlike the thin film transistor array panel shown in FIGS. 1 to 4, in the thin film transistor array panel according to the present exemplary embodiment, the semiconductor layer 154 extends linearly with the data line 171, and the ohmic contact member 163 also includes data. It extends longitudinally with the line 171.

In this case, the semiconductor layer 154 may be substantially formed of the data line 171, the first and second drain electrodes 175a and 175b, and the ohmic contacts 163, 165a and 165b below the thin film transistor. It has the same planar shape.

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

As described above, when the data line is refracted to form a pixel in the shape of a band, a lateral electric field between adjacent pixels acts in a direction to help the formation of the domain so that the domain is stably formed and the sustain electrode line to which the common voltage is applied is formed. The aperture ratio of the pixel may be maximized by placing the overlapping portion of the electrode to strengthen the fringe field. In addition, by dividing the pixel into two subpixels and arranging the subpixels on both sides of the data line, variations in parasitic capacitance between the data line and the pixel electrode may occur even if distortion, such as transition, rotation, or distortion, of the mask occurs during the manufacturing process. Can be minimized to prevent the difference in screen brightness.

Claims (17)

Insulation board, A first signal line formed on the insulating substrate and extending in a first direction, A second signal line formed on the insulating substrate and insulated from and intersecting the first signal line, the second signal line having a curved portion and a portion extending in a second direction; A first thin film transistor and a second thin film transistor connected to the first signal line and the second signal line, A pixel electrode including a first digestive electrode connected to the first thin film transistor and a second digestive electrode connected to the second thin film transistor, The first digestive electrode and the second digestive electrode are bent in the same shape as the bent portion of the second signal line, and the first digestive electrode and the second digestive electrode are opposite to the second signal line. The thin film transistor array panel located in the. delete In claim 1, A third signal line positioned on both sides of the second signal line and including a branch extending in parallel with the bent portion of the second signal line and intersecting the first signal line; The boundary line of the first digestive electrode and the second digestive electrode is positioned on the branch. In claim 1, And the first digestive electrode and the second digestive electrode are connected to each other through a connection part and a contact hole formed on the same layer as the first signal line. 4. The method of claim 3, And the first digestive electrode and the second digestive electrode are connected to each other through a contact hole and a connection part formed on the same layer as the first signal line. The method of claim 5, The curved portion of the second signal line includes two or more straight portions, and the two or more straight portions form ± 45 degrees substantially alternately with respect to the first signal line. In claim 6, The connection part is a thin film transistor array panel positioned at the point where the straight portion meets. Insulation board, A gate line formed on the insulating substrate and having a gate electrode, A gate insulating film formed on the gate line, A semiconductor layer formed on the gate insulating film, At least a part of the data line having a source electrode formed on the semiconductor layer and having a bent portion and a portion orthogonal to the gate line; A drain electrode formed on the semiconductor layer and facing the source electrode on the gate electrode; A protective film covering the semiconductor layer, A pixel electrode electrically connected to the drain electrode, the pixel electrode including a first digestive electrode and a second digestive electrode positioned on opposite sides of the data line; Including, The first digestive electrode and the second digestive electrode are bent along the data line, and the first digestive electrode and the second digestive electrode are connected to a contact portion and a contact hole positioned on the same layer as the gate line. The thin film transistor array panel is connected to each other through. In claim 8, The curved portion of the data line forms a ± 45 degree angle with the gate line. In claim 8, A storage electrode line positioned on both sides of the data line and extending in parallel with the bent portion of the data line, and further comprising a storage electrode line crossing the gate line; The boundary line between the first digestive electrode and the second digestive electrode is on the sustain electrode. delete delete delete delete First insulating substrate, A first signal line formed on the first insulating substrate, A second signal line formed on the first insulating substrate and insulated from and intersecting the first signal line and having a bent portion; A first thin film transistor and a second thin film transistor connected to the first signal line and the second signal line, A pixel electrode including a first digestive electrode connected to the first thin film transistor and a second digestive electrode connected to the second thin film transistor; A second insulating substrate facing the first insulating substrate, A common electrode formed on the second insulating substrate, Domain dividing means formed on at least one side of said first insulating substrate and said second insulating substrate, Liquid crystal layer injected between the first insulating substrate and the second insulating substrate Including, The first digestive electrode and the second digestive electrode are bent in the same shape as the bent portion of the second signal line, and the first digestive electrode and the second digestive electrode are opposite to the second signal line. Liquid crystal display located in the. 16. The method of claim 15, And the first digestive electrode or the second digestive electrode are dividedly oriented into a plurality of domains by domain dividing means, and the long side of the domain is parallel to the bent portion of the adjacent second signal line. 16. The method of claim 15, And the domain dividing means is a protrusion formed on the common electrode or a cutout formed on the pixel electrode or the common electrode.

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