KR101725424B1 - Array substrate for fringe field switching mode liquid crystal display device and method of fabricating the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a fringe field switching mode liquid crystal display device capable of reducing power consumption and a manufacturing method thereof.

The present invention is characterized by further comprising a second passivation layer over the first passivation layer located on the front surface of the substrate and completely overlapping the gate and data lines at the boundary of each pixel area.

A protective layer of a triple layer structure having a thickness of 6000 ANGSTROM or more is formed between the data line and the common electrode and a protective layer of a single layer structure having a thickness of less than 6000 ANGSTROM is formed between the common electrode and the pixel electrode, There is an effect that the fringe field strength between the common electrodes is improved and the driving voltage is reduced.

In addition, there is an effect of reducing power consumption by reducing the driving voltage.

Fringe field, liquid crystal display, driving voltage, array substrate, parasitic capacitance

Description

[0001] The present invention relates to an array substrate for a fringe field switching mode liquid crystal display device and a manufacturing method thereof,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a fringe field switching mode liquid crystal display device capable of reducing power consumption and a manufacturing method thereof.

In general, a liquid crystal display device is driven by using optical anisotropy and polarization properties of a liquid crystal. Since the liquid crystal has a long structure, it has a directionality in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal by optical anisotropy, so that image information can be expressed.

At present, an active matrix liquid crystal display (AM-LCD: hereinafter referred to as liquid crystal display) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has excellent resolution and video realization capability, It is attracting attention.

The liquid crystal display device includes a color filter substrate on which a common electrode is formed, an array substrate on which pixel electrodes are formed, and a liquid crystal interposed between the two substrates. In such a liquid crystal display device, The liquid crystal is driven to have excellent properties such as transmittance and aperture ratio.

However, liquid crystal driving by an electric field that is applied up and down has a drawback that the viewing angle characteristic is not excellent.

Therefore, a transverse electric field type liquid crystal display device having excellent viewing angle characteristics has been proposed to overcome the above disadvantages.

Hereinafter, a general transverse electric field type liquid crystal display device will be described in detail with reference to FIG.

1 is a cross-sectional view of a general transverse electric field type liquid crystal display device.

As shown in the figure, the upper substrate 9, which is a color filter substrate, and the lower substrate 10, which is an array substrate, are spaced apart from each other and face each other. A liquid crystal layer 11 is interposed between the upper and lower substrates 9, .

The common electrode 17 and the pixel electrode 30 are formed on the same plane on the lower substrate 10 and the liquid crystal layer 11 is formed by the common electrode 17 and the pixel electrode 30 And is operated by the horizontal electric field (L).

2A and 2B are cross-sectional views respectively showing the on and off states of a general transverse electric field type liquid crystal display device.

2A showing the alignment state of the liquid crystal in the ON state to which the voltage is applied, the phase of the liquid crystal 11a at the position corresponding to the common electrode 17 and the pixel electrode 30 is The liquid crystal 11b located between the common electrode 17 and the pixel electrode 30 is formed by a horizontal electric field L formed by applying a voltage between the common electrode 17 and the pixel electrode 30, And arranged in the same direction as the horizontal electric field (L). That is, since the liquid crystal is moved by the horizontal electric field in the transverse electric field type liquid crystal display device, the viewing angle becomes wide.

Therefore, when viewed from the front, the transverse electric-field-type liquid-crystal display device can be visually seen in the direction of about 80 to 85 degrees in the up / down / left / right direction without reversal.

Next, referring to FIG. 2B, a horizontal electric field is not formed between the common electrode and the pixel electrode since the liquid crystal display device is in an off state in which no voltage is applied, so that the alignment state of the liquid crystal layer 11 is not changed.

However, such a transverse electric field type liquid crystal display device has the advantage of improving the viewing angle, but has a disadvantage in that the aperture ratio and transmittance are low.

Therefore, a fringe field switching mode LCD has been proposed in which liquid crystal operates by a fringe field in order to realize the disadvantage of such a transverse electric field type liquid crystal display device.

3 is a cross-sectional view of a portion of a conventional fringe field switching mode liquid crystal display device substrate cut through a central portion of one pixel region.

As shown in the figure, a plurality of pixel regions (not shown) are defined on the array substrate 41 for the conventional fringe field switching mode liquid crystal display through the gate insulating film 45, (Not shown) and a data line 47 are formed in the pixel region (not shown), and thin film transistors (not shown) are connected to the gate and data lines (not shown)

In addition, a plate-shaped pixel electrode 55 is formed on each of the pixel regions (not shown) on the gate insulating film 45 in contact with drain electrodes (not shown) of the thin film transistors. The pixel electrode 55 is formed on the same layer as the data line 47, that is, on the gate insulating layer 45, and the data line 47 ) And a predetermined distance from each other.

A protection layer 60 is formed on the entire surface of the data line 47 and the pixel electrode 55 as an inorganic insulating material and is formed over the protection layer 60 to correspond to each pixel region A common electrode 65 having a plurality of openings op, which are spaced apart from each other by a predetermined distance and have a bar shape, is formed.

Since the array substrate 41 for a conventional fringe field switching mode liquid crystal display having such a sectional configuration has a structure in which the common electrode 65 is located at the top and is formed on the entire surface of the display region, The common electrode 65 is formed so as to overlap with the protective layer 60 interposed therebetween.

Therefore, the data line 47, the protective layer 60, and the common electrode 67, which overlap each other, form a parasitic capacitor. In order to perform the pulse-field switching driving in consideration of the influence on the parasitic capacitor, The layer 60 is formed to have a thickness of at least 6000A.

In this case, since the spacing distance between the common electrode 67 and the pixel electrode 55 is at least about 6000 ANGSTROM, the driving voltage for forming the fringe field for liquid crystal driving that maintains proper display quality is relatively large, Power is increasing.

In the conventional fringe field switching mode LCD device array substrate 41 having such a configuration, if the driving voltage is lowered, the transmittance is decreased, and the contrast ratio is lowered, resulting in a problem that the display quality is lowered.

When the protective layer 60 is formed to have a thickness smaller than about 6000 ANGSTROM, the distance between the common electrode 65 and the data line 47 is reduced, and the parasitic capacitance due to these elements increases, It is a reality.

SUMMARY OF THE INVENTION It is an object of the present invention to overcome the disadvantages of the conventional array substrate for a fringe field switching mode liquid crystal display device and to reduce the thickness of a protective layer interposed between the pixel electrode and the common electrode, And it is an object of the present invention to provide an array substrate for a fringe field switching mode liquid crystal display device capable of increasing fringe field intensity and minimizing a parasitic capacitance between a data line and a common electrode, thereby reducing power consumption.

According to an aspect of the present invention, there is provided an array substrate for a fringe field switching mode liquid crystal display, including: a gate wiring formed on a transparent substrate in one direction; A gate insulating film formed on the gate wiring; A data line crossing the gate line perpendicularly to the gate insulating layer and defining a pixel region; A thin film transistor electrically connected to the gate wiring and the data wiring and formed near the intersection of the two wirings; A pixel electrode formed on the gate insulating film in contact with the drain electrode of the thin film transistor and formed in the pixel region; A first protective layer formed on the entire surface of the substrate over the pixel electrode, the first protective layer having a first thickness as a first inorganic insulating material; A second passivation layer formed on the first passivation layer and having a first opening corresponding to the pixel region as a second inorganic insulating material and having a second thickness completely overlapping the gate and the data line at the boundary of each pixel region, ; And a plurality of second openings exposing the first protective layer in a bar shape spaced apart from the second protective layer by a predetermined distance corresponding to each pixel region on the first protective layer exposed outside of the second protective layer, Wherein the first and second protective layers provided between the data line and the common electrode formed on the data line have a thickness greater than 6000A and the first thickness is 1000A to 4000A.

At this time, the first inorganic insulating material is silicon nitride (SiNx), and the second inorganic insulating material is silicon oxide (SiO ₂ ).

Also, the second thickness is preferably 2000 Å to 6000 Å.

The common electrode is characterized in that a third opening is formed in correspondence with the thin film transistor.

A method of fabricating an array substrate for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention includes: forming gate wirings extending in one direction on a transparent substrate; Forming a gate insulating film on the entire surface of the substrate over the gate wiring; Forming a data line crossing over the gate insulating film and defining a pixel region over the gate insulating film; Forming a thin film transistor electrically connected to the gate wiring and the data wiring and near the intersection of the two wiring lines; Forming a plate-shaped pixel electrode on the gate insulating film in contact with the drain electrode of the thin film transistor for each pixel region; Depositing a first inorganic insulating material on the entire surface of the substrate over the data line and the pixel electrode to form a first protective layer having a first thickness and continuously depositing a second inorganic insulating material on the first protective layer, Forming an inorganic insulating layer on the substrate; The first dry etching process using the first reaction gas that does not react with the first protective layer is performed so that the inorganic insulating layer is removed so that the first passivation layer and the first passivation layer are formed over the first passivation layer, Forming a second protective layer having a first opening exposing the gate electrode and the data line and completely overlapping the gate and the data line over the first protective layer in correspondence with the boundary of each pixel region; A common electrode is formed on the entire surface of the display region on the first passivation layer exposed to the outside of the second passivation layer, and a plurality of second openings having a bar shape and being spaced apart from each other by a predetermined distance Wherein the first and second protective layers provided between the data line and the common electrode formed on the data line have a thickness greater than 6000A and the first thickness has a value less than 6000A .

At this time, after the step of forming the common electrode having the plurality of second openings, the first dry etching proceeds to remove the first protective layer exposed through the second opening of the common electrode, Thereby forming a hole for exposing one pixel electrode.

The first inorganic insulating material may be silicon nitride (SiNx), the second inorganic insulating material may be silicon oxide (SiO2), silicon oxide ₂ ).

In addition, the step of forming the common electrode having the plurality of second openings includes forming a third opening corresponding to the thin film transistor to expose the second protective layer.

In the array substrate for a fringe field switching mode liquid crystal display according to the present invention, a double-layered protective layer having a thickness of 6000 ANGSTROM or more is formed between the data line and the common electrode, and a thickness of less than 6000 ANGSTROM is formed between the common electrode and the pixel electrode. A protective layer having a single layer structure is formed, thereby improving the fringe field strength between the pixel electrode and the common electrode, thereby reducing the driving voltage.

In addition, there is an effect of reducing power consumption by reducing the driving voltage.

In addition, the spacing between the pixel electrode and the common electrode in each pixel region is smaller than that in the prior art, thereby improving the capacity of the storage capacitor formed of the pixel electrode, the common electrode, and the first protective layer interposed between the two electrodes. .

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

4 is a plan view of one pixel region of an array substrate for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention. A region where a plurality of pixel regions P are formed is defined as a display region and a region outside the display region is defined as a non-display region, and a region where the thin film transistor Tr is formed is referred to as an element region .

As shown in the drawing, a plurality of gate wirings 105 are formed in the display region in the first direction and extend in a second direction orthogonal to the first direction. In addition to the gate wirings 105, A plurality of data lines 130 defining regions P are formed.

The gate electrode 108 and the gate electrode 108 are connected to the gate wiring 105 and the data wiring 130 at the boundary of each pixel region P or corresponding to the plurality of pixel regions P, A semiconductor layer (not shown) composed of an insulating film (not shown), an active layer of pure amorphous silicon (not shown) and an ohmic contact layer (not shown) of impurity amorphous silicon and source and drain electrodes 133 and 136 ) Is formed on the surface of the thin film transistor Tr.

In this case, although the separation region (hereinafter, referred to as a channel region) between the source and drain electrodes 133 and 136 is shown as an example in the figure, the shape of the channel region may be changed into various shapes have. For example, when the drain electrode 136 is formed in the form of a U-shaped source electrode 133 and inserted into the opening of the U-shaped source electrode 133, the channel region may include a U- Form.

Although it is shown in the drawing that the thin film transistor Tr is formed in the boundary of the pixel region P and a part of the pixel region P, the semiconductor layer (not shown) and the source and drain electrodes 133 and 136 May be formed so as to completely overlap the gate line 105, thereby forming a structure at the boundary of each pixel region P, thereby improving the aperture ratio.

On the other hand, the pixel electrode 138 is formed in contact with the drain electrode of the thin film transistor Tr.

A first passivation layer (not shown) formed of a first inorganic insulating material and having a first thickness is formed on the entire surface of the substrate 101, A second passivation layer 143 having a second thickness made of a second inorganic insulating material corresponding to the boundary of each pixel region P and the device region TrA is formed on a protection layer (not shown) . Here, the second passivation layer 143 has a first opening op1 exposing the first passivation layer (not shown) corresponding to the pixel region P.

 (Not shown) spaced apart from the first protective layer (not shown) through the second protective layer 143 and the first opening op1 and corresponding to the pixel regions P (Not shown) having a plurality of second openings op2 in the form of a first opening (op2) and a third opening op3 corresponding to the device region TrA.

Since the characteristic structure of the present invention can be well expressed by the sectional structure, the sectional structure of the array substrate 101 for a fringe field switching mode liquid crystal display according to the above-described embodiment will be described in detail below do.

5 is a cross-sectional view of the portion cut along line V-V in Fig. For convenience of explanation, the portion where the thin film transistor which is the switching element is formed is defined as the element region TrA.

As shown in the figure, on a transparent insulating substrate 101 forming a base of an array substrate 101 for a fringe field switching mode liquid crystal display according to an embodiment of the present invention, a metal material having low resistance characteristics, for example, aluminum (Al Gate interconnections (not shown) extending in one direction are formed as one metal material selected from the group consisting of aluminum (AlNd), copper (Cu), copper alloy, chromium (Cr), and molybdenum (Mo) A gate electrode 108 is formed in the element region TrA in connection with the gate wiring.

A gate insulating film 115 made of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is formed on the entire surface of the substrate 101 over the gate wiring 105 and the gate electrode 108 have.

A semiconductor layer 120 composed of an active layer 120a of pure amorphous silicon and an ohmic contact layer 120b of impurity amorphous silicon corresponding to the gate electrode 108 is formed in the device region TrA above the gate insulating film 115 And source and drain electrodes 133 and 136 are formed on the semiconductor layer 120 and are spaced apart from each other. At this time, the active layer 120a is exposed between the source and drain electrodes 133 and 136 which are spaced apart from each other.

A data line 130 is formed on the gate insulating layer 115 to define a pixel region P intersecting the gate line 105 at the boundary of each pixel region. At this time, the data line is connected to the source electrode 133 of the thin film transistor Tr.

Although the first and second dummy patterns 121a and 121b made of the same material as the semiconductor layer 120 are formed under the data line 130 in the drawing, The second dummy patterns 121a and 121b are caused by the manufacturing method and can be omitted.

Next, a plate-shaped pixel electrode 138, which is in direct contact with one end of the drain electrode and is made of a transparent conductive material, is formed on the gate insulating layer 115 in each pixel region P.

On the entire surface of the thin film transistor Tr and the pixel electrode 138, a first passivation layer having a first thickness of 1000 ANGSTROM to 4000 ANGSTROM and made of a first inorganic insulating material such as silicon nitride (SiNx) 140 are formed.

On the first passivation layer 140 made of silicon nitride (SiNx), the data line 130 and the device region TrA are formed in the boundary of the pixel region P, And has a larger width than the first insulating material 130 and has a second thickness of about 2000 Å to 6000 Å in a state of completely overlapping with the data line 130, and has a larger dielectric constant than the first inorganic insulating material, A second protective layer 143 made of silicon oxide (SiO ₂ ) is formed.

At this time, the first and second protective layers 140 and 143, which are sequentially stacked on the data line 130 at the boundary of the pixel region P, have a total thickness of 6000 Å or more. That is, if the first protective layer has a thickness of about 1000 Å, the second protective layer has a thickness of about 5000 Å to 6000 Å. If the first protective layer has a thickness of about 4000 Å, The distance between the data line and the common electrode in the vertical direction is about 6000 ANGSTROM or more.

The second passivation layer 143 is formed in correspondence with the boundary of the pixel region P and the device region TrA by the above-described structure, so that the second passivation layer 143 is formed on the entire surface of the substrate 101 And has a first opening (op1) for exposing the first protective layer (140).

Next, over the first passivation layer 140 exposed through the second passivation layer 143 and the first opening op1, a transparent conductive material is deposited on the entire surface of the display region at a predetermined interval A common electrode 160 having a plurality of second openings op2 in the form of a bar spaced apart is formed.

At this time, the pixel electrode 138, the common electrode 160, and the first passivation layer 140 interposed between the two pixel electrodes 138, 138 and 160 constitute a storage capacitor.

The array substrate 101 for a fringe field switching mode liquid crystal display according to an embodiment of the present invention having the above-described structure is formed between the pixel electrode 138 and the common electrode 160 within each pixel region P, Only the first passivation layer 140 having a first thickness of 4000 ANGSTROM is formed. The array substrate 101 for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention has a structure in which the thickness of the single layer is less than 6000 A in order to reduce the influence of the parasitic capacitance between the common electrode and the data line to a proper level, The spacing in the vertical direction between the pixel electrode and the common electrode is reduced as compared with the conventional array substrate for the fringe field switching mode liquid crystal display device forming the protective layer of the fringe field switching mode liquid crystal display device, It can be seen that the intensity becomes relatively large compared to the conventional case when the same driving voltage is applied. Therefore, when the fringe field strength is the same as the conventional one, the driving voltage can be lowered and the power consumption can be further reduced.

The common electrode 160 may include a second protection layer 143 corresponding to the thin film transistor Tr corresponding to the device region TrA in addition to the second openings op2 of the bar shape, And a third opening (op3) exposing the second opening (op3). This is to minimize the influence on the channel region and minimize the parasitic capacitance generated by overlapping with the source and drain electrodes 133 and 136. [

Particularly, the common electrode 160 is removed so as to have the third opening op3 in correspondence with the spacing between the source and drain electrodes 133 and 136 in which the channel is formed in the thin film transistor Tr desirable. This is to prevent the common electrode 160 from affecting the characteristics of the thin film transistor by affecting the flow characteristics of carriers such as electrons or holes moving through the channel formed in the active layer 120a.

The first and second protective layers 140 and 143 are formed between the data line 130 and the common electrode 160. The first and second protective layers 140 and 143 The thickness is more than 6000A. Therefore, it can be seen that the parasitic capacitance generated by the data line 130 and the common electrode 160 overlapping each other becomes the same level as the conventional one.

The array substrate 101 for a fringe field switching mode liquid crystal display device according to the present invention having the above-described structure has a spacing distance between the pixel electrode 138 and the common electrode 160 within each pixel region P So that the capacitance of the storage capacitor formed by the two electrodes 138 and 160 and the first passivation layer 140 is further enhanced.

Meanwhile, FIG. 6 is a graph showing the transmittance according to the driving voltage change according to the thickness of the protective layer located between the pixel electrode and the common electrode. At this time, the graph shows that the thickness of the protective layer is 6000 Å (the minimum protective layer thickness required in the conventional fringe field switching mode LCD device array substrate) and 1000 Å (the fringe field switching mode liquid crystal display The minimum protective layer thickness that the array substrate can have).

As shown in the figure, when the gap between the pixel electrode and the common electrode (the thickness of the protective layer) is 6000 ANGSTROM, the maximum transmittance is obtained when a driving voltage of about 4 V is applied. However, When the distance between the electrodes and the common electrode is 1000 Å, for example, the maximum transmittance is obtained when a driving voltage of about 2.9 V is applied.

The driving voltage of the array substrate for a fringe field switching mode liquid crystal display according to an embodiment of the present invention in which only the first protective layer having a first thickness of about 1000 Å to 4000 Å is formed between the pixel electrode and the common electrode, Is significantly lower than that of the conventional array substrate for a fringe field switching mode liquid crystal display.

When the driving voltage for forming the fringe field between the pixel electrode and the common electrode is lowered, the power consumption can be reduced. Therefore, when the driving voltage is applied to an application such as a notebook computer or a mobile phone, the use time of the device can be improved.

7 is a cross-sectional view of one pixel region of an array substrate for a fringe field switching mode liquid crystal display according to a modification of the embodiment of the present invention. In the modification example, only the configuration different from the embodiment will be described briefly. The same reference numerals are given to the same constituent elements as those of the embodiment.

As shown in the drawing, the modification is characterized in that the intensity of the fringe field between the pixel electrode and the common electrode can be further improved when a driving voltage of the same magnitude is applied.

That is, the first passivation layer 140 is removed corresponding to each of the plurality of bar-shaped second openings op2 of the common electrode 160 to expose the pixel electrode, Is provided.

The common electrode 160 and the first passivation layer 140 are formed in such a manner that the hole h1 exposes the pixel electrode corresponding to the second opening op2, 138 to increase the intensity of the fringe field. That is, the first passivation layer 140 having a first thickness of about 1000 Å to about 4000 Å, which corresponds to the plurality of second openings op2 of the common electrode 160, The fringe field intensity formed between the common electrode 160 and the pixel electrode 138 through each of the plurality of second openings op2 can be increased. Accordingly, since a part of the material layer (the first protective layer 140) that interferes with fringe field formation is removed, a fringe field having a higher intensity for the same drive voltage application is formed, The driving voltage can be further lowered.

Hereinafter, a method of manufacturing an array substrate for a fringe field switching mode liquid crystal display according to an embodiment and a modification of the present invention having the above-described structural features will be described. In the modification example, the steps up to the step of forming the common electrode are the same as those of the embodiment, and thus only the embodiment will be mainly described and only the different parts will be described briefly.

8A to 8J are cross-sectional views illustrating steps of manufacturing an array substrate for a fringe field switching mode liquid crystal display according to an embodiment of the present invention. Here, for convenience of description, a region where the thin film transistor Tr is formed in each pixel region P is defined as an element region TrA.

First, as shown in FIG. 8A, a first metal material having a low resistance property, such as aluminum (Al), an aluminum alloy (AlNd), copper (Cu), a copper alloy, A first metal layer (not shown) is formed by depositing a selected material of chromium (Cr), molybdenum (Mo), and then a photoresist is applied successively, exposure is performed using a photomask, development of the exposed photoresist, A plurality of gate wirings 105 (not shown) extending in a first direction are formed by patterning the first metal layer (not shown) by performing a mask process including a series of unit processes such as etching And a gate electrode 108 connected to the gate wiring (not shown) is formed in the device region TrA.

Next, as shown in FIG. 8B, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the gate wiring 105 and the gate electrode 108, A gate insulating film 115 is formed.

Next, as shown in FIG. 8C, a pure amorphous silicon layer (not shown) and an impurity amorphous silicon layer (not shown) are formed on the gate insulating layer 115, A second metal layer (not shown) is formed by depositing one of two metal materials, for example, aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), copper (Cu) and copper alloy. Thereafter, a photoresist layer (not shown) is formed on the second metal layer (not shown), a first photoresist pattern 191a having a third thickness is formed by performing halftone exposure or diffraction exposure, A second photoresist pattern 191b having a fourth thickness thinner than the third thickness is formed.

Next, the second metal layer (not shown) exposed to the outside of the first and second photoresist patterns 191a and 191b and the impurities and pure amorphous silicon layer (not shown) below the second metal layer are etched and removed, (Not shown) extending in a second direction to define a data line 130 defining a pixel region P, and at the same time, forming a source / drain pattern (not shown) connected to the data line 130 in the device region TrA, The ohmic contact pattern 118 and the active layer 120a are sequentially formed on the substrate 129 and the lower portion thereof.

  Next, as shown in FIG. 8D, ashing is performed to remove the second photoresist pattern (191b in FIG. 8C) having the fifth thickness. At this time, the first photoresist pattern (191a in FIG. 8C) having the third thickness is also reduced in thickness by the ashing, but is still left on the substrate 101.

Thereafter, the center portion of the source drain pattern (129 in FIG. 8C) exposed by removing the second photoresist pattern (191b in FIG. 8C) is removed by etching, and the ohmic contact layer The source and drain electrodes 133 and 136 are spaced apart from each other by dry etching to remove the contact pattern 118. The active layer 120a is formed below the source and drain electrodes 133 and 136, Is formed on the ohmic contact layer 120b. The active layer 120a and the ohmic contact layer 120b constitute a semiconductor layer 120. The gate electrode 108, the gate insulating layer 115, and the semiconductor layer 120, which are sequentially stacked in the device region TrA, 120, and the source and drain electrodes 133, 136 spaced apart from each other constitute a thin film transistor Tr.

The semiconductor layer 120 and the data line 130 and the source and drain electrodes 133 and 136 are simultaneously formed through a single mask process so that the semiconductor The first and second dummy patterns 121a and 121b are formed of the same material forming the layer 120. The semiconductor layer 120 and the data line 130 and the source and drain electrodes 133 and 133, The first and second dummy patterns 121a and 121b made of a semiconductor material may not be formed under the data line 130. In this case,

Next, as shown in FIG. 8E, the first photoresist pattern (191a in FIG. 8D) remaining on the data line 130 and the source and drain electrodes 133 and 136 is stripped .

8F, a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) is deposited on the gate insulating film 115 on the entire surface of the substrate 101 And a pixel electrode 138 is formed in each pixel region P so as to be in direct contact with the drain electrode 136 of the thin film transistor Tr.

Next, as shown in FIG. 8G, a first inorganic insulating material such as silicon nitride (SiNx) is formed over the entire surface of the thin film transistor Tr, the data line 130, and the pixel electrode 138, 1 < / RTI > thickness.

Then, a second inorganic insulating material such as silicon oxide (SiO ₂ ) is deposited on the first passivation layer 140 so as to have a selective ratio with the first inorganic insulating material and is hardly affected by dry etching. An inorganic insulating layer 142 having a second thickness of about 2 nm is formed.

At this time, the first passivation layer 140 and the inorganic insulating layer 142 are formed through a chemical vapor deposition (CVD) apparatus (not shown). Accordingly, the two layers 140 and 142 are formed continuously by changing only the reactive gas injected into the chamber (not shown) of the chemical vapor deposition (CVD) equipment (not shown).

Thereafter, a photoresist is coated on the inorganic insulating layer 142, exposure and development are performed thereon to form a third photoresist pattern 193 corresponding to the boundary of the pixel region P and the device region TrA .

Next, as shown in FIG. 8H, the inorganic insulating layer (142 in FIG. 8G) exposed outside the third photoresist pattern 193 is removed by dry etching to form the pixel region P The second protective layer 143 having a first opening op1 exposing the first protective layer 140 is formed. At this time, the second protective layer 143 has a width wider than that of the two wirings (not shown) 130, corresponding to the boundaries of the pixel region P, that is, the gates and the data lines (not shown) And is formed corresponding to the device region TrA.

Meanwhile, the first reaction gas for removing the inorganic insulating layer (145 in FIG. 8G) during the dry etching is formed on the second protection layer 140, which is exposed through the first opening op1, There is no problem that the first protective layer 140 is removed because the insulating material has little influence due to a very large selection ratio difference. Therefore, even after the dry etching process, the first passivation layer 140 exposed through the first opening op1 still maintains the first thickness.

Accordingly, the first and second protective layers 140 and 143 having the first and second thicknesses are sequentially formed on the data line 130 by the dry etching process described above to have a thickness of 6000 Å or more, And only the first passivation layer 140 having the first thickness is formed in the pixel region P. In this case,

Next, as shown in FIG. 8I, a third photoresist pattern (193 in FIG. 8H) remaining on the second passivation layer 143 is stripped and removed.

Next, as shown in FIG. 8J, the third protective layer 143 exposed by removing the third photoresist pattern 193 (FIG. 8H) and the first passivation layer 140 exposed to the outside outside A transparent conductive material layer (not shown) is formed by depositing a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).

Thereafter, the transparent conductive material layer (not shown) is patterned by performing a masking process to form a plurality of second openings op2 having a bar shape spaced apart from each other by a predetermined distance corresponding to each pixel region P And a third opening op3 exposing the thin film transistor Tr including a spacing region between the source and drain electrodes 133 and 136 corresponding to the device region TrA To complete the array substrate 101 for a fringe field switching mode liquid crystal display. At this time, the second passivation layer 143 is exposed for the third opening op3, and the first passivation layer 140 is exposed for the plurality of second openings op2.

On the other hand, in the case of a modification of the embodiment of the present invention, referring to FIG. 9 (a process sectional view of a part of manufacturing steps for one pixel region of an array substrate for a fringe field switching mode liquid crystal display according to a modification of the embodiment of the present invention) After the above-described step, the second dry etching is performed using the second reaction gas that reacts with the first inorganic insulating material forming the first protective layer 140 to expose the second openings op2 through the plurality of second openings op2 The first passivation layer 140 may be removed to form the plurality of holes hl for exposing the pixel electrodes 138. [ At this time, the plurality of second openings op2 and the plurality of holes h1 are completely overlapped, and in the case of the second protective layer 143 exposed through the third opening op3, Since the second reaction gas does not react at all with respect to the second reaction gas, the hole hl is not formed and the second protection layer 143 is exposed through the third opening op3 as it is Feature.

Since the second dry etching proceeds using the common electrode 160 as an etching mask, it is unnecessary to perform a mask process for forming a separate etching mask to prevent the etching from progressing. The transparent conductive material forming the common electrode 160 is not affected by dry etching at all.

The present invention is not limited to the above-described embodiments and modifications, and various changes and modifications can be made without departing from the spirit of the present invention.

1 is a cross-sectional view schematically showing a part of a general transverse electric field type liquid crystal display device.

FIGS. 2A and 2B are cross-sectional views respectively showing the on and off states of a general transverse electric field liquid crystal display device;

3 is a cross-sectional view of one pixel region of an array substrate of a conventional fringe field switching mode liquid crystal display.

4 is a plan view of one pixel region of an array substrate for a fringe field switching mode liquid crystal display according to an embodiment of the present invention.

5 is a cross-sectional view of a portion cut along line V-V in Fig. 4; Fig.

6 is a graph showing transmittance according to a driving voltage change according to a thickness of a protective layer located between a pixel electrode and a common electrode.

7 is a cross-sectional view of one pixel region of an array substrate for a fringe field switching mode liquid crystal display according to a modification of the embodiment of the present invention.

8A to 8J are cross-sectional views illustrating an array substrate for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 9 is a process sectional view of a part of manufacturing steps for one pixel region of an array substrate for a fringe field switching mode liquid crystal display according to a modification of the embodiment of the present invention. FIG.

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

101: array substrate 108: gate electrode

115: gate insulating film 120: semiconductor layer

120a: active layer 120b: ohmic contact layer

121a and 121b: first and second dummy patterns

130: data line 133: source electrode

136: drain electrode 138: pixel electrode

140: first protective layer 143: second protective layer

160: common electrode

op1, op2, op3: first, second and third openings

P: pixel region Tr: thin film transistor

TrA: device region

Claims (11)

A gate wiring extending in one direction on a transparent substrate; A gate insulating film on the gate wiring; A data line crossing the gate line above the gate insulating layer and defining a pixel region; A thin film transistor which is electrically connected to the gate wiring and the data wiring and is located near the intersection of the two wiring; A pixel electrode in the form of a plate disposed on the gate insulating film and in contact with an upper surface and a side surface of a drain electrode of the TFT; A first protective layer having a first thickness as a first inorganic insulating material on the substrate over the plate-shaped pixel electrode; A second passivation layer having a first opening corresponding to the pixel region as a second inorganic insulating material over the first passivation layer and completely overlapping the gate and the data line at a boundary of each pixel region, ; A plurality of second openings are formed on the first passivation layer exposed to the outside of the second passivation layer and the second passivation layer and having a bar shape spaced apart from each other by a predetermined distance corresponding to each pixel region, Type pixel electrode and a common electrode / RTI > Wherein the first protective layer includes a hole corresponding to the second opening and exposing the plate-shaped pixel electrode under the first protective layer, The pixel electrode Wherein an edge of the common electrode overlaps with an edge of the first passivation layer, and the second opening and the hole completely overlap each other. The method according to claim 1, Wherein the first inorganic insulating material is silicon nitride (SiNx) and the second inorganic insulating material is silicon oxide (SiO ₂ ). The method according to claim 1, Wherein the second thickness is 2000 to 6000 ANGSTROM for a fringe field switching mode liquid crystal display. The method according to claim 1, And the common electrode includes a third opening corresponding to the thin film transistor. Forming a gate wiring in one direction on a transparent substrate; Forming a gate insulating film on the entire surface of the substrate over the gate wiring; Forming a data line crossing over the gate insulating film and defining a pixel region over the gate insulating film; Forming a thin film transistor electrically connected to the gate wiring and the data wiring and near the intersection of the two wiring lines; Forming a plate-shaped pixel electrode on the gate insulating film, the plate-shaped pixel electrode being in contact with an upper surface and a side surface of the drain electrode of each thin film transistor in each pixel region; Depositing a first inorganic insulating material on the entire surface of the substrate over the data line and the plate-shaped pixel electrode to form a first protective layer having a first thickness, continuously depositing a second inorganic insulating material on the first protective layer Thereby forming an inorganic insulating layer having a second thickness; The first dry etching using the first reaction gas which does not react with the first protective layer is performed so that the inorganic insulating layer is removed, so that the first protection layer, the first protection layer, Forming a second passivation layer having a first opening exposing the layer and completely overlapping the gate and the data line over the first passivation layer corresponding to the boundary of each pixel region; And a plurality of second openings formed on the entire surface of the display region on the first passivation layer exposed outside of the second passivation layer and spaced apart from each other by a predetermined distance corresponding to the pixel regions, A step of forming a common electrode overlapping the pixel electrode of / RTI > The method of claim 1, wherein the step of forming the common electrode having the plurality of second openings comprises: forming a common electrode on the common electrode, Forming a hole for exposing the plate-shaped pixel electrode under the first passivation layer, The pixel electrode Wherein the edge of the common electrode overlaps the edge of the first passivation layer and the second opening and the hole are completely overlapped with each other. delete 6. The method of claim 5, Wherein the first thickness is about 1000 Å to about 4000 Å and the second thickness is about 2000 Å to about 6000 Å. 6. The method of claim 5, Wherein the first inorganic insulating material is silicon nitride (SiNx), and the second inorganic insulating material is silicon oxide (SiO ₂ ). 6. The method of claim 5, Wherein forming the common electrode having the plurality of second openings includes forming a third opening corresponding to the thin film transistor to expose the second passivation layer. Gt; 6. The method of claim 5, Wherein the first and second protective layers provided between the data line and the common electrode formed on the data line have a thickness greater than 6000A or 6000A and the first thickness is less than 6000A, A method of manufacturing an array substrate for a display device. The method according to claim 1, Wherein the first and second protective layers provided between the data line and the common electrode formed on the data line have a thickness greater than 6000A or 6000A and the first thickness ranges from 1000A to 4000A for a fringe field switching mode liquid crystal display Board.

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