KR101694151B1 - Array substrate for fringe field switching mode liquid crystal display device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a fringe field switching mode liquid crystal display device capable of reducing power consumption.

The present invention further includes an etch stopper corresponding to a pixel region above the first passivation layer covering the thin film transistor, and a second passivation layer on the top of the etch stopper.

At this time, the common electrode includes a plurality of first openings in the form of a bar, and the second protective layer includes a groove corresponding to the first opening.

Accordingly, a double-layered protective layer having a thickness of 6000 ANGSTROM or more is formed between the data line and the common electrode, and a groove is formed between the common electrode and the pixel electrode to remove the first protective layer, thereby improving the fringe field strength There is an effect of reducing the driving voltage.

There is an effect of reducing power consumption by reducing the driving voltage.

Fringe field, liquid crystal display, driving voltage, array substrate

Description

[0001] The present invention relates to an array substrate for a fringe field switching mode liquid crystal display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a fringe field switching mode liquid crystal display device capable of reducing power consumption.

In general, a liquid crystal display device is driven by using optical anisotropy and polarization properties of a liquid crystal. Since the liquid crystal has a long structure, it has a directionality in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal by optical anisotropy, so that image information can be expressed.

At present, an active matrix liquid crystal display (AM-LCD) having a thin film transistor and a pixel electrode connected to the thin film transistor arranged in a matrix manner has excellent resolution and moving picture performance It is attracting attention.

The liquid crystal display device includes a color filter substrate on which a common electrode is formed, an array substrate on which pixel electrodes are formed, and a liquid crystal interposed between the two substrates. In such a liquid crystal display device, The liquid crystal is driven to have excellent properties such as transmittance and aperture ratio.

However, liquid crystal driving by an electric field that is applied up and down has a drawback that the viewing angle characteristic is not excellent.

Therefore, a transverse electric field type liquid crystal display device having excellent viewing angle characteristics has been proposed to overcome the above disadvantages.

Hereinafter, a general transverse electric field type liquid crystal display device will be described in detail with reference to FIG.

1 is a cross-sectional view of a general transverse electric field type liquid crystal display device.

As shown in the figure, the upper substrate 9, which is a color filter substrate, and the lower substrate 10, which is an array substrate, are spaced apart from each other and face each other. A liquid crystal layer 11 is interposed between the upper and lower substrates 9, .

The common electrode 17 and the pixel electrode 30 are formed on the same plane on the lower substrate 10 and the liquid crystal layer 11 is formed by the common electrode 17 and the pixel electrode 30 And is operated by the horizontal electric field (L).

2A and 2B are cross-sectional views respectively showing the on and off states of a general transverse electric field type liquid crystal display device.

2A showing the alignment state of the liquid crystal in the ON state to which the voltage is applied, the phase of the liquid crystal 11a at the position corresponding to the common electrode 17 and the pixel electrode 30 is The liquid crystal 11b located between the common electrode 17 and the pixel electrode 30 is formed by a horizontal electric field L formed by applying a voltage between the common electrode 17 and the pixel electrode 30, And arranged in the same direction as the horizontal electric field (L). That is, since the liquid crystal is moved by the horizontal electric field in the transverse electric field type liquid crystal display device, the viewing angle becomes wide.

Therefore, when viewed from the front, the transverse electric-field-type liquid-crystal display device can be visually seen in the direction of about 80 to 85 degrees in the up / down / left / right direction without reversal.

Next, referring to FIG. 2B, a horizontal electric field is not formed between the common electrode and the pixel electrode since the liquid crystal display device is in an off state in which no voltage is applied, so that the alignment state of the liquid crystal layer 11 is not changed.

However, such a transverse electric field type liquid crystal display device has the advantage of improving the viewing angle, but has a disadvantage in that the aperture ratio and transmittance are low.

Therefore, a fringe field switching mode LCD has been proposed in which liquid crystal operates by a fringe field in order to realize the disadvantage of such a transverse electric field type liquid crystal display device.

3 is a cross-sectional view of a portion of a conventional fringe field switching mode liquid crystal display device substrate cut through a central portion of one pixel region.

As shown in the figure, a plurality of pixel regions (not shown) are defined on the array substrate 41 for the conventional fringe field switching mode liquid crystal display through the gate insulating film 45, (Not shown) and a data line 47 are formed in the pixel region (not shown), and thin film transistors (not shown) are connected to the gate and data lines (not shown)

In addition, a plate-shaped pixel electrode 55 is formed on each of the pixel regions (not shown) on the gate insulating film 45 in contact with drain electrodes (not shown) of the thin film transistors. The pixel electrode 55 is formed on the same layer as the data line 47, that is, on the gate insulating layer 45, and the data line 47 ) And a predetermined distance from each other.

A protection layer 60 is formed on the entire surface of the data line 47 and the pixel electrode 55 as an inorganic insulating material and is formed over the protection layer 60 to correspond to each pixel region A common electrode 65 having a plurality of openings oa spaced apart from each other and having a bar shape is formed.

Since the array substrate 41 for a conventional fringe field switching mode liquid crystal display having such a sectional configuration has a structure in which the common electrode 65 is located at the top and is formed on the entire surface of the display region, The common electrode 65 is formed so as to overlap with the protective layer 60 interposed therebetween.

Accordingly, the data line 47, the protective layer 60, and the common electrode 67 overlapping each other form a parasitic capacitor. In order to perform the fringe field switching drive in consideration of the influence on the parasitic capacitor, Is formed with a thickness of at least 6000A.

In this case, since the interval between the common electrode and the pixel electrode is at least about 6000 ANGSTROM, the driving voltage for forming the fringe field for the liquid crystal driving that maintains proper display quality is relatively large, and the power consumption is finally increased.

In a conventional array substrate for a fringe field switching mode liquid crystal display device having such a configuration, when the driving voltage is lowered, the transmittance is reduced and the contrast ratio is lowered, resulting in a problem that the display quality is lowered.

In addition, when the protective layer is formed to have a thickness smaller than about 6000 ANGSTROM, the distance between the common electrode and the data line is reduced. As a result, the parasitic capacitance due to these components increases and the power consumption is further increased.

SUMMARY OF THE INVENTION It is an object of the present invention to overcome the disadvantages of the conventional array substrate for a fringe field switching mode liquid crystal display device and to reduce the thickness of a protective layer interposed between the pixel electrode and the common electrode, And it is an object of the present invention to provide an array substrate for a fringe field switching mode liquid crystal display device capable of increasing fringe field intensity and minimizing a parasitic capacitance between a data line and a common electrode, thereby reducing power consumption.

According to an aspect of the present invention, there is provided an array substrate for a fringe field switching mode liquid crystal display, including: a gate wiring formed on a transparent substrate in one direction; A gate insulating film formed on the gate wiring; A data line crossing the gate line perpendicularly to the gate insulating layer and defining a pixel region; A thin film transistor electrically connected to the gate wiring and the data wiring and formed near the intersection of the two wirings; A pixel electrode formed on the gate insulating film in contact with the drain electrode of the thin film transistor and formed in the pixel region; A first protective layer formed on the entire surface of the substrate over the pixel electrode, the first protective layer having a first thickness; An etch stopper formed in each pixel region above the first passivation layer; A second protective layer formed on the entire surface of the substrate over the etch stopper to have a second thickness; And a common electrode formed on the second passivation layer and having a plurality of first openings formed in a bar shape and spaced apart from each pixel region by a predetermined distance, the second passivation layer corresponding to the plurality of first openings And a groove for exposing the etch stopper is formed.

The first passivation layer may include a first contact hole exposing the pixel electrode, and the etch stopper contacts the pixel electrode through the first contact hole.

According to another aspect of the present invention, there is provided an array substrate for a fringe field switching mode liquid crystal display, including: a gate wiring formed on a transparent substrate and extending in one direction; A gate insulating film formed on the gate wiring; A data line crossing over the gate insulating film perpendicularly to the gate wiring and defining a pixel region; A thin film transistor electrically connected to the gate wiring and the data wiring and formed near the intersection of the two wirings; A first protective layer formed on the entire surface of the substrate over the thin film transistor, the first protective layer having a first thickness; A pixel electrode formed in contact with the drain electrode of the thin film transistor in each pixel region on the first passivation layer; A second protective layer formed on the entire surface of the substrate over the pixel electrode to have a second thickness; And a common electrode formed on the second passivation layer and having a plurality of first openings formed in a bar shape and spaced apart from each pixel region by a predetermined distance, the second passivation layer corresponding to the plurality of first openings And a groove for exposing the etch stopper is formed.

Wherein the first protective layer is provided with a drain contact hole exposing a drain electrode of the thin film transistor and the pixel electrode is in contact with the pixel electrode through the drain contact hole. Board.

The first and second thicknesses may range from about 3000 Å to about 4000 Å, the second thickness ranges from about 2000 Å to about 3000 Å, and the first and second thicknesses may be equal to or greater than about 6000 Å. And is made of silicon oxide (SiO ₂ ) or silicon nitride (SiN x) which is an inorganic insulating material.

The common electrode is characterized in that a second opening is formed in correspondence with the thin film transistor.

In addition, the pixel electrode is made of indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) which is a transparent conductive material.

The etch stopper is made of indium-tin-oxide (ITO) or indium-zinc-oxide (IZO), which is a transparent conductive material, and is formed in the same plane as the pixel electrode.

In the array substrate for a fringe field switching mode liquid crystal display according to the present invention, a double layer protective layer having a thickness of 6000 ANGSTROM or more is formed between the data line and the common electrode, and a first protective layer is removed between the common electrode and the pixel electrode So that the driving voltage can be reduced by improving the intensity of the applied fringe field.

There is an effect of reducing power consumption by reducing the driving voltage.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

4 is a plan view of one pixel region of an array substrate for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention. A region where a plurality of pixel regions P are formed is defined as a display region and a region outside the display region is defined as a non-display region, and a region where the thin film transistor Tr is formed is referred to as an element region .

As shown in the drawing, a plurality of gate wirings 105 are formed in the display region in the first direction and extend in a second direction orthogonal to the first direction. In addition to the gate wirings, a plurality of pixel regions P A plurality of data lines 130 are formed.

The gate lines 108 and the gate lines 108 are connected to the gate lines 105 and the data lines 130 in the pixel regions P or corresponding to the plurality of pixel regions P, A semiconductor layer (not shown) composed of an active layer of pure amorphous silicon (not shown) and an ohmic contact layer of impurity amorphous silicon (not shown), and source and drain electrodes 133 and 136 spaced from each other A thin film transistor Tr is formed.

In this case, although the separation region (hereinafter, referred to as a channel region) between the source and drain electrodes 133 and 136 is shown as an example in the figure, the shape of the channel region may be changed into various shapes have. For example, when the drain electrode 136 is formed in the form of a U-shaped source electrode 133 and inserted into the opening of the U-shaped source electrode 133, the channel region may include a U- Form.

Although it is shown in the drawing that the thin film transistor Tr is formed in the boundary of the pixel region P and a part of the pixel region P, the semiconductor layer (not shown) and the source and drain electrodes 133 and 136 May be formed so as to completely overlap the gate line 105, thereby forming a structure at the boundary of each pixel region P, thereby improving the aperture ratio.

On the other hand, the pixel electrode 138 is formed in contact with the drain electrode of the thin film transistor Tr.

A first passivation layer (not shown) is formed on the pixel electrode 138, and a first passivation layer (not shown) is formed on the pixel electrode 138, 138 and the etch stopper 145 is formed in a completely overlapping manner. A second passivation layer (not shown) is formed on the etch stopper 145 as an inorganic insulating material.

A common electrode (not shown) is formed on the second passivation layer (not shown) and has a plurality of first openings op1 spaced apart from each other by a predetermined distance corresponding to each pixel region P .

At this time, as a characteristic feature, the second protective layer (not shown) is removed corresponding to the first opening (op1), and a groove for exposing the etch stopper 145 is formed.

Since this structure is well shown through the cross-sectional structure, the cross-sectional structure of the array substrate for a fringe field switching mode liquid crystal display according to the first embodiment will be described hereinafter.

5 is a cross-sectional view of the portion cut along line V-V in Fig. For convenience of explanation, the portion where the thin film transistor which is the switching element is formed is defined as the element region TrA.

As shown in the figure, on a transparent insulating substrate 101 forming a base of an array substrate 101 for a fringe field switching mode liquid crystal display according to an embodiment of the present invention, a metal material having low resistance characteristics, for example, aluminum (Al Gate interconnections (not shown) extending in one direction are formed as one metal material selected from the group consisting of aluminum (AlNd), copper (Cu), copper alloy, chromium (Cr), and molybdenum (Mo) A gate electrode 108 is formed in the element region TrA in connection with the gate wiring.

A gate insulating film 115 made of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is formed on the entire surface of the substrate 101 over the gate wiring 105 and the gate electrode 108 have.

A semiconductor layer 120 composed of an active layer 120a of pure amorphous silicon and an ohmic contact layer 120b of impurity amorphous silicon corresponding to the gate electrode 108 is formed in the device region TrA above the gate insulating film 115 And source and drain electrodes 133 and 136 are formed on the semiconductor layer 120 and are spaced apart from each other. At this time, the active layer 120a is exposed between the source and drain electrodes 133 and 136 which are spaced apart from each other.

A pixel region P is defined on the gate insulating film 115 so as to intersect with the gate wiring 105 and is connected to the source electrode 133 of the thin film transistor Tr and a data line 130 is formed have. At this time, the first and second dummy patterns 121a and 121b are formed under the data line 130 as the same material as the semiconductor layer 120. However, (121a, 121b) are due to the manufacturing method and may be omitted.

Next, a plate-shaped pixel electrode 138, which is in direct contact with one end of the drain electrode and is made of a transparent conductive material, is formed on the gate insulating layer 115 in each pixel region P.

An inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN x) having a first thickness of about 3000 Å to 4000 Å is formed on the thin film transistor Tr and the pixel electrode 138, (140) are formed.

An etch stopper 145 is formed on the first passivation layer 140 by patterning a transparent conductive material using the same exposure mask used for forming the pixel electrode 138 as a characteristic feature of the present invention Respectively. At this time, the etch stopper 145 preferably has a thickness of about 200 Å to about 500 Å. The driving voltage is increased by increasing the separation distance between the common electrode 160 and the pixel electrode 138 to be formed later.

A second passivation layer 150 is formed on the etch stopper 145 with an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN x) to have a second thickness of about 2000 Å to 3000 Å have.

  The first passivation layer 140 and the second passivation layer 150 are separated from each other by the etch stopper 145 in each pixel region P, The protective layer is formed in contact with each other in the boundary region of the pixel region P where the gate and data lines (not shown) (130) are formed and the device region TrA. At this time, the first protective layer 140 and the second protective layer 140 are directly contacted with each other at a minimum thickness of 5000 to 7000 Å.

Next, a common electrode 160 having a plurality of bar-shaped first openings op1 spaced apart from each other by a predetermined distance corresponding to each pixel region P as a transparent conductive material is formed on the second passivation layer 150, Is formed on the entire surface of the display area. At this time, the common electrode 160 has a second opening op2 corresponding to the device region TrA. This is to minimize the influence on the channel region and to minimize parasitic capacitance caused by overlapping with the source and drain electrodes 133 and 136. [

Next, as another characteristic structure in the first embodiment of the present invention, in the first opening (op1) of the common electrode 160, the second passivation layer 150 is removed to form a groove, (145) is exposed.

The common electrode 160 and the second passivation layer 150 are formed between the common electrode 160 and the pixel electrode 138 and the etch stopper 145 and the common electrode 160 are formed between the common electrode 160 and the pixel electrode 138, Only the first protective layer 140 is located.
In this case, the etch stopper 145 is formed to have a thickness of 200 to 500 ANGSTROM, and the first passivation layer 140 is formed to have a thickness of 3000 to 4000 ANGSTROM, 4500A. ≪ / RTI >
Therefore, compared to the case where the second passivation layer 150 is formed to have a thickness of 2000 to 3000 ANGSTROM, the electric field generated by the fringe field between the common electrode 160 and the pixel electrode 138 It is possible to increase the strength.
That is, the second protective layer 150 having a second thickness of about 2000 Å to 3000 Å is removed corresponding to the first opening op1 of the common electrode 160, The fringe field intensity formed between the pixel electrode 160 and the pixel electrode 138 is improved. Since a part of the material layer (first and second second protective layers) that interfere with the formation of an electric field is removed, a fringe field having a larger intensity is formed for the same driving voltage application, The driving voltage can be lowered.

The removal of the second protective layer 150 corresponding to the first opening op1 provided in the common electrode 160 may be performed by the common electrode 160 itself serving as an etching prevention mask, op1 in the state where the common electrode 160 is formed, the dry etching is performed in a reactive gas atmosphere in which the inorganic insulating material can be etched.

Since the etch stopper 145 is formed in each pixel region P during the dry etching process, the first passivation layer 140 located under the etch stopper 145 is not affected at all. Therefore, the display quality deterioration due to the occurrence of stains due to the difference in fringe field intensity due to the difference in depth of the grooves corresponding to the first opening (op1) is inherently prevented.

On the other hand, when the etch stopper 145 is not formed and the first and second passivation layers 140 and 150 are made of the same inorganic insulating material as described above, a difference in etch rate is generated in each dry etching process , Resulting in a fringe field intensity difference, which may cause a display quality deterioration such as occurrence of a stain defect due to a partial luminance difference. Also, due to the characteristics of the inorganic insulating material, when the dry etching is stopped to adjust the thickness of the dry etching, the unevenness of the thickness causes the unevenness.

However, in the first embodiment of the present invention, since the etch stopper 145 is provided, only the second passivation layer 150 can be accurately removed, so that an etching error due to the dry etching progress does not occur. Therefore, Can be prevented.

At this time, since the common electrode 160 is formed corresponding to the portion where the data line 130 is formed, the first and second protective layers 140 and 150 are formed without etching the second protective layer 150 A thickness of 5000 to 7000 ANGSTROM or more is maintained. Therefore, it can be seen that the parasitic capacitance generated by the data line 130 and the common electrode 160 is the same level as the conventional one.

6 is a cross-sectional view of one pixel region of an array substrate for a fringe field switching mode liquid crystal display according to a modification of the first embodiment of the present invention. Only the portions that are different from the first embodiment will be described. 100 are added to the same constituent elements as those of the first embodiment, and the same reference numerals are given.

A structure different from the first embodiment is that a pixel electrode 238 and an etch stopper 245 formed on the lower and upper portions of the first passivation layer 240 are provided in the first passivation layer 240 And are formed to be in contact with each other through the first contact hole 241. The other components have the same configuration as the first embodiment.

In the modification of the first embodiment having such a configuration, the etch stopper 245 formed in each pixel region P having the same shape as the pixel electrode 238 is electrically connected to the drain electrode 236 through the pixel electrode 238 A signal voltage is received, and thus the second pixel electrode substantially functions as a second pixel electrode.

Therefore, the spacing between the common electrode 260 and the etch stopper 245 serving as the second pixel electrode is smaller than the spacing between the common electrode 260 and the pixel electrode 238, thereby further increasing the maximum transmissivity And the driving voltage of the driving circuit can be reduced.

At this time, since the first and second protective layers 240 and 250 are still present between the data line 230 and the common electrode 260, they have a spacing distance of 5000 to 7000 ANGSTROM or more. As a result, The same level. The spacing distance between the common electrode 260 forming the fringe field and the etch stopper 245 serving as the second pixel electrode is about 2000 Å to 3000 Å which is the second thickness of the second passivation layer 250, A groove is formed in the second passivation layer 250 to expose the etch stopper 245 serving as the second pixel electrode corresponding to the first opening op1 provided in the common electrode 260 The driving voltage can be remarkably reduced.

The other constituent elements are the same as those of the first embodiment described above, and a description thereof will be omitted.

7 is a graph showing a transmittance characteristic curve according to a change in driving voltage.

As shown in the figure, the driving voltage for maximizing the transmittance of the array substrate for a fringe field switching mode liquid crystal display device having a protective layer having a thickness of about 6000 angstroms is 4.5 V, In the case of the array substrate for a fringe field switching mode liquid crystal display device according to the first embodiment of the present invention (shown as the first embodiment) in which the second protective layer having a thickness of about 1 nm is removed corresponding to the first opening of the common electrode, The driving voltage is 3.4 V, which is lower than the conventional driving voltage.

In addition, in the case of the modification (shown as a modification) of the first embodiment in which the etch stopper is connected to the pixel electrode, the driving voltage for maximizing the transmittance is 2.9 V, which means that the driving voltage is significantly lower than the conventional one.

When the driving voltage for forming the fringe field is lowered, the power consumption can be reduced. Therefore, when the driving voltage is applied to an application such as a notebook computer or a mobile phone, the use time of the battlefield can be improved.

8 is a cross-sectional view of one pixel region of an array substrate for a fringe field switching mode liquid crystal display according to a second embodiment of the present invention. At this time, the same components as those of the first embodiment are denoted by reference numerals with the addition of 200, and a description will be given mainly of the portions which are different from the first embodiment.

In the second embodiment of the present invention, the most distinctive feature different from the first embodiment is the pixel electrode 346 serving also as an etch stopper.

Referring to the drawing, a gate and a data line (not shown) 330 which define a pixel region P and intersect with each other with a gate insulating film 315 interposed therebetween are connected to the device region TrA as in the first embodiment A thin film transistor (Tr) is provided on the substrate and a first protection having a first thickness of 3000 to 4000 Å in an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) A layer 240 is formed.

In the first embodiment, although the pixel electrode (138 in Fig. 5) is formed on the gate insulating film (115 in Fig. 5) directly in contact with the drain electrode (136 in Fig. 5) of the thin film transistor . In the second embodiment, the first passivation layer 340 is formed on the gate insulating layer 315.

The first passivation layer 340 may include a drain contact hole 342 exposing one end of the drain electrode 336 of the thin film transistor Tr.

Next, the first passivation layer 340 having the drain contact hole 342 is formed on the first passivation layer 340 as a transparent conductive material through the drain contact hole 342 and in contact with the drain electrode 336, The pixel electrode 346 is formed.

A second passivation layer 340 having a second thickness of about 2000 Å to about 3000 Å is formed on the entire surface of the pixel electrode 346. A transparent conductive material A common electrode 360 having a plurality of first openings op1 spaced apart from each other by a predetermined distance corresponding to each pixel region P is formed.

As in the first embodiment, the second passivation layer 340 has grooves that expose the pixel electrodes 346 by being removed corresponding to a plurality of first openings op1 of the common electrode 360 .

In the case of the array substrate 301 for a fringe field switching mode liquid crystal display according to the second embodiment having the above-described configuration, the parasitic capacitance due to the data line 330 and the common electrode 360, as in the modification of the first embodiment, Since the first and second protective layers 340 and 350 having a thickness of 5000 to 7000 ANGSTROM or more are formed between the two components 330 and 360, the same level as the array substrate for a conventional fringe field switching mode liquid crystal display Between the pixel electrode 346 and the common electrode 360 is formed only a second passivation layer 350 having a first thickness of 2000 Å to 3000 Å and the first opening op1 It is possible to lower the driving voltage to the level of the array substrate for the fringe field switching mode liquid crystal display according to the modification of the first embodiment by using the special It is Jing.

Hereinafter, a manufacturing method of an array substrate for a fringe field switching mode liquid crystal display according to a first embodiment of the present invention having the above-described structural features will be described with reference to FIGS. 4 and 5. FIG. At this time, in the case of the modification of the first embodiment and the case of the second embodiment, only the portions which are differentiated from the first embodiment in each process step will be briefly mentioned. On the other hand, for convenience of description, a region where the thin film transistor Tr is formed in each pixel region P is defined as an element region TrA.

First, a first metal material having low resistance characteristics such as aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, chromium (Cr), molybdenum (Mo) (Not shown) to form a first metal layer (not shown), followed by successive application of photoresist, exposure using a photomask, development of exposed photoresist, etching of the first metal layer A plurality of gate wirings 105 extending in a first direction are formed by patterning the first metal layer (not shown) by performing a mask process including a series of unit processes such as a strip A gate electrode 108 connected to the gate wiring (not shown) is formed in the element region TrA.

Next, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the gate wiring 105 and the gate electrode 108 to form a gate insulating film 115 on the entire surface of the substrate 101 .

Next, a pure amorphous silicon layer (not shown) and an impurity amorphous silicon layer (not shown) are formed on the gate insulating layer 115 and a second metal material such as aluminum (not shown) is formed on the impurity amorphous silicon layer A second metal layer (not shown) is formed by depositing one of aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), copper (Cu) and copper alloy. Thereafter, a photoresist layer (not shown) is formed on the second metal layer (not shown) and subjected to halftone exposure or diffraction exposure to develop first and second photoresist patterns (not shown) .

Next, the second metal layer (not shown) exposed to the outside of the first and second photoresist patterns (not shown), and the impurities and the pure amorphous silicon layer (not shown) below the second metal layer are etched and removed, A plurality of data lines 130 intersecting with the data lines 130 and extending in a second direction to define a plurality of pixel regions P and being connected to the data lines 130 in the device regions TrA, And forms an active layer 120a and an ohmic contact pattern (not shown) sequentially stacked on a source drain pattern (not shown) and a lower portion thereof.

 Next, the second photoresist pattern (not shown) having a small thickness is removed, thereby forming the ohmic contact pattern (not shown) located at the center and below the source drain pattern (not shown) newly exposed The source and drain electrodes 133 and 136 are separated from each other by etching so as to form an ohmic contact layer 120b exposing the active layer 120a under the source and drain electrodes 133 and 136 do. The active layer 120a and the ohmic contact layer 120b constitute a semiconductor layer 120. The gate electrode 108, the gate insulating layer 115, and the semiconductor layer 120, which are sequentially stacked in the device region TrA, 120, and the source and drain electrodes 133, 136 spaced apart from each other constitute a thin film transistor Tr.

In the first embodiment, the semiconductor layer 120, the data line 130, and the source and drain electrodes 133 and 136 are simultaneously formed through a single mask process, The first and second dummy patterns 121a and 121b are formed of the same material as the semiconductor layer 120. The semiconductor layer 120 and the data line 130 and the source and drain electrodes 133 and 136 may be formed through different mask processes. In this case, the first and second dummy patterns 121a and 121b made of a semiconductor material are not formed under the data line 130.

Next, a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) is deposited on the gate insulating film on the entire surface of the substrate 101, A pixel electrode 138 is formed in the pixel region P so as to be in direct contact with the drain electrode 136 of the thin film transistor Tr.

On the other hand, in the case of the second embodiment, the pixel electrode is not formed on the gate insulating film in this step.

Next, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the entire surface of the thin film transistor Tr, the data line 130 and the pixel electrode 138 to a thickness of 3000 Å to 4000 Å The first protective layer 140 is formed.

On the other hand, in the modification of the first embodiment, the pixel electrode (238 in Fig. 6) corresponding to the drain electrode (236 in Fig. 6) is formed by patterning the first protective layer 8) by forming a first contact hole (241 in FIG. 6) for exposing the first passivation layer (241 in FIG. 6) A drain contact hole (342 in Fig. 8) for exposing the drain electrode (336 in Fig. 8) is formed.

In the case of the first embodiment, the first protective layer 140 is not patterned but is maintained in a state of being deposited on the entire surface.

Next, a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) is deposited on the first passivation layer 140. When the pixel electrode 138 is formed An etching stopper 145 having the same planar shape as that of the pixel electrode 138 and overlapping with the island electrode is formed by performing a mask process using the used exposure mask as it is.

At this time, in the modification of the first embodiment, the etch stopper (245 of FIG. 6) is in contact with the pixel electrode (238 of FIG. 6) through the first contact hole (241 of FIG. 6).

8) of the first protective layer (340 in FIG. 8) is formed in the same manner as the etch stopper (245 in FIG. 6) of the first embodiment by the above- The pixel electrode (346 in FIG. 8) is formed in the drain contact hole (342 in FIG. 8) provided in the first protective layer (340 in FIG. 8) (336 in Fig. 8) of the thin film transistor (Tr in Fig. 8).

Next, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN x) is deposited on the etch stopper 345 (the pixel electrode in the case of the second embodiment) to form a first electrode having a second thickness of about 3000 Å to 4000 Å The second protective layer 350 is formed.

Then, a transparent conductive material layer (not shown) is formed on the second passivation layer 350 by depositing a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). Thereafter, the transparent conductive material layer (not shown) is patterned by a mask process to form a plurality of first openings op1 having a bar shape spaced apart from each other in correspondence to the pixel regions P And a second opening op2 exposing the thin film transistor Tr including a spacing region between the source and drain electrodes 133 and 136 corresponding to the device region TrA. At this time, the second protective layer 250 is exposed in correspondence to the first openings op1 and the second openings op2.

Next, the substrate 101 on which the common electrode 160 having the plurality of first openings op1 and the second openings opposed is formed is subjected to a dry etching process using a reactive gas having a property of reacting with and removing the inorganic insulating material The second passivation layer 160 exposed through the plurality of first openings op1 is removed to expose the etch stopper 145 (the pixel electrode in the second embodiment) The array substrate 101 for a fringe field switching mode liquid crystal display according to the first embodiment is completed. At this time, the second passivation layer 150 exposed through the second opening op2 is also removed, thereby exposing the first passivation layer 140. However, the element region Tr is formed by a portion forming the fringe field So that the first protective layer 140 is not completely removed and a part of the thickness is reduced.

The present invention is not limited to the above-described embodiments and modifications, and various changes and modifications can be made without departing from the spirit of the present invention.

1 is a cross-sectional view schematically showing a part of a general transverse electric field type liquid crystal display device.

FIGS. 2A and 2B are cross-sectional views respectively showing the on and off states of a general transverse electric field liquid crystal display device;

3 is a cross-sectional view of one pixel region of an array substrate of a conventional fringe field switching mode liquid crystal display.

4 is a plan view of one pixel region of an array substrate for a fringe field switching mode liquid crystal display according to the first embodiment of the present invention.

5 is a cross-sectional view of a portion cut along line V-V in Fig. 4; Fig.

6 is a cross-sectional view of one pixel region of an array substrate for a fringe field switching mode liquid crystal display according to a modification of the first embodiment of the present invention.

7 is a graph showing a transmittance characteristic curve according to a change in driving voltage.

8 is a cross-sectional view of one pixel region of an array substrate for a fringe field switching mode liquid crystal display according to a second embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

101: array substrate 108: gate electrode

115: gate insulating film 120: semiconductor layer

120a: active layer 120b: ohmic contact layer

130: data line 133: source electrode

136: drain electrode 138: pixel electrode

140: first protective layer 145: etch stopper

150: second protection layer 160: common electrode

op1 and op2: first and second openings P: pixel region

Tr: thin film transistor TrA: element region

Claims (9)

A gate wiring provided on the transparent substrate in one direction; A gate insulating film located above the gate wiring; A data line crossing the gate line above the gate insulating layer and defining a pixel region; A thin film transistor electrically connected to the gate wiring and the data wiring and positioned at an intersection of the two wirings; A pixel electrode on the gate insulating film, the pixel electrode being in contact with the drain electrode of the thin film transistor and located in the pixel region; A first protective layer on the entire surface of the substrate over the pixel electrode, the first protective layer having a first thickness; An etch stopper located in each pixel region above the first passivation layer; A second passivation layer over the etch stopper and having a second thickness over the substrate; And a plurality of first openings having a bar shape and spaced apart from each other by a predetermined distance over the second protective layer, Wherein the second protective layer has grooves for exposing the etch stopper corresponding to the plurality of first openings. ≪ Desc / Clms Page number 19 > The method according to claim 1, Wherein the first passivation layer includes a first contact hole exposing the pixel electrode, and the etch stopper contacts the pixel electrode through the first contact hole. delete delete 3. The method according to claim 1 or 2, The first thickness ranges from 3000 A to 4000 A, Wherein the second thickness is 2000 Å to 3000 Å. 6. The method of claim 5, Wherein the first and second protective layers are made of silicon oxide (SiO ₂ ) or silicon nitride (SiN x), which is an inorganic insulating material, for the fringe field switching mode liquid crystal display. 3. The method according to claim 1 or 2, Wherein the common electrode includes a second opening corresponding to the thin film transistor. 3. The method according to claim 1 or 2, Wherein the pixel electrode is made of indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) which is a transparent conductive material. 3. The method according to claim 1 or 2, Wherein the etch stopper is made of indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) which is a transparent conductive material and has the same planarity as the pixel electrode.

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