KR101971144B1 - Array substrate for Fringe field switching mode liquid crystal display device - Google Patents

Abstract

A plurality of gate wirings formed in one direction on a substrate provided with a display region including a plurality of pixel regions and a non-display region outside thereof; A plurality of data lines formed to intersect the gate lines and the gate insulating layer to define a plurality of pixel regions; A thin film transistor formed in each pixel region and electrically connected to the gate line and the data line; And a gate electrode which is formed to overlap with a gate line located at a boundary with a neighboring pixel region extending to upper and lower neighboring pixel regions, A pixel electrode; An insulating layer formed on the pixel electrode; And a plurality of second common electrodes formed on the insulating layer and spaced apart from the first common electrodes in a linear shape corresponding to the respective data lines and spaced apart from the first common electrodes, And a plurality of second regions for connecting the plurality of first regions and the first region with the first common electrode, wherein the plurality of first regions are arranged in parallel with the first common electrode, And the second common electrode is connected to and corresponds to two or more pixel regions located in the upper and lower positions.

Description

[0001] The present invention relates to an array substrate for a fringe field switching mode liquid crystal display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a fringe field switching mode liquid crystal display device having improved transmittance.

Description of the Related Art [0002] Liquid crystal display devices (LCDs) are display devices using optical anisotropy and polarization properties of liquid crystals, and are widely used in displays of portable electronic devices, monitors or televisions of computers.

Liquid crystals have a long and elongated molecular structure, and they have a directionality in orientation. When placed in an electric field, the orientation of molecules is changed according to their size and direction. Therefore, the liquid crystal display device includes a liquid crystal panel in which a liquid crystal layer is positioned between two substrates on which electric field generating electrodes are respectively formed, and artificially adjusts the arrangement direction of liquid crystal molecules through a change in an electric field generated between the two electrodes, And various images are displayed by changing the light transmittance.

In general, a liquid crystal display device includes an array substrate on which a plurality of wirings, switching elements, and pixel electrodes are formed, and a color filter substrate on which color filters and common electrodes are formed. The liquid crystal molecules between the two substrates are arranged between the pixel electrodes and the common electrodes Is driven by the induced electric field, that is, the vertical electric field in the direction perpendicular to the substrate.

However, there is a problem that the method of driving the liquid crystal by the vertical electric field is not excellent in the viewing angle characteristic.

In order to overcome such a problem, a transverse electric field type liquid crystal display device has been proposed. In the transverse electric field type liquid crystal display device, the pixel electrode and the common electrode are staggered on the same substrate, and a horizontal electric field in a direction parallel to the substrate is induced between the two electrodes. Therefore, the liquid crystal molecules are driven by a horizontal electric field and move in a direction parallel to the substrate, and such a lateral electric field liquid crystal display device has an improved viewing angle.

However, such a transverse electric field type liquid crystal display device has a disadvantage of low aperture ratio and low transmittance.

Accordingly, a fringe field switching mode liquid crystal display (LCD) driving a liquid crystal by a fringe field has been proposed in order to overcome the drawbacks of the transverse electric field liquid crystal display.

1 is a plan view of one pixel region in an array substrate of a conventional fringe field switching mode liquid crystal display.

As shown in the drawing, a plurality of gate wirings 43 extend in one direction. A plurality of data wirings 51 are defined by intersecting the plurality of gate wirings 43 to define a plurality of pixel regions P Respectively.

Each of the plurality of pixel regions P is connected to the data line 51 and the gate line 43 defining the pixel region P and includes a gate electrode 45, a gate insulating layer (not shown), a semiconductor layer (not shown) And a thin film transistor Tr which is a switching element including drain electrodes 55 and 58 is formed.

A pixel electrode 60 connected to the thin film transistor Tr is formed in the pixel region P and the pixel electrode 60 is connected to the thin film transistor Tr through a drain contact hole 59. [ Drain electrode 58, and has a plate shape corresponding to each pixel region P substantially.

A common electrode 75 is formed on the entire surface of the display region on which the plurality of pixel regions P are formed so as to overlap with the plate-shaped pixel electrode 60 corresponding to each pixel region P. At this time, the common electrode 75 has a plurality of openings op in each pixel region P. That is, the common electrode 75 extends to the adjacent pixel region P and is formed to correspond to the entire display region including the plurality of pixel regions P, and the plurality of common electrodes 75 Each of the openings (op) is in the form of a bar parallel to the data line 51.

The array substrate 41 for a conventional fringe field switching mode liquid crystal display having such a structure is formed by applying a voltage to the pixel electrode 60 and the common electrode 75 for each pixel region P, field.

However, in the conventional array substrate 41 for a fringe field switching liquid crystal display having the above-described configuration, the common electrode 75 having the plurality of bar-shaped openings op corresponding to the pixel electrodes 60, In particular, it can be seen that the plurality of openings op are formed so as to completely overlap with the pixel electrodes.

In this case, since the electric field is not formed in one direction at both ends in the major axis direction of the opening op in terms of the shape of the pixel electrode 60 and the common electrode 75, That is, a photograph showing that a foreground is generated in one pixel region of the liquid crystal display device), a disclination area DA is generated in which liquid crystal molecules move in different directions.

Such a foreground area DA is irregularly dark compared with the surrounding area because the liquid crystal display device can not transmit light in a fully on state.

A portion where such a foreground area DA is generated does not normally transmit light, so that the transmittance is lowered and the display quality is lowered.

In addition, in the conventional array substrate for the fringe field switching mode liquid crystal display, since the common electrode is formed on the entire surface of the display area, that is, the area occupied by the common electrode itself in the pixel area is larger than the area of the opening, So that the overlapping region with the pixel electrode in each pixel region is relatively large.

Therefore, the storage capacitor StgC formed between the pixel electrode 60 and the common electrode 74 has a value three to five times larger than that of the transverse electric field liquid crystal display device.

When the capacity of the storage capacitor StgC is excessively large, a relatively large charging time is required, so that a high-resolution model with a short charging time or a high-frequency model is difficult to charge.

SUMMARY OF THE INVENTION The present invention has been conceived to solve the problems of the conventional array substrate for a fringe field switching mode liquid crystal display device, and it is an object of the present invention to provide a high- And an object of the present invention is to provide an array substrate for a fringe field switching mode liquid crystal display device capable of reducing the storage capacity in each pixel region to improve the charging characteristics.

According to an aspect of the present invention, there is provided an array substrate for a fringe field switching mode liquid crystal display, comprising: a substrate having a display region including a plurality of pixel regions and a non- A plurality of extended gate wirings; A plurality of data lines formed to intersect the gate lines and the gate insulating layer to define a plurality of pixel regions; A thin film transistor formed in each pixel region and electrically connected to the gate line and the data line; And a gate electrode which is formed to overlap with a gate line located at a boundary with a neighboring pixel region extending to upper and lower neighboring pixel regions, A pixel electrode; An insulating layer formed on the pixel electrode; And a plurality of second common electrodes formed on the insulating layer and spaced apart from the first common electrodes in a linear shape corresponding to the respective data lines and spaced apart from the first common electrodes, And a plurality of second regions for connecting the plurality of first regions and the first region with the first common electrode, wherein the plurality of first regions are arranged in parallel with the first common electrode, And the second common electrode is formed so as to correspond to two or more pixel regions located in the upper and lower positions.

In this case, the gate wiring overlapping with the pixel electrode is a gate wiring which is not connected to the thin film transistor connected to the pixel electrode among the upper and lower gate wirings defining the pixel region.

The spacing between the upper and lower adjacent pixel electrodes is 5 占 퐉 or less.

When the number of first regions constituting each of the second common electrodes is n (n is a natural number greater than 1), n second common electrodes are formed within each pixel region with a predetermined distance therebetween, Each of the second common electrodes is formed so as to correspond to n pixel regions with respect to upper and lower neighboring pixel regions.

In addition, the second region may be formed to correspond to a spacing region between the gate line and two adjacent pixel electrodes positioned adjacent to the gate line, and one end of the first common electrode may be connected to the non- .

The thin film transistor may include a semiconductor layer having a bilayer structure of an amorphous silicon ohmic contact layer which is separated from an active layer of pure amorphous silicon and is formed on the oxide semiconductor layer and on the oxide semiconductor layer, A semiconductor layer having a single-layer structure including an etch stopper formed corresponding to a central portion or an etch stopper having a semiconductor contact hole exposing the oxide semiconductor layer.

Further, a protective layer having a flat surface between the thin film transistor and the pixel electrode and having a drain contact hole exposing a drain electrode of the thin film transistor is further provided, and the pixel electrode is formed on the gate insulating film.

The common electrode is characterized in that the first common electrode, the second common electrode spaced apart from the first common electrode, and the spaced region between the second common electrode form an opening.

The array substrate for the fringe field switching mode liquid crystal display according to the present invention is formed such that the common electrode is reduced in area and connected to the pixel regions located above and below the openings so that generation of foreground is suppressed at the upper and lower ends of the pixel regions The bar has an effect of improving the transmittance and at the same time providing an image of high quality due to suppression of the occurrence of the foreground.

Further, by reducing the area of the common electrode and optimizing the area of the opening, the area is overlapped with the pixel electrode in each pixel area, thereby reducing the area and improving the charging characteristics.

1 is a plan view of one pixel region of an array substrate of a conventional fringe field switching mode liquid crystal display;
2 is a photograph showing that a foreground occurs in one pixel region of a conventional fringe field switching mode liquid crystal display device.
3 is a plan view of a portion of a display region of an array substrate for a fringe field switching mode liquid crystal display according to an embodiment of the present invention.
4 is a view schematically showing a planar shape of another common electrode in an array substrate for a fringe field switching mode liquid crystal display according to an embodiment of the present invention.
Fig. 5 is a cross-sectional view of a portion cut along line V-V in Fig. 3; Fig.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a plan view of a portion of a display area of an array substrate for a fringe field switching mode liquid crystal display according to an embodiment of the present invention. For convenience of description, an area in which a plurality of pixel areas P are formed is defined as a display area, and an area located outside the display area is defined as a non-display area. A portion where the thin film transistor Tr is formed in the pixel region P is defined as a switching region TrA.

As shown in the drawing, the array substrate 101 for a fringe field switching mode liquid crystal display according to an embodiment of the present invention includes gate lines 107 extending in a first direction in a display region, And a data line 130 which extends along the gate line 107 and defines the pixel region P is formed.

The switching region TrA in each pixel region P is provided with a thin film transistor Tr which is connected to the gate wiring 107 and the data wiring 130 and is a switching element.

At this time, the thin film transistor Tr includes a gate electrode 107, a gate insulating film (not shown), an active layer of pure amorphous silicon (not shown) and an ohmic contact layer (not shown) of impurity amorphous silicon (Not shown) and source and drain electrodes 133 and 136 spaced apart from each other on the semiconductor layer (not shown), or a bilayer semiconductor layer (not shown) made of pure water and impurity amorphous silicon, A gate insulating film (not shown), an oxide semiconductor layer (not shown), and an etch stopper (not shown) are provided in place of the gate electrode 107, an oxide semiconductor layer And a source electrode 133 and a drain electrode 136 which are separated from each other on the etch stopper (not shown) and contact the oxide semiconductor layer (not shown), respectively.

In the array substrate 101 for a fringe field switching mode liquid crystal display according to an embodiment of the present invention, a plate-shaped pixel electrode 150 is formed in each pixel region P as a drain contact And is formed in contact with the drain electrode 136 of the thin film transistor Tr through a hole 143.

The plate-shaped pixel electrode 150 is connected to the thin film transistor Tr provided in each pixel region P among the two gate lines 107 provided at the top and bottom of each pixel region P, And extends to the neighboring pixel region P while overlapping the gate wiring 107b other than the wiring 107a, that is, the gate wiring 107b not connected to the thin film transistor Tr that is involved in the pixel region P .

At this time, the spacing distance d1 between the pixel electrodes 150 adjacent to each other in each pixel region P is greater than or equal to a size (usually 2 mu m) which does not cause a patterning error as a mask process proceeds, Or less.

When the spacing d1 between the upper and lower neighboring pixel electrodes 150 is greater than 6 mu m on the characteristic of the array substrate 101 for a fringe field switching mode liquid crystal display according to an embodiment of the present invention, (1 in Fig. 1) for the mode liquid crystal display device.

For example, assuming that the transmittance of each pixel region of the array substrate (1 of FIG. 1) for a conventional fringe field switching mode liquid crystal display device is assumed to be 100%, the fringe field switching mode liquid crystal display device according to the embodiment of the present invention The spacing d1 between the pixel electrodes 150 adjacent to the upper and lower sides of the array substrate 101 is 118.5%, 115.1% when the distance d1 is 1 占 퐉, and 105.6% when the distance is 5 占 퐉 It was found that the transmittance was 98.5% in the case of 7 μm, and the transmittance was smaller than that of the conventional array substrate for fringe field switching mode liquid crystal display (1 in FIG. 1).

Therefore, it is preferable that the spacing distance between the upper and lower neighboring pixel electrodes 150 is 5 mu m or less within a range in which no patterning error occurs. In this case, in the case of the conventional fringe field switching mode liquid crystal display array substrate 1 < / RTI > of FIG. 1).

The common electrode 170 overlaps the pixel region P corresponding to the pixel electrode 150 having such a structure.

At this time, the common electrode 170 is not formed on the entire surface of the display region as in the conventional art, and an opening (op) is partially connected between the upper and lower pixel regions P in each display region .

The planar configuration of the common electrode 170 will be described in more detail.

The common electrode 170 provided on the array substrate 101 for a fringe field switching mode liquid crystal display according to an embodiment of the present invention has a linear bar shape without a bent portion in a display region, And the first common electrode 171 is formed to have a width wider than the data line 130. The first common electrode 171 branched in the form of a straight line bar is connected to the second common electrode 171, 174 are provided.

The portion of the second common electrode 174 which branches off from the first common electrode 171 is located in a region between the portion where the gate wiring 107 is formed and the pixel electrode 150 located above and below to be.

The second common electrode 174 branched from the first common electrode 171 is bent again in the pixel region P located at the lower end to position the pixel region P located at the upper end And the end of the second common electrode 174 is connected to the first common electrode 171 which overlaps the data line 130. In this case,

That is, in the array substrate 101 for a fringe field switching mode liquid crystal display according to an embodiment of the present invention, the common electrode 170 has a straight line shape without bending, A common electrode 171 and a second common electrode 174 connected to two first common electrodes 171 located on the left and right sides of the common electrode 171 with respect to each pixel region P Feature.

The second common electrode 174 may include a plurality of first regions 174a disposed in parallel to the first common electrode 171 and a second region 174b connecting the plurality of first regions 174a. (174b).

Each of the second common electrodes 174 is formed corresponding to two or more neighboring pixel regions P in the vertical direction. In this case, each of the first regions 174a is formed in parallel with the first common electrode 171, and the positions thereof are different for each pixel line defined as a group of pixel regions P connected to the same gate line 107 .

In FIG. 4, the second common electrode 174 is formed to be spaced apart from the pixel region P by a predetermined distance. In FIG. 4, The second common electrode 174 may be spaced apart from each other by a predetermined distance in the pixel region P and may be formed in a number of two or more, as shown in a plan view of another common electrode in the substrate) have. 4, three second common electrodes 174 are formed in each pixel region P, for example.

The second common electrode 174 has a length corresponding to the number of the first common electrode 174, and the number of the first common electrode 174 is equal to the number of the first common electrode 174 174a are provided and connected to the same number of pixel regions P1, P2, P3 as the number of the first regions 174a in the longitudinal direction of the pixel region P, that is, And is formed.

The second region 174b among the components constituting the second common electrode 174 has a boundary between the pixel regions P1, P2 and P3 more precisely between the portion where the gate wiring 107 is formed and the portion where the gate wiring 107 And the pixel electrodes 150 are arranged in the vertical direction.

3, when two second common electrodes 174 are formed in each pixel region P with reference to one pixel region P as shown in the drawing, And a second region 174b located at both ends of each first region 174a is divided into a first region 174a and a second region 174b, And the second region 174b located at the center connects the first region 174a with the first region 174a.

The first region 174a is located at the first position Po1 in the first pixel region P1 and the other first region 174a is located at the lower portion of the first pixel region P1 And a second position Po2 that is spaced apart from the first position Po1 by a predetermined distance to the right in the second pixel region P2.

At this time, the second region 174b is formed to correspond to the gate wiring 107 or the spacing region of the pixel electrode 150 located above and below.

4, three second common electrodes 174 are formed for each pixel region P1, P2, and P3, and three pixel regions P1, P2, and P3 adjacent to the first and second pixel electrodes P1, P2, And they are connected to each other.

In this case, when the pixel region P located at the lower portion from the upper portion is defined as the first, second, and third pixel regions P1, P2, and P3, The second common electrode 174 adjacent to the first common electrode 171 is arranged at the first position Po1 in the first pixel region P1 and at the first position Po1 in the second pixel region P2. In the second position Po2 which is spaced apart from the right side by a predetermined distance and in the third position Po3 which is spaced apart from the second position Po2 by a predetermined distance in the third pixel region P3 .

In the second pixel region P2, the first common electrode 171 is connected to the first common electrode 171 at the first position Po1 and the second common electrode 174 is located at the first position Po1. And extends to the third pixel region P3 and is located at the second position Po2.

In the third pixel region P3, another second common electrode 174 branched from the first common electrode 171 located on the left side is located at the first position Po1.

When the common electrode 170 is formed as described above, the spacing region between the first and second common electrodes 171 and 174 and the second common electrode 174 form an opening op. do.

The common electrode 170 having such a configuration may be formed by disposing the second common electrode 174 apart from each other when viewed only in each pixel region P, but the first common electrode 171 and the 2 common electrodes 174 are all connected.

Therefore, even if a common voltage is applied to any portion of the common electrode 170, a common voltage of the same magnitude can be applied to the entire display region.

Although not shown in the drawing, the common electrode 170 may have a structure in which all ends of the common electrode 170 are connected to each other in a non-display region outside the display region. In this case, since the ends of the first common electrodes 171 are connected again, a common voltage of the same magnitude can be applied to the entire display area.

In the case of the array substrate 101 for a fringe field switching mode liquid crystal display according to an embodiment of the present invention having such a configuration, there is no configuration in which common electrodes are connected to the entire display region in the extension direction of the gate wiring 107 And the area of the common electrode 170 overlapping the pixel electrode 150 becomes relatively small.

Therefore, the overlapping area of the common electrode 170 and the pixel electrode 150 in each pixel region P is reduced compared to the conventional array substrate for fringe field switching mode liquid crystal display (1 in FIG. 1) The charging speed can be improved.

In addition, in the array substrate 101 for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention, the openings op formed in the common electrode 170 may include at least two adjacent pixel regions P1 (P2 in FIG. 1) are connected to each other. Therefore, each opening (op in FIG. 1) is formed for each pixel region (P in FIG. 1) as in the conventional array substrate for a fringe field switching mode liquid crystal display 1) and the pixel electrode (60 in Fig. 1) caused by the openings (op in Fig. 1) due to the pixel electrode (60 in Fig. 1) can be suppressed or minimized, thereby improving the transmittance and improving the display quality .

Hereinafter, a cross-sectional structure of an array substrate for a fringe field switching mode liquid crystal display according to an embodiment of the present invention having the above-described plane structure will be described.

5 is a cross-sectional view of a portion cut along line V-V in Fig. 3; Fig. For convenience of description, a portion where the thin film transistor Tr as a switching element is formed in each pixel region P is defined as a switching region TrA.

As shown in the figure, the array substrate 101 for a fringe field switching mode liquid crystal display according to an embodiment of the present invention includes a transparent insulating substrate 101, for example, a glass or plastic substrate, (Not shown) extending in the first direction as a metal material selected from among materials such as aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, chromium (Cr), and molybdenum And a gate electrode 105 is formed in the switching region TrA in connection therewith.

A gate insulating film 110 is formed on the entire surface of the substrate 101 over the gate wiring (not shown) and the gate electrode 105 as an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) have.

A semiconductor layer 120 consisting of an active layer 120a of pure amorphous silicon and an ohmic contact layer 120b of impurity amorphous silicon corresponding to the gate electrode 105 in the switching region TrA above the gate insulating layer 110, Respectively.

Although the semiconductor layer 120 is formed of pure amorphous silicon and impurity amorphous silicon, the semiconductor layer 120 may be an oxide semiconductor material such as IGZO (Indium Gallium Zinc Oxide) (Zinc Tin Oxide), ZIO (Zinc Indium Oxide), or the like.

A source electrode 133 and a drain electrode 136 are formed on the semiconductor layer 120 to be spaced apart from each other.

In this case, when the semiconductor layer 120 is formed of an oxide semiconductor layer (not shown), an island shape (not shown) exposing both ends of the oxide semiconductor layer (not shown) corresponding to the central portion of the oxide semiconductor layer (Not shown) having a semiconductor layer contact hole (not shown) for exposing both ends of the oxide semiconductor layer (not shown) or an etch stopper (not shown) of the oxide semiconductor layer The source electrode 133 and the drain electrode 136 may be formed in contact with the oxide semiconductor layer (not shown).

A data line 130 which intersects the gate line (not shown) and defines the pixel region P extends in the second direction and is formed on the gate insulating layer 110 (or an etch stopper .

Although the first and second semiconductor patterns 121a and 121b made of the same material that forms the active layer 120a and the ohmic contact layer 120b are formed under the data line 130 in the drawing, This is due to the manufacturing method and can be omitted. Furthermore, when the thin film transistor includes the oxide semiconductor layer (not shown), the first and second semiconductor patterns 121a and 121b are not formed under the data line 130.

The source electrode 133 of the thin film transistor Tr is connected to the data line 130.

In addition, the data line 130, was covered with a thin film transistor (Tr), for the inorganic insulating material, for example one or an organic insulating material selected from silicon oxide (SiO ₂₎ or silicon nitride (SiNx), for example, benzocyclobutene A first protective layer 140 is formed on the entire surface of the substrate 101 as a BCB or photo acryl.

A drain contact hole 143 exposing a portion of the drain electrode 136 of the thin film transistor Tr is formed in the first passivation layer 140.

In addition, a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) is formed for each pixel region P on the first passivation layer 140 having the drain contact hole 143, A plate-shaped pixel electrode 150 is formed in contact with the drain electrode 136 through the drain contact hole 143.

At this time, the pixel electrode 150 overlaps a gate line (not shown) not connected to the thin film transistor Tr connected thereto and extends to a neighboring pixel region P, and the adjacent pixel region P And the pixel electrode 150 adjacent thereto is characterized by having a spacing of 5 mu m or less within a range where these two pixel electrodes 150 do not cause a patterning error.

In this case, the pixel electrode 150 may be formed on the gate insulating layer 110 directly in contact with the drain electrode 136 of the thin film transistor Tr as a modification of the cross-sectional structure. In this case, the first passivation layer 140 having the drain contact hole 143 is omitted.

A second passivation layer 160 is formed on the entire surface of the substrate 101 using the inorganic insulating material or the organic insulating material on the pixel electrode 150. An example of a transparent conductive material is provided on the second passivation layer 160 A first common electrode 171 formed of indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) and having a linear bar shape corresponding to the data line 130, And a common electrode 170 composed of a plurality of second common electrodes 174 is formed.

At this time, the common electrode 770 is characterized in that a spacing region between the first common electrode 171 and the second common electrode 174 and a spacing region between the second common electrode 174 form an opening op .

The shape of the common electrode 170 having such a structure has been described in detail with reference to the plan view, and therefore, the description thereof will be omitted.

The present invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit of the present invention.

101: substrate 107: gate wiring
105: gate electrode 130: data line
133: source electrode 136: drain electrode
143: drain contact hole 150: pixel electrode
170: common electrode 171: first common electrode
174: second common electrode 174a: first region
174b: second region P: pixel region
op: opening Tr: thin film transistor
TrA: switching area

Claims (12)

A plurality of gate wirings extending in one direction on a substrate provided with a display region including a plurality of pixel regions and a non-display region outside thereof;
A plurality of data lines formed to intersect the gate lines and the gate insulating layer to define a plurality of pixel regions;
A thin film transistor formed in each pixel region and electrically connected to the gate line and the data line;
Wherein each of the pixel regions has a plate shape in contact with a drain electrode of the thin film transistor provided in each of the pixel regions and extends to a vertically adjacent pixel region, A pixel electrode formed to overlap both the first and second sides;
An insulating layer formed on the pixel electrode;
And a plurality of second common electrodes formed on the insulating layer and spaced apart from the first common electrodes in a linear shape corresponding to the respective data lines and spaced apart from the first common electrodes, And a plurality of second regions for connecting the first regions and the first common electrodes between the first regions and the first regions.
Wherein the second common electrode is formed to be connected to at least two pixel regions located at upper and lower positions.
The method according to claim 1,
Wherein the gate wiring overlapping with the pixel electrode is a gate wiring not connected to the thin film transistor connected to the pixel electrode among two upper and lower gate wirings defining the pixel region.
The method according to claim 1,
Wherein the spacing between the upper and lower neighboring pixel electrodes is 5 占 퐉 or less.
The method according to claim 1,
When the number of the first regions constituting each of the second common electrodes is n (n is a natural number greater than 1), n second common electrodes are formed within each pixel region at a predetermined interval, And the second common electrode is extended to correspond to n pixel regions with respect to upper and lower neighboring pixel regions.
The method according to claim 1,
Wherein the second region is formed to correspond to a spacing region between the gate line and adjacent two pixel electrodes adjacent to and adjacent to the gate line.
The method according to claim 1,
Wherein one end of the first common electrode is connected in the non-display region.
The method according to claim 1,
Wherein the thin film transistor comprises an active layer of pure amorphous silicon and a semiconductor layer having a bilayer structure of an ohmic contact layer of impurity amorphous silicon spaced apart from the active layer,
Or a single-layered semiconductor layer including an oxide semiconductor layer and an etch stopper formed on the oxide semiconductor layer and corresponding to a central portion of the oxide semiconductor layer, or an etch stopper having a semiconductor contact hole exposing the oxide semiconductor layer. Fringe field switching mode Array substrate for liquid crystal display.
The method according to claim 1,
And a protective layer having a flat surface between the TFT and the pixel electrode and having a drain contact hole exposing a drain electrode of the TFT.
The method according to claim 1,
And the pixel electrode is formed on the gate insulating layer.
The method according to claim 1,
Wherein the common electrode has an opening between the first common electrode and the second common electrode spaced apart from the first common electrode and the spaced region between the second common electrode and the second common electrode. The method according to claim 1,
(N is a natural number greater than 1) is located in each of the pixel regions, and a first region (k is a natural number smaller than n) of the first pixel region is located in the lower portion of the first pixel region (K + 1) < th > first region of the second pixel region located in the second pixel region and the second region.
The method according to claim 1,
Wherein the pixel electrode has first and second edges parallel to the first and second sides, and a first distance from the first side to the first edge of the pixel electrode is a distance from the first side to the pixel electrode And the first distance is greater than the third distance between the first and second sides. The fringe field switching mode liquid crystal display of claim 1, wherein the second distance is less than the second distance.

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