KR20120115837A - Fringe field switching type thin film transistor substrate and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A fringe field switching type thin film transistor substrate and a manufacturing method thereof are provided to manufacture a fringe field switching type thin film transistor substrate with an oxide semiconductor layer by 6 mask processes. CONSTITUTION: A pixel electrode(PXL) is connected to a thin film transistor through a drain contact hole. The drain contact hole passes a protective film. The pixel electrode is overlapped with a common electrode wherein the pixel electrode has a shape made of rods. A shield line(SH) is formed on the protective film. The shield line is overlapped with a data line.

Description

Fringe Field Switching Thin Film Transistor Substrate and its Manufacturing Method {Fringe Field Switching Type Thin Film Transistor Substrate and Manufacturing Method Thereof}

The present invention relates to a thin film transistor substrate for a fringe field switching type horizontal field type liquid crystal display device and a method of manufacturing the same. In particular, the present invention relates to a method for manufacturing a thin film transistor substrate for a fringe field switching type liquid crystal display device, which requires a relatively large number of mask steps, and to a method for manufacturing a thin film transistor substrate using the method and a method of manufacturing the same. will be.

A liquid crystal display device (LCD) displays an image by adjusting the light transmittance of the liquid crystal using an electric field. Such liquid crystal displays are classified into a vertical electric field type and a horizontal electric field type according to the direction of the electric field for driving the liquid crystal.

In the vertical field type liquid crystal display, a liquid crystal in TN (Twistred Nematic) mode is driven by a vertical electric field formed between a pixel electrode and a common electrode disposed to face up and down substrates. Such a vertical field type liquid crystal display device has an advantage of large aperture ratio, but has a disadvantage that the viewing angle is as narrow as 90 degrees.

In a horizontal field type liquid crystal display, a horizontal electric field is formed between a pixel electrode and a common electrode disposed in parallel to a lower substrate to drive a liquid crystal in an in plane switching (IPS) mode. The IPS mode liquid crystal display device has a wide viewing angle of about 160 degrees, but has a disadvantage of low aperture ratio and low transmittance. Specifically, in the IPS mode liquid crystal display, the gap between the common electrode and the pixel electrode is formed to be wider than the gap between the upper and lower substrates in order to form an in-plane field, and the common electrode and the pixel electrode in order to obtain an electric field having an appropriate intensity. In the form of a strip having a constant width. An electric field substantially parallel to the substrate is formed between the pixel electrode and the common electrode in the IPS mode, but no electric field is formed in the liquid crystal on the pixel electrode having the width and the common electrodes. That is, the liquid crystal molecules on the pixel electrode and the common electrode are not driven and maintain their initial arrangement. Liquid crystals that maintain their initial state do not transmit light, which is a factor of lowering the aperture ratio and transmittance.

In order to improve the disadvantage of the IPS mode liquid crystal display device, a fringe field switching (FFS) type liquid crystal display device operated by a fringe field has been proposed. A FFS type liquid crystal display device has a common electrode and a pixel electrode with an insulating film interposed therebetween in each pixel region, and the gap between the common electrode and the pixel electrode is formed to be smaller than the gap between the upper and lower substrates, thereby forming a parabola on the common electrode and the pixel electrode. Make a fringe field of the shape. By operating the liquid crystal molecules interposed between the upper and lower substrates by the fringe field, it is possible to obtain a result of improved aperture ratio and transmittance.

1 is a plan view illustrating a thin film transistor (TFT) substrate having an oxide semiconductor layer included in a conventional FFS type liquid crystal display device. FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along the line II ′.

The thin film transistor substrate illustrated in FIGS. 1 and 2 includes a gate wiring 13 and a data wiring 23 crossing each other with a gate insulating film 11 interposed therebetween on a lower substrate 1, and a thin film transistor formed at each intersection thereof. 7). In the thin film transistor substrate, the pixel region is defined by the intersection structure of the gate wiring 13 and the data wiring 23. The pixel region includes the pixel electrode 45 and the common electrode 55 formed with the passivation layer 11 therebetween to form a fringe field. The pixel electrode 45 has a substantially rectangular shape corresponding to the pixel area, and the common electrode 55 is formed in a plurality of parallel band shapes.

The common electrode 55 is connected to the common wiring 53 arranged side by side with the gate wiring. The common electrode 55 is supplied with a reference voltage (or common voltage) for driving the liquid crystal through the common wire 53.

The thin film transistor 7 keeps the pixel signal of the data line 23 charged in the pixel electrode 45 in response to the gate signal of the gate line 13. To this end, the thin film transistor 7 faces the gate electrode 15 branched from the gate line 13, the source electrode 25 branched from the data line 23, and the source electrode 25 and faces the pixel electrode 45. And a drain electrode 35 connected to the gate electrode 11 and a semiconductor layer 37 overlapping the gate electrode 15 on the gate insulating layer 11 and forming a channel between the source electrode 25 and the drain electrode 35. An ohmic contact layer for ohmic contact may be further included between the semiconductor layer 37 and the source electrode 25 and between the semiconductor layer 37 and the drain electrode 35.

In particular, when the semiconductor layer 37 is formed of an oxide semiconductor material, it is advantageous to a large area thin film transistor substrate having a large charge capacity due to high charge mobility characteristics. However, the oxide semiconductor material preferably further includes an etch stopper (ES) on the upper surface for protection from the etchant to ensure the stability of the device. Specifically, the etch stopper ES may be formed to protect the semiconductor layer 37 from the etching solution flowing through the separated portion between the source electrode 25 and the drain electrode 35.

One end of the gate line 13 includes a gate pad 17 for receiving a gate signal from the outside. The gate pad 17 contacts the gate pad terminal 19 through the gate pad contact hole 71 passing through the gate insulating layer 11 and the passivation layer 41. On the other hand, one end of the data line 23 includes a data pad 27 for receiving a pixel signal from the outside. The data pad 27 contacts the data pad terminal 29 through the data pad contact hole 73 passing through the passivation layer 41.

The pixel electrode 45 is connected to the drain electrode 35 on the gate insulating film 11. The common electrode 55 is formed to overlap the pixel electrode 45 with the passivation layer 41 covering the pixel electrode 45 therebetween. An electric field is formed between the pixel electrode 45 and the common electrode 55 such that liquid crystal molecules arranged in a horizontal direction between the thin film transistor substrate and the color filter substrate rotate by dielectric anisotropy. In addition, the light transmittance through the pixel region is changed according to the degree of rotation of the liquid crystal molecules to implement gray scale.

Hereinafter, the process of manufacturing the FFS type thin film transistor substrate containing the oxide semiconductor by a prior art is demonstrated. 3A to 3G are cross-sectional views taken along the line II ′ of FIG. 1, illustrating a process of manufacturing a conventional FFS type thin film transistor substrate.

The gate metal is deposited on the transparent lower substrate 1. The gate metal is patterned to form a gate element by a first mask process. The gate element includes a gate wiring 13, a gate electrode 15 branching from the gate wiring 13, and a gate pad 17 formed at one end of the gate wiring 13. (FIG. 3A)

On the substrate 1 on which the gate materials are formed, the gate insulating film 11 is entirely coated. Subsequently, an oxide semiconductor material and an insulating material are deposited successively. In the second mask process, the insulating material is patterned to form an etch stopper ES. The etch stopper ES is preferably formed so as to be located at the center of the semiconductor layer to be formed on the gate electrode 15. (FIG. 3B)

In a third mask process, the oxide semiconductor material is patterned to form the semiconductor layer 37. Although not shown in the drawings, the semiconductor layer 37 includes an active layer forming a channel between the source electrode and the drain electrode, and an ohmic contact layer for allowing the source electrode and the drain electrodes to make ohmic contact with the active layer. (FIG. 3C)

A source-drain metal is deposited on the substrate 1 on which the semiconductor layer 37 is formed. In a fourth mask process, the source-drain metal is patterned to form the source-drain element. The source-drain element includes a data line 23 perpendicular to the gate line 13, a data pad 27 formed at one end of the data line 23, and a branch from the data line 23 and the semiconductor layer 37. A source electrode 25 in contact with one side of the substrate, and a drain electrode 35 in contact with the other side of the semiconductor layer 37 and facing the source electrode 25. In particular, the source electrode 25 and the drain electrode 35 are physically separated from each other, but are connected to each other through a semiconductor layer 37 overlapping the gate electrode 15 with the gate insulating layer 11 therebetween. Has

If the etch stopper ES is not present, the semiconductor layer 37 is etched by an etchant that etches between the source electrode 25 and the drain electrode 35 in the process of patterning the source electrode 25 and the drain electrode 35. Back etch occurs. When the semiconductor layer 37 includes an amorphous semiconductor material, the back etch does not significantly affect the characteristics of the device. However, when the semiconductor layer 37 includes an oxide semiconductor material, a back etch may cause a problem in the stability of the device. Therefore, when the channel layer is formed of an oxide semiconductor material, it is preferable to include an etch stopper (ES). (FIG. 3D)

A transparent conductive material such as indium tin oxide (ITO) is deposited on the entire surface of the substrate 1 on which the source-drain element is formed. In a fifth mask process, the transparent conductive material is patterned to form the pixel electrode 45. The pixel electrode 45 is formed to be in contact with a part of the drain electrode 35. The pixel electrode 45 is preferably formed in a substantially rectangular shape in the pixel region formed by the intersection of the gate wiring 13 and the data wiring 23. (FIG. 3E)

The protective film 41 is coated on the entire surface of the substrate 1 on which the pixel electrode 45 is formed. In the sixth mask process, the passivation layer 41 is patterned to form a data pad contact hole 73 exposing a portion of the data pad 27. At the same time, the protective film 41 and the gate insulating film 11 are patterned to form a gate pad contact hole 71 exposing a part of the gate pad 17. (Figure 3f)

A transparent conductive material such as ITO is again deposited on the protective film 41. In the seventh mask process, the transparent conductive material is patterned to form the common electrode 55, the gate pad terminal 19, and the data pad terminal 29. The common electrode 55 is formed to overlap the pixel electrode 45 with the passivation layer 41 therebetween. In particular, it is formed in the shape of rods arranged in parallel at regular intervals. The gate pad terminal 19 contacts the gate pad 17 exposed through the gate pad contact hole 71. The data pad terminal 29 contacts the exposed data pad 27 through the data pad contact hole 73. (Figure 3g)

Subsequently, although not illustrated in the drawing, the thin film transistor substrate on which the pixel electrode 55 and the common electrode 55 are formed is transferred to the alignment layer process chamber to apply the alignment layer. The liquid crystal layer is coated and bonded to the color filter substrate to complete the liquid crystal display panel.

As described above, seven mask processes are used to fabricate a thin film transistor substrate for an FFS type liquid crystal display device including an oxide semiconductor. When manufacturing a thin film transistor substrate of the FFS method including an amorphous semiconductor that does not require an etch stopper (ES), at least six mask processes are required. The more the mask process, the more complicated the manufacturing process and the higher the possibility of defects. Therefore, it is an important problem to simplify the process of manufacturing the thin film transistor substrate which includes the largest number of components in the liquid crystal display device.

An object of the present invention is designed to overcome the above problems, a method of manufacturing a fringe field switching thin film transistor substrate comprising an oxide semiconductor layer in a six-mask process and a fringe field switching comprising an oxide semiconductor layer by the method The present invention provides a thin film transistor substrate.

In order to achieve the object of the present invention, a fringe field switching type thin film transistor substrate including an oxide semiconductor layer according to the present invention, the gate wiring in which a transparent conductive layer and a metal layer are laminated on the substrate, and the transparent conductive layer is exposed Common electrode; A gate insulating layer covering the gate electrode and the common electrode; A data line orthogonal to the gate line on the gate insulating film; A thin film transistor formed on a portion of the gate insulating layer where the gate line and the data line cross each other; A passivation layer covering the thin film transistor; A pixel electrode connected to the thin film transistor through a drain contact hole penetrating through the passivation layer and overlapping the common electrode in a plurality of bar shapes disposed at predetermined intervals on the passivation layer; And a shield line formed on the passivation layer and overlapping the data line.

A common wiring crossing the central portion of the common electrode and traveling in parallel with the gate wiring, wherein the transparent conductive layer and the metal layer are stacked; And a shield wiring contact hole penetrating the gate insulating film and the passivation layer to expose a portion of the common wiring, wherein the shield wiring is connected to the common wiring through the shield wiring contact hole.

A gate pad formed on one end of the gate wiring; A data pad formed at one end of the data line; A gate pad contact hole penetrating the gate insulating layer and the passivation layer covering the gate pad and exposing a portion of the gate pad; A data pad contact hole penetrating the passivation layer covering the data pad and exposing a portion of the data pad; A gate pad terminal contacting the gate pad through the gate pad contact hole; And a data pad terminal contacting the data pad through the data pad contact hole.

The thin film transistor may include a gate electrode branched from the gate line; A semiconductor layer overlapping the gate electrode on the gate insulating layer; A source electrode branched from the data line and in contact with one side of the semiconductor layer, and a drain electrode contacting the other side of the semiconductor layer and spaced apart from the source electrode at a predetermined price and connected to the pixel electrode through the drain contact hole. ; And an etch stopper interposed between the semiconductor layer, the source electrode, and the drain electrode.

The semiconductor layer is characterized in that it comprises an oxide semiconductor material.

In addition, in the method of manufacturing a fringe field switching thin film transistor substrate including an oxide semiconductor layer according to the present invention, a transparent conductive layer and a gate metal layer are continuously deposited on a substrate and patterned with a halftone mask to form the transparent conductive layer and the A first mask process of forming a gate element on which a gate metal layer is stacked and a common electrode to which the transparent conductive layer is exposed; A second mask process of sequentially depositing a gate insulating film, a semiconductor material, and an insulating material on the gate element and the common electrode, and patterning the insulating material to form an etch stopper; A third mask process of patterning the semiconductor material to form a semiconductor layer; A fourth mask process of forming a thin film transistor including a source electrode and a drain electrode by depositing and patterning a source-drain metal layer on the substrate on which the etch stopper and the semiconductor layer are formed; A fifth mask process of depositing and patterning a passivation layer on the substrate on which the thin film transistor is formed to form a drain contact hole exposing the drain electrode; A sixth mask process of depositing and patterning a transparent conductive material on the passivation layer to form a pixel electrode connected to the drain electrode through the drain contact hole and overlapping the common electrode in a plurality of bar shapes disposed at predetermined intervals; It includes.

The first mask process may include a gate wiring running in a horizontal direction of the substrate, a gate electrode branching from the gate wiring, a gate pad connected to one end of the gate wiring, and a center portion of the common electrode. Form the gate element comprising common wiring running in parallel with the gate; The fourth mask process may further include forming a data line connecting the source electrode and running in the longitudinal direction of the substrate and a data pad connected to one end of the data line; The sixth mask process may further include a shield line overlapping and covering the data line on the passivation layer.

The third mask process may be performed by etching only the semiconductor material using a halftone mask to form the semiconductor layer, and etching the semiconductor material and the gate insulating layer to expose a portion of the gate pad. Forming a shield wiring contact hole exposing a portion of the wiring; The fifth mask process may include a gate pad contact hole exposing a portion of the gate pad by patterning the passivation layer, a shield wire contact hole exposing a portion of the common wiring again, and a data pad contact exposing a portion of the data pad. It is characterized by forming a hole.

The fifth mask process may further include forming a data pad contact hole exposing a portion of the data pad when the protective layer is patterned to form the drain contact hole exposing a portion of the drain electrode; The gate insulating layer may be successively patterned to further form a gate pad contact hole exposing a part of the gate pad and a shield wiring contact hole exposing a part of the common wiring.

The semiconductor material patterned in the third mask process may include an oxide semiconductor material, and the semiconductor layer may include an oxide semiconductor layer.

The fringe field switching thin film transistor substrate including the oxide semiconductor layer according to the present invention comprises six mask processes. Compared with the prior art, the number of mask processes is reduced, so that manufacturing cost is low and manufacturing time is shortened. In addition, when forming the pixel electrode formed on the uppermost layer, the shield layer for shielding the data line may be formed together, and the shield layer may be connected to the common line disposed below through the contact hole. Accordingly, the present invention provides a fringe field switching thin film transistor substrate including an oxide semiconductor layer having excellent image quality in which light leakage due to parasitic capacitance generated between the data line and the pixel electrode does not occur.

1 is a plan view showing a thin film transistor substrate included in a conventional FFS type liquid crystal display device.
FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along the line II ′.
3A to 3G are cross-sectional views taken along line II ′ of FIG. 1, illustrating a process of manufacturing a FFS type thin film transistor substrate according to the prior art.
4 is a plan view illustrating a thin film transistor substrate included in an FFS type liquid crystal display device including an oxide semiconductor layer according to the present invention;
FIG. 5 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 4 taken along the line II-II ′.
6A to 6F are cross-sectional views taken along line II-II 'and III-III' of FIG. 4 to illustrate cross-sectional views illustrating a process of manufacturing a FFS type thin film transistor substrate including an oxide semiconductor layer according to the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like numbers refer to like elements throughout. In the following description, when it is determined that the detailed description of the known technology or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

4 is a plan view illustrating a thin film transistor substrate included in an FFS type liquid crystal display device including an oxide semiconductor layer according to the present invention. FIG. 5 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 4 taken along the line II-II ′.

4 and 5, the thin film transistor substrate according to the present invention includes a gate line GL and a data line DL intersecting each other with a gate insulating layer GI interposed therebetween on a lower substrate SUB, and each intersection thereof. The formed thin film transistor T is provided. In addition, the thin film transistor substrate defines a pixel area with a cross structure of the gate line GL and the data line DL. The pixel region includes the pixel electrode PXL and the common electrode COM formed with the gate insulating film GI and the protective film PAS interposed therebetween so as to form a fringe field. Here, the common electrode COM has a substantially rectangular shape corresponding to the pixel region, and the pixel electrode PXL is formed in a plurality of parallel band shapes.

The common electrode COM branches from the common line CL arranged in parallel with the gate line GL. The common electrode COM receives a reference voltage (or a common voltage) for driving the liquid crystal through the common line CL.

The thin film transistor T keeps the pixel signal of the data line DL charged in the pixel electrode PXL in response to the gate signal of the gate line GL. To this end, the thin film transistor T faces the gate electrode G branched from the gate line GL, the source electrode S branched from the data line DL, and the source electrode S, and faces the pixel electrode PXL. And an oxide semiconductor layer A overlapping the gate electrode G on the gate insulating layer GI and forming a channel between the source electrode S and the drain electrode D on the gate insulating layer GI. . It may further include an ohmic contact layer for ohmic contact between the semiconductor layer (T) and the source electrode (S) and between the semiconductor layer (A) and the drain electrode (D).

In particular, when the semiconductor layer A is formed of an oxide semiconductor material, it is advantageous for a large area thin film transistor substrate having a large charge capacity due to its high charge mobility property. However, the oxide semiconductor material preferably further includes an etch stopper (ES) on the upper surface for protection from the etchant to ensure the stability of the device. Specifically, the etch stopper ES is formed so as to protect the oxide semiconductor layer A from the etching liquid flowing through the separated portion between the source electrode S and the drain electrode D. FIG.

A gate pad GP for receiving a gate signal from the outside is formed at one end of the gate line GL. The gate pad GP contacts the gate pad terminal GP through the gate pad contact hole GPH passing through the gate insulating layer GI and the passivation layer PAS. Meanwhile, one end of the data line DL includes a data pad DP for receiving a pixel signal from the outside. The data pad DP contacts the data pad terminal DPT through the data pad contact hole DPH passing through the passivation layer PAS.

The pixel electrode PXL is connected to the drain electrode D through the drain contact hole DH on the passivation layer PAS. The common electrode COM is formed to overlap the pixel electrode PXL with the gate insulating layer GI and the passivation layer PAS covering the pixel electrode PXL interposed therebetween. An electric field is formed between the pixel electrode PXL and the common electrode COM, and the liquid crystal molecules arranged in the horizontal direction between the thin film transistor substrate and the color filter substrate rotate by dielectric anisotropy. In addition, the light transmittance through the pixel region is changed according to the degree of rotation of the liquid crystal molecules to implement gray scale.

Hereinafter, the process of manufacturing the FFS type thin film transistor substrate containing the oxide semiconductor by this invention is demonstrated. 6A through 6F are cross-sectional views taken along the line II-II 'and III-III' of FIG. 4, illustrating a process of manufacturing an FFS type thin film transistor substrate according to the present invention.

The transparent conductive material 100 and the gate metal 200 are successively deposited on the transparent substrate SUB. The transparent conductive material 100 includes indium tin oxide (ITO) or indium zinc oxide (IZO). The gate metal 200 may include a low resistance metal material such as aluminum (Al) or copper (Cu). In the first mask process, the transparent conductive material 100 and the gate metal 200 are patterned to form a common electrode COM and a gate element. In particular, the common electrode COM is formed to include only the transparent conductive material 100, and the gate element is formed to have a structure in which the transparent conductive material 100 and the gate metal 200 are stacked. Since the thickness to be etched is different, it is preferable to use a half-tone mask in the first mask process. The gate element includes a gate line GL, a gate electrode G branching from the gate line GL, a gate pad GP formed at one end of the gate line GL, and a central portion of the common electrode COM. The common wiring CL running in parallel with the gate wiring is included. (FIG. 6A)

The gate insulating film GI is entirely coated on the substrate SUB on which the common electrode COM and the gate element are formed. Subsequently, an oxide semiconductor material (SEM) and an insulating material are deposited successively. In the second mask process, the insulating material is patterned to form an etch stopper ES. The etch stopper ES is preferably formed at a central portion of the semiconductor layer A to be formed on the gate electrode G. (Fig. 6B)

In a third mask process, an oxide semiconductor material (SEM) is patterned to form a semiconductor layer (A). At the same time, the gate insulating layer GI covering the gate pad GP is continuously patterned to form the gate pad contact hole GPH exposing the gate pad GP. In addition, a shield wiring contact hole SSH exposing a part of the common wiring CL is formed. As described above, since the oxide semiconductor material SEM and the gate insulating film GI are selectively etched in the third mask process, only a halftone mask is preferably used. Although not shown in the drawings, the semiconductor layer A may include an active layer forming a channel between the source electrode and the drain electrode, and an ohmic contact layer that allows the source electrode and the drain electrodes to make ohmic contact with the active layer. (FIG. 6C)

The source-drain metal is deposited on the substrate SUB on which the semiconductor layer A is formed. In a fourth mask process, the source-drain metal is patterned to form the source-drain element. The source-drain element includes a data line DL perpendicularly intersecting with the gate line GL, a data pad DP formed at one end of the data line DL, and a branch from the data line DL, and the semiconductor layer A. A source electrode S in contact with one side of the substrate, and a drain electrode D in contact with the other side of the semiconductor layer A and facing the source electrode S. In particular, the source electrode S and the drain electrode D are physically separated from each other, but are connected to each other through a semiconductor layer A overlapping the gate electrode G with the gate insulating layer GI therebetween. Has In addition, since the common wiring CL runs in parallel with the gate wiring GL, the data wiring DL has a structure in which the common wiring CL intersects with the gate insulating film GI therebetween.

If the etch stopper ES is not present, the semiconductor layer A is etched by an etchant that etches the source electrode S and the drain electrode D in the process of patterning the source electrode S and the drain electrode D. FIG. Back etch occurs. When the semiconductor layer (A) contains an amorphous semiconductor material, even if a back etch occurs, the characteristics of the device are not greatly affected. However, in the case where the semiconductor layer A includes the oxide semiconductor material, if back etching occurs, a problem may arise in the stability of the device. Therefore, when the channel layer is formed of an oxide semiconductor material, it is preferable to include an etch stopper (ES). (FIG. 6D)

A passivation layer (PAS) such as silicon nitride (SiNx) or silicon oxide (SiOx) is deposited on the entire surface of the substrate SUB on which the source-drain element is formed. The passivation layer PAS is patterned by a fifth mask process to expose the drain electrode D, the drain contact hole DH exposing the drain electrode D, the gate pad contact hole GPH exposing the gate pad GP, and the data pad DP. A data pad contact hole DPH is formed to expose A. In addition, a shield wiring contact hole SSH exposing a part of the common wiring CL is formed. (Fig. 6E)

A transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the substrate SUB on which the contact holes are formed. In a sixth mask process, the transparent conductive material is patterned to form the pixel electrode PXL. The pixel electrode PXL contacts the drain electrode D through the drain contact hole DH. The pixel electrode PXL is preferably formed to have a shape in which a plurality of rod-shaped electrodes parallel to each other are arranged at regular intervals in a pixel region formed by crossing the gate line GL and the data line DL. Do. At the same time, the gate pad terminal GPT contacts the gate pad GP through the gate pad contact hole GPH and the data pad terminal DPT contacts the data pad DP through the data pad contact hole DPH. To form. Then, a shield wiring SH completely overlapping with the data wiring DL is formed on the passivation film PAS covering the data wiring DL. The shield wiring SH is connected to the common wiring CL through the shield wiring contact hole SSH. As a result, the common voltage is applied to the shield wiring SH, and serves to shield the data wiring DL. (Fig 6f)

In the manufacturing process described above with reference to the drawings, a third mask process and a fifth mask may be performed using the gate pad contact hole GPH exposing the gate pad GP and the shield wiring contact hole SSH exposing a part of the common wiring CL. The process was formed twice. That is, in the third mask process, the gate insulating layer GI is patterned to form the gate pad contact hole GPH and the shield wiring contact hole SSH. In the third mask process, since the semiconductor layer A is formed, the semiconductor layer A and the contact holes GPH and SSH are formed together using a half tone mask. In the fifth mask process, when the passivation layer PAS is patterned to form the data pad contact hole DPH exposing the data pad DP, the gate pad contact hole GPH and the shield wiring contact hole are once again formed. SSH).

However, for convenience, in the third mask process, only the semiconductor material (SEM) is dismissed to form only the semiconductor layer (A), and in the fifth mask process, the data pad contact hole (DPH), the gate pad contact hole (GPH), In addition, the shield wiring contact hole SSH may be formed. Which method to choose may be decided at the convenience of the manufacturer.

As described above, the present invention provides a method of manufacturing a thin film transistor substrate of the FFS type to protect the oxide semiconductor layer (A) with an etch stopper (ES) in six mask processes. Further, a method of manufacturing a thin film transistor substrate for shielding the data line DL with a shield line SH having the same voltage as the common line CL is provided.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the present invention should not be limited to the details described in the detailed description but should be defined by the claims.

7, T: thin film transistor 1, SUB: substrate
13, GL: gate line 53, CL: common line
23, DL: data line 45, PXL: pixel electrode
55, COM: common electrode 17, GP: gate pad
27, DP: data pad 19, GPT: gate pad terminal
29, DPT: Data pad terminal 71, GPH: Gate pad contact hole
73, DPH: Data pad contact hole SSH: Contact hole
15, G: gate electrode 25, S: source electrode
35, D: drain electrode 37, A: semiconductor layer
11, GI: gate insulating film 41, PAS: protective film
DH: Drain contact hole ES: Etch stopper
SEM: Oxide Semiconductor Material
100: transparent conductive material 200: gate metal material

Claims (10)

A gate wiring in which a transparent conductive layer and a metal layer are stacked on a substrate, and a common electrode to which the transparent conductive layer is exposed;
A gate insulating layer covering the gate electrode and the common electrode;
A data line orthogonal to the gate line on the gate insulating film;
A thin film transistor formed on a portion of the gate insulating layer where the gate line and the data line cross each other;
A passivation layer covering the thin film transistor;
A pixel electrode connected to the thin film transistor through a drain contact hole penetrating through the passivation layer and overlapping the common electrode in a plurality of bar shapes disposed at predetermined intervals on the passivation layer; And
And a shield line formed on the passivation layer and overlapping the data line to cover the data line.
The method of claim 1,
A common wiring crossing the central portion of the common electrode and traveling in parallel with the gate wiring, wherein the transparent conductive layer and the metal layer are stacked; And,
A shield wiring contact hole penetrating the gate insulating film and the protective film to expose a portion of the common wiring;
The shield wiring is fringe field switching thin film transistor substrate, characterized in that connected to the common wiring through the shield wiring contact hole.
The method of claim 1,
A gate pad formed on one end of the gate wiring;
A data pad formed at one end of the data line;
A gate pad contact hole penetrating the gate insulating layer and the passivation layer covering the gate pad and exposing a portion of the gate pad;
A data pad contact hole penetrating the passivation layer covering the data pad and exposing a portion of the data pad;
A gate pad terminal contacting the gate pad through the gate pad contact hole; And
And a data pad terminal contacting the data pad through the data pad contact hole.
The thin film transistor according to claim 1,
A gate electrode branched from the gate wiring;
A semiconductor layer overlapping the gate electrode on the gate insulating layer;
A source electrode branched from the data line and in contact with one side of the semiconductor layer, and a drain electrode contacting the other side of the semiconductor layer and spaced apart from the source electrode at a predetermined price and connected to the pixel electrode through the drain contact hole. ; And
And a etch stopper interposed between the semiconductor layer, the source electrode, and the drain electrode.
The method of claim 4, wherein
The semiconductor layer is a fringe field switching thin film transistor substrate comprising an oxide semiconductor material.
A first mask process of sequentially depositing a transparent conductive layer and a gate metal layer on a substrate and patterning with a halftone mask to form a gate element on which the transparent conductive layer and the gate metal layer are stacked and a common electrode to which the transparent conductive layer is exposed;
A second mask process of sequentially depositing a gate insulating film, a semiconductor material, and an insulating material on the gate element and the common electrode, and patterning the insulating material to form an etch stopper;
A third mask process of patterning the semiconductor material to form a semiconductor layer;
A fourth mask process of depositing and patterning a source-drain metal layer on the substrate on which the etch stopper and the semiconductor layer are formed to form a thin film transistor including a source electrode and a drain electrode;
A fifth mask process of depositing and patterning a passivation layer on the substrate on which the thin film transistor is formed to form a drain contact hole exposing the drain electrode; And
Depositing and patterning a transparent conductive material on the passivation layer to form a pixel electrode connected to the drain electrode through the drain contact hole and overlapping the common electrode in a plurality of bar shapes disposed at predetermined intervals; A fringe field switching thin film transistor substrate manufacturing method comprising a.
The method according to claim 6,
The first mask process may include a gate wiring running in a horizontal direction of the substrate, a gate electrode branching from the gate wiring, a gate pad connected to one end of the gate wiring, and a center portion of the common electrode. Form the gate element comprising common wiring running in parallel with the gate;
The fourth mask process may further include forming a data line connecting the source electrode and running in the longitudinal direction of the substrate and a data pad connected to one end of the data line;
In the sixth mask process, a shield line covering the data line and overlapping the data line is further formed on the passivation layer.
The method of claim 7, wherein
The third mask process may be performed by etching only the semiconductor material using a halftone mask to form the semiconductor layer, and etching the semiconductor material and the gate insulating layer to expose a portion of the gate pad. Forming a shield wiring contact hole exposing a portion of the wiring;
The fifth mask process may include a gate pad contact hole exposing a portion of the gate pad by patterning the passivation layer, a shield wire contact hole exposing a portion of the common wiring again, and a data pad contact exposing a portion of the data pad. A method of manufacturing a thin film transistor substrate having a fringe field switching method, wherein holes are formed.
The method of claim 7, wherein the fifth mask process,
Forming a data pad contact hole exposing a portion of the data pad when the protective layer is patterned to form the drain contact hole exposing a portion of the drain electrode;
A method of manufacturing a fringe field switching thin film transistor substrate, further comprising forming a gate pad contact hole exposing a portion of the gate pad and a shield wiring contact hole exposing a portion of the common wiring by sequentially patterning the gate insulating layer. .
The method according to claim 6,
The semiconductor material patterned in the third mask process includes an oxide semiconductor material, wherein the semiconductor layer comprises an oxide semiconductor layer.

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