KR101950826B1 - Thin film transistor substrate and method of fabricating the same - Google Patents

Abstract

The present invention provides a thin film transistor substrate capable of preventing afterimage and a manufacturing method thereof.
A thin film transistor substrate according to the present invention includes: a gate line formed on a substrate; A data line crossing the gate line and the gate insulating film to form a pixel region; A thin film transistor connected to the gate line and the data line; A pixel electrode connected to the thin film transistor and formed of a transparent conductive film on the pixel region; A common electrode formed in the pixel region to form a fringe electric field with the pixel electrode; A common line formed of a metal having a lower resistivity than the transparent conductive film and connected to the common electrode; An alignment contact hole that exposes the common line through the gate insulating film and a protective film formed to cover the thin film transistor; And an alignment film which is in direct contact with the common line exposed through the alignment contact hole.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a thin film transistor substrate,

The present invention relates to a thin film transistor substrate capable of preventing afterimage and a manufacturing method thereof.

2. Description of the Related Art In general, a liquid crystal display (LCD) is one of flat panel display devices for displaying an image using a liquid crystal, and is thin and light compared to other display devices, has advantages of low driving voltage and low power consumption, It is widely used throughout.

Such a liquid crystal display device includes a liquid crystal display panel having a thin film transistor substrate and a color filter substrate facing each other with a liquid crystal therebetween.

The color filter substrate comprises a black matrix formed on the upper substrate for preventing light leakage, a color filter for color implementation, and an upper alignment film formed thereon for liquid crystal alignment.

The thin film transistor substrate includes a gate line and data lines formed on a lower substrate, a thin film transistor formed as a switching element at each intersection of gate lines and data lines, a pixel electrode formed in a unit of a liquid crystal cell and connected to the thin film transistor, A common electrode which forms an electric field with the electrodes, and an alignment film coated thereon. Here, the thin film transistor supplies the pixel electrode with a video signal supplied to the data line in response to the scan signal supplied to the gate line.

In the conventional liquid crystal display panel, charges generated during driving are accumulated in an alignment film, a protective film, and a gate insulating film. In the conventional liquid crystal display panel, the electric field accumulated between the pixel electrode and the common electrode is distorted due to the charges accumulated in the alignment film, the protective film, and the gate insulating film, resulting in a problem of a residual image.

In order to solve the above problems, the present invention provides a thin film transistor substrate and a method of manufacturing the same that can prevent afterimage.

According to an aspect of the present invention, there is provided a thin film transistor substrate comprising: a gate line formed on a substrate; A data line crossing the gate line and the gate insulating film to form a pixel region; A thin film transistor connected to the gate line and the data line; A pixel electrode connected to the thin film transistor and formed of a transparent conductive film on the pixel region; A common electrode formed in the pixel region to form a fringe electric field with the pixel electrode; A common line formed of a metal having a lower resistivity than the transparent conductive film and connected to the common electrode; An alignment contact hole that exposes the common line through the gate insulating film and a protective film formed to cover the thin film transistor; And an alignment film which is in direct contact with the common line exposed through the alignment contact hole.

Here, the common line may be formed of the same material on a substrate that is coplanar with the gate line, the pixel electrode may be formed on a substrate that is coplanar with the common line, and the common electrode may be formed to cover the thin film transistor And is formed on the protective film.

In addition, the thin film transistor substrate of the present invention is further provided with a contour common pattern which is formed to be connected to the common line in an outer region of the substrate, and which is exposed through the alignment contact hole and connected to the alignment film.

According to an aspect of the present invention, there is provided a method of manufacturing a thin film transistor substrate including a gate line, a gate electrode connected to the gate line, a common line parallel to the gate line, Forming a driving electrode on the substrate; A source electrode connected to the data line, a drain electrode connected to the pixel electrode, and a source electrode connected to the data line, wherein the gate electrode, the gate electrode, ; ≪ / RTI > Forming a remaining one of the pixel electrode and the common electrode in the pixel region; Forming an aligned contact hole exposing the common line; And forming an alignment layer in contact with the common line exposed through the alignment contact hole, wherein the common line is formed of a metal having a specific resistance lower than that of the pixel electrode formed of a transparent conductive film.

The present invention can prevent the afterimage because the discharge characteristic can be improved by direct contact between the alignment layer and the common line formed of a metal having a lower resistivity than the transparent conductive metal.

1 is a plan view showing a thin film transistor substrate according to the present invention.
2 is a sectional view showing a thin film transistor substrate taken along the line " I-I '" and the line "II-II'"
3 is a sectional view showing another embodiment of a thin film transistor substrate taken along the line " I-I " in Fig. 1 and the line " II-II "
4 is a plan view showing an outer region of the thin film transistor substrate shown in FIG.
5 is a cross-sectional view showing a thin film transistor substrate taken along the line " III-III " in Fig.
6A to 6E are cross-sectional views illustrating a method of manufacturing the TFT substrate shown in FIG.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

FIG. 1 is a plan view of a thin film transistor substrate according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view taken along a line I-I 'and a line II-II' Sectional view.

The thin film transistor substrate shown in FIGS. 1 and 2 includes a gate line 102 and a data line 104 crossing the lower substrate 101 with a gate insulating film 112 therebetween, a gate line 102 And a common electrode 136 formed to form a fringe field with the pixel electrode 122 in the pixel region. The pixel electrode 122 is connected to the thin film transistor connected to the intersection of the data line 104 and the data line 104, A common line 132 connected to the common electrode 136 and an alignment film 140 connected to the common line 132. [

The gate line 102 supplies a scan signal from a gate driver (not shown), and the data line 104 supplies a video signal from a data driver (not shown). The gate line 102 and the data line 104 intersect each other with a gate insulating film 112 therebetween to define respective pixel regions.

The thin film transistor causes the video signal on the data line 104 to be charged and held in the pixel electrode 122 in response to the scan signal of the gate line 102. For this, the thin film transistor has a gate electrode 106 connected to the gate line 102, a source electrode 108 connected to the data line 104, and a source electrode 108 connected to the pixel electrode 122, An active layer 114 and a source electrode 108 overlapping the gate line 102 with the gate insulating film 112 sandwiched therebetween and forming a channel between the source electrode 108 and the drain electrode 110, And an ohmic contact layer 116 formed on the active layer 114 except for the channel region for ohmic contact with the drain electrode 110. The semiconductor pattern including the active layer 114 and the ohmic contact layer 116 is formed so as to overlap with the data line 104 as well.

The pixel electrode 122 is formed in a plate shape on the substrate 101 and is formed of a transparent conductive layer. The pixel electrode 122 is exposed through the pixel contact hole 120 passing through the gate insulating layer 112 and the passivation layer 118. The pixel electrode 122 exposed through the pixel contact hole 120 is exposed through the pixel contact hole 120, Drain electrode 110 and the pixel connection unit 124. [0064] The pixel electrode 122 overlaps the common electrode 136 with the gate insulating layer 112 and the protective layer 118 interposed therebetween to form a fringe field in each pixel region. That is, when a video signal is supplied through the thin film transistor, the pixel electrode 122 forms a fringe field with the common electrode 136 to which the common voltage is supplied, thereby forming liquid crystal molecules (liquid crystal molecules) arranged horizontally between the thin film transistor substrate and the color filter substrate Are rotated by dielectric anisotropy. The transmittance of light passing through the pixel region is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing the gradation.

The common electrode 136 is formed in each pixel region and is connected to the common line 132. The slit 138 of the common electrode 136 is symmetric with respect to the center line of each pixel region parallel to the gate line 102, and is formed in an oblique direction. Accordingly, the liquid crystal molecules are arranged symmetrically with respect to the slit 138 by the fringing electric field formed between the common electrode 136 and the pixel electrode 122, so that the multi-domain can be formed and the viewing angle can be improved .

The common line 132 supplies a reference voltage for driving the liquid crystal, that is, a common voltage to each common electrode 136. The common line 132 is formed in parallel with the gate line 102. The common line 132 is exposed through the common contact hole 130 penetrating the gate insulating film 112 and the protective film 118 and is connected to the common electrode 136.

Here, the common line 132 is formed on the substrate 101 together with the gate electrode 106 and the gate line 102, as shown in FIG. 2, in at least two or more multi-layer structures. 2, the common line 132, the gate electrode 106, and the gate line 102 are formed by a first conductive layer 106a using a transparent conductive layer and a second conductive layer 106b using a first conductive layer 106a, And a second conductive layer 106b using a metal having a lower resistivity than the first conductive layer 106b. In this case, ITO, TO, IZO and ITZO are used for the first conductive layer 106a and low resistance metals such as Cu, Mo, Al, Cu alloy, Mo alloy and Al alloy are used for the second conductive layer 106b .

In addition, the common line 132 may be formed on the substrate 101 together with the gate electrode 106 and the gate line 102 as shown in FIG. 3, such as Cu, Mo, Al, Cu alloy, Mo alloy, Al alloy, Layer structure using a resistive metal.

An alignment film 140 is formed for liquid crystal initial alignment on the substrate 101 on which the common electrode 136 is formed. The alignment film 140 is in contact with the exposed common line 132 through the alignment contact hole 142. The alignment contact hole 142 penetrates the gate insulating film 112 and the passivation film 118 and is formed to be connected to the opening 144 of the common electrode 136. Thus, the charges accumulated in the alignment film 140, the gate insulating film 112, and the protective film 118 are discharged to the outside through the common line 132. In particular, the alignment layer 140 may be directly connected to the common line 132 formed of a metal having a lower resistivity than that of the transparent conductive metal as shown in Table 1, thereby improving the discharge characteristics.

Transparent conductive metal (ITO) Low resistance metal (Cu) Resistivity 1.95 Ωm 0.025 Ωm

4 and 5, the alignment film 140 is formed on the color filter substrate 160 such that the gate pad 164 and the outer common pattern 146 formed in the substrate outer region, in which the data pad 168 is exposed, And the alignment contact hole 142, as shown in FIG. At this time, the outline common pattern 146 is formed so as not to affect the adjacent gate link 162, the data link 166, the gate pad 164, and the data pad 168. In particular, the outline common pattern 146 is formed on the gate line 162 and the gate pad 164 to prevent the gate line 162 and the gate pad 164, which are coplanar with the outline common pattern 146, As shown in FIG.

The outline common pattern 146 is formed to be electrically connected to the common line 132 formed in the display area. This makes it possible to further improve the discharge characteristics of the charges accumulated in the alignment film 140 since the area in which the common line 132 and the outer common pattern 146 are in contact with the alignment film 140 is widened.

6A to 6E are cross-sectional views illustrating a method of manufacturing the TFT substrate shown in FIG. Hereinafter, a method of manufacturing a thin film transistor substrate according to the present invention will be described with reference to FIGS. 1, 4, and 5. FIG.

6A, a first mask process includes a common line 132, a gate line 102, a gate electrode 106, a contour common pattern 146, and a pixel electrode 122 on a lower substrate 101 A first conductive pattern is formed. Specifically, the first and second conductive layers 106a and 106b are stacked on the lower substrate 101 through a deposition method such as a sputtering method. As the first conductive layer 106a, a transparent conductive material such as ITO, TO, IZO or ITZO may be used. As the second conductive layer 106b, a metal such as Mo, Ti, Cu, AlNd, Al, Cr, Materials are used as a single layer, or used as a multi-layer structure using them. Then, the first and second conductive layers 106a and 106b are patterned using a photoresist pattern formed through a photolithography process using a halftone mask or a slit mask as a mask to form the common line 132, The pixel electrode 122 made of only the first conductive layer 106a and the line 102, the gate electrode 106 and the outer common pattern 146 are formed.

On the other hand, it is exemplified that the common line 132, the gate line 102, the gate electrode 106, the outer common pattern 146 and the pixel electrode 122 are simultaneously formed through the patterning process using the halftone mask or the slit mask The common line 132, the gate line 102, the gate electrode 106, the outer common pattern 146, and the pixel electrode 122 may be formed through two mask processes. That is, the common line 132, the gate line 102, the gate electrode 106, and the common frame pattern 146 are first formed through a patterning process using a low-resistance metal layer, and then patterned using a transparent conductive layer The pixel electrode 122 may be formed. Therefore, the common line 132, the gate line 102, the gate electrode 106, and the common frame pattern 146 are formed in a single-layer structure made of a low-resistance metal layer, and the pixel electrode 122 is a single layer .

6B, a gate insulating layer 112 is formed on a lower substrate 101 on which a first conductive pattern is formed, and an active layer 114 and an ohmic contact layer 116, and a second conductive pattern including the data line 104, the source electrode 108, and the drain electrode 110 are formed.

Specifically, an amorphous silicon layer doped with a gate insulating layer 112, an amorphous silicon layer, and impurities (n + or p +) is sequentially formed on a lower substrate 101 on which a first conductive pattern is formed by a deposition method such as PECVD, And a source / drain metal layer is formed thereon by a deposition method such as sputtering. As the gate insulating film 112, an inorganic insulating material such as SiOx, SiNx, or the like is used. As the source / drain metal layer, a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, or an alloy thereof may be used as a single layer, or may be used as a multi-layer structure using them. Then, the amorphous silicon layer, the amorphous silicon layer doped with the impurity (n + or p +) and the source / drain metal layer are patterned by using the photoresist pattern formed through the photolithography process using the halftone mask or the slit mask as a mask, An active layer 114, an ohmic contact layer 116, a data line 104, a source electrode 108, and a drain electrode 110 are formed on a substrate 112.

6C, a protective film 118 having a common contact hole 130, an alignment contact hole 142, and a pixel contact hole 120 is formed on a gate insulating film 112 having a second conductive pattern formed by a third mask process. .

Specifically, the passivation layer 118 is formed on the gate insulating layer 112 on which the second conductive pattern is formed by a method such as PECVD, spin coating, or spinless coating. As the protective film 118, an inorganic insulating material such as the gate insulating film 112 may be used, or an organic insulating material may be used. The protective film 118 and the gate insulating film 112 are patterned by the photolithography process and the etching process using the third photomask on the protective film 118 to form the common contact hole 130, the alignment contact hole 142, (120) is formed. The common contact hole 130 and the alignment contact hole 142 penetrate the gate insulating layer 112 and the passivation layer 118 to expose the common line 132. The pixel contact hole 120 exposes the drain electrode 110 and the pixel electrode 122 through the gate insulating layer 112 and the passivation layer 118.

Referring to FIG. 6D, in a fourth mask process, a third electrode 136, including a common electrode 136 having a slit 138 and an opening 144, a pixel connection 124, and a common connection 134 on the passivation layer 118, A conductive pattern is formed.

Specifically, a transparent conductive layer is formed on the protective film 118 by a deposition method such as sputtering. As the transparent conductive layer, ITO, TO, IZO, ITZO or the like similar to the first conductive layer 106a of the first conductive pattern may be used. Then, the transparent conductive layer is patterned by the photolithography process and the etching process using the fourth photomask to form the common electrode 136 having the opening 144, and the common connection portion 124 including the pixel connection portion 124 and the common connection portion 134 A third conductive pattern is formed. The opening 144 of the common electrode 136 is formed so as to overlap the alignment contact hole 142 with a wider width than the alignment contact hole 142. [ The pixel connection part 124 is connected to the drain electrode 110 and the pixel electrode 122 exposed through the pixel contact hole 120. Accordingly, the pixel electrode 122 is connected to the drain electrode 110 through the pixel connection portion 124.

Referring to FIG. 6E, an alignment layer 140 is formed on a substrate 101 on which a third conductive pattern is formed.

Specifically, the alignment film 140 is formed by applying polyimide on the substrate 101 on which the third conductive pattern is formed and then rubbing. The alignment film 140 is connected to the low resistance metal of the common line 132 through the alignment contact hole 142 and the opening 144 of the common electrode 136.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

102: gate line 104: data line
106: gate electrode 108: source electrode
110: drain electrode 112: gate insulating film
114: active layer 116: ohmic contact layer
118: protective layer 120,130,142: contact hole
122: pixel electrode 132: common line
136: common electrode 138: slit
140: Orientation layer 146: Outline common pattern

Claims (8)

A substrate having a display area and an outer area;
A gate line formed on the substrate;
A data line crossing the gate line and the gate insulating film;
A thin film transistor connected to the gate line and the data line;
A pixel electrode connected to the thin film transistor and formed of a transparent conductive film;
A common electrode that forms a fringe electric field with the pixel electrode;
A common line formed of a metal having a lower resistivity than the transparent conductive film and connected to the common electrode;
An alignment contact hole exposing the common line;
And an alignment film in direct contact with the common line disposed under the common electrode in the display region. The method according to claim 1,
The common line is formed of the same material on a substrate which is coplanar with the gate line,
Wherein the pixel electrode is disposed on a substrate which is coplanar with the common line,
Wherein the common electrode is disposed on a protective film covering the thin film transistor. The method according to claim 1,
And a peripheral common pattern connected to the common line and connected to the alignment layer in the outer area. Providing a substrate having a display area and an outer area;
Forming a gate electrode, a gate electrode connected to the gate line, a common line parallel to the gate line, and a pixel electrode and a common electrode on the substrate;
Forming a semiconductor pattern, a data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode on the gate line, the gate electrode, and the substrate on which the driving electrode is formed, ;
Forming a driving electrode of the other one of the pixel electrode and the common electrode;
Forming an alignment contact hole exposing the common line;
Forming an alignment film in direct contact with the common line disposed under the common electrode in the display region,
Wherein the common line is formed of a metal having a lower resistivity than the pixel electrode formed of a transparent conductive film. 5. The method of claim 4,
The common line is formed of the same material on a substrate which is coplanar with the gate line,
Wherein the pixel electrode is formed on a substrate which is coplanar with the common line,
Wherein the common electrode is formed on a protective film covering the source and drain electrodes. 5. The method of claim 4,
And forming an outline common pattern connected to the common line in the outer area and connected to the alignment layer. The method according to claim 1,
Wherein the common electrode has an opening overlapping with the alignment contact hole,
Wherein the opening has a width wider than the alignment contact hole. The method according to claim 1,
And the alignment contact hole is disposed so as to be surrounded by the common electrode.

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