KR20120056469A - Thin film transistor substrate and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A thin film transistor substrate and a manufacturing method thereof are provided to reduce process costs with the reduced number of processes by forming a semiconductor pattern and a connection contact hole in the same process. CONSTITUTION: A plurality of gate lines is formed on a lower substrate(101). A plurality of data lines(104) is formed on the lower substrate by being separated from the gate line. A gate electrode(106) is connected to the gate line. A source electrode(108) is connected to the data line. A drain electrode(110) supplies a pixel signal from the data line to a pixel electrode. An active layer(114) is overlapped with the gate electrode while forming a gate insulating film(112) between the active layer and the gate electrode.

Description

Thin film transistor substrate and its manufacturing method {THIN FILM TRANSISTOR SUBSTRATE AND MANUFACTURING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate and a method for manufacturing the same, and more particularly, to a thin film transistor substrate and a method for manufacturing the same, which can reduce the number of processes and improve the aperture ratio.

The liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal having dielectric anisotropy using an electric field. Such a liquid crystal display includes a liquid crystal display panel including a thin film transistor substrate and a color filter substrate bonded to each other, a backlight unit for irradiating light to the liquid crystal display panel, and a driving circuit unit for driving the liquid crystal display panel. .

The thin film transistor substrate may include a gate line and a data line intersecting a gate insulating layer on a lower substrate, a thin film transistor formed at each crossing portion thereof, a drain electrode of the thin film transistor, and a pixel electrode connected through a contact hole. And a lower alignment film applied thereon.

The color filter substrate is composed of a color filter for color implementation and a black matrix for preventing light leakage, a common electrode forming a vertical electric field with the pixel electrode, and an upper alignment applied thereon for liquid crystal alignment.

As described above, the liquid crystal display panel may be formed in a twisted-nematic (TN) method in which electrodes are installed on two substrates and arranged so that the liquid crystal directors are twisted by 90 °, and then a voltage is applied to the electrodes to drive the liquid crystal directors. In-Plane Swiching (IPS) mode, which forms two electrodes on one substrate and controls the director of the liquid crystal with a horizontal electric field generated between the two electrodes, forming two electrodes as transparent conductors A method such as a FFS (Fringe Field Swiching) mode method in which a liquid crystal molecule is operated by a fringe field formed between two electrodes by forming a narrow gap between them is used.

In this case, the fringe field type liquid crystal display panel may cover the common electrode on the data line, thereby reducing the line width of the black matrix to improve the aperture ratio. In addition, in the fringe electric field method, as the thickness of the passivation layer formed between the pixel electrode and the common electrode is thinner, the driving voltage is lowered, contributing to power consumption, and the thickness is made thinner. However, the thinner the passivation layer, the larger the value of the capacitor between the data line and the common electrode formed on the data line, thereby increasing power consumption.

In order to compensate for this, as shown in FIG. 1, the protective layer is formed by dividing the first and second protective layers 52 and 54. That is, only the second passivation layer 54 is disposed between the pixel electrode 20 and the common electrode 30, and the first and second passivation layers 52 and 54 overlap with the data line 40 and the common electrode 30. ), It was possible to lower the power consumption. However, as the number of protective films increases, the number of processes increases, thereby causing a problem in that process time and cost increase. In addition, as described above, the pixel electrode is connected to the drain electrode of the thin film transistor through the contact hole, thereby reducing the opening ratio by the region where the contact hole is formed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a thin film transistor substrate and a method for manufacturing the same, which can reduce the number of processes and improve the aperture ratio.

To this end, the thin film transistor substrate according to the present invention is formed of a plurality of gate lines formed on the lower substrate and non-overlapping on the same layer as the gate lines on the lower substrate, and a plurality of data formed by separating adjacent lines from each other. A semiconductor formed to overlap lines, a gate electrode connected to the gate lines, a source electrode connected to the data line, a data electrode formed to face the source electrode, and the gate electrode and a gate insulating layer interposed therebetween A thin film transistor including a pattern, a connection contact hole exposing the separated data lines on the gate insulating layer, and connecting the separated data lines through the connection contact hole, and a source electrode and the data line of the thin film transistor. A connection electrode connecting the connection electrodes through the connection contact holes; And a pixel electrode formed in the pixel area formed by the intersection of the gate lines and the data lines and formed to be in direct contact with the drain electrode of the thin film transistor.

The connection contact hole may be formed in the same process as the semiconductor pattern.

The display device may further include a common electrode forming a fringe electric field with the pixel electrode.

The pixel electrode is formed on the gate insulating layer, and the common electrode is formed with the pixel electrode and the passivation layer interposed therebetween to form a fringe electric field with the pixel electrode.

In the method of manufacturing a thin film transistor substrate according to the present invention, a gate electrode, gate lines connected to the gate electrode, non-overlapping are formed on the same layer as the gate lines on the substrate, and a plurality of adjacent lines are separated from each other. Forming a first conductive pattern group including the data lines of the semiconductor substrate, a gate insulating layer formed on the substrate on which the first conductive pattern group is formed, and a semiconductor pattern on which an active layer and an ohmic contact layer are formed, and the separated data Forming a connection contact hole exposing the lines, forming a pixel electrode on the substrate on which the first conductive pattern group is formed, and making direct contact with the pixel electrode on the substrate on which the pixel electrode is formed A drain electrode, a source electrode formed to face the drain electrode, and the separated data line Forming a second conductive pattern group including a connection electrode configured to connect the plurality of electrodes to the connection contact hole and connecting the source electrode and the data lines through the connection contact hole; Forming a protective film on the substrate on which the conductive pattern group is formed, and forming a common electrode on the protective film to form a fringe electric field with the pixel electrode.

The forming of the semiconductor pattern and the connection contact hole may be formed using a halftone mask or a slit mask.

And a gate pad connected to the gate line and a data pad connected to the data line.

The gate pad may include a gate lower electrode connected to the gate line and a gate upper electrode connected to the gate lower electrode through a gate contact hole penetrating through the gate insulating layer and the passivation layer.

In the forming of the gate pad, the gate upper electrode is formed in the forming of the first conductive pattern group, and the gate contact hole penetrating the passivation layer and the gate insulating layer is formed in the forming of the passivation layer. And forming the gate upper electrode in the forming of the common electrode.

The data pad may include a data lower electrode connected to the data line, and a data lower electrode connected to the data lower electrode through a data contact hole penetrating through the gate insulating layer and the passivation layer.

The forming of the data pad may include forming the data upper electrode in the forming of the second conductive pattern group, and forming the data contact hole penetrating through the passivation layer in the forming of the passivation layer. In the forming of the common electrode, the data upper electrode may be formed.

The thin film transistor substrate and the method of manufacturing the same according to the present invention can reduce the capacitor value between the common electrode overlapping the data line even when only the gate insulating film and one protective film are formed, and drive the fringe electric field between the pixel electrode and the common electrode low. It can be achieved by voltage, which can lower power consumption.

In addition, the thin film transistor substrate and the method of manufacturing the same according to the present invention can reduce the number of processes by forming the semiconductor pattern and the connection contact hole in the same process, thereby reducing the process cost and time.

In addition, the thin film transistor substrate and the method of manufacturing the same according to the present invention can improve the aperture ratio by directly forming the drain electrode and the pixel electrode without contact holes.

1 is a cross-sectional view of a conventional fringe electric field thin film transistor substrate.
2 is a plan view illustrating a thin film transistor substrate according to an exemplary embodiment of the present disclosure;
3 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 2 taken along lines II ′, II-II ′, III-III ′, and VI-VI ′.
4A and 4B are plan views and cross-sectional views illustrating a method of manufacturing a first conductive pattern group in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.
5A through 5B are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor pattern and a connection contact hole in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.
6A through 6E are cross-sectional views illustrating a method of manufacturing the semiconductor pattern and the connection contact hole illustrated in FIGS. 5A and 5B.
7A and 7B illustrate a plan view and a cross-sectional view for describing a method of manufacturing a pixel electrode in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.
8A and 8B are plan views and cross-sectional views illustrating a method of manufacturing a second conductive pattern group in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.
9A and 9B illustrate a plan view and a cross-sectional view for describing a method of manufacturing a protective film in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.
10A and 10B are plan views and cross-sectional views illustrating a method of manufacturing a third conductive pattern group in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The configuration of the present invention and the operation and effect thereof will be clearly understood through the following detailed description. Before describing the present invention in detail, the same components are denoted by the same reference symbols as possible even if they are displayed on different drawings. In the case where it is judged that the gist of the present invention may be blurred to a known configuration, do.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. 2 to 10B.

FIG. 2 is a plan view illustrating a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIG. 3 illustrates the thin film transistor substrate shown in FIG. 2 as shown in FIGS. It is sectional drawing cut along a line.

The TFT substrate illustrated in FIGS. 2 and 3 may include a TFT connected to each of the gate line 102 and the data line 104, and a pixel electrode 120 formed in a pixel region having a cross structure. And a common electrode 124 forming a fringe electric field with the pixel electrode 120 in the pixel region.

The thin film transistor TFT keeps the pixel signal supplied to the data line 104 charged in the pixel electrode 120 in response to the scan signal supplied to the gate line 102. To this end, the thin film transistor TFT includes a gate electrode 106, a source electrode 108, a drain electrode 110, an active layer 114, and an ohmic contact layer 116.

The gate electrode 106 is connected with the gate line 102 to supply a scan signal from the gate line 102. The source electrode 108 is connected to the data line 104 so that the pixel signal from the data line 104 is supplied. The drain electrode 110 is formed to face the source electrode 108 with the channel portion of the active layer 114 interposed therebetween to supply the pixel signal from the data line 104 to the pixel electrode 122. The active layer 114 overlaps the gate electrode 106 with the gate insulating layer 112 therebetween to form a channel portion between the source and drain electrodes 108 and 110. The ohmic contact layer 116 is formed between the source electrode 108 and the drain electrode 110 and the active layer 114, that is, on the active layer 114 except for the channel portion. This ohmic contact layer 116 serves to reduce the electrical contact resistance between the source and drain electrodes 108, 110 and the active layer 114, respectively.

The gate pad supplies a scan signal from a gate driver (not shown) to the gate line 102. To this end, the gate pad may include a gate lower electrode 152 connected to the gate line 102, a gate lower electrode 152 through a gate contact hole 154 passing through the gate insulating layer 112, and the passivation layer 118. The gate upper electrode 156 is connected.

The data pad supplies a pixel signal from a data driver (not shown) to the data line. To this end, the data pad includes a data lower electrode 162 connected to the data line 104, and a data upper electrode connected to the data lower electrode 162 through a data contact hole 164 penetrating through the passivation layer 118. 156). In addition, the data line 104 is formed at the same time as the gate line 102 and the gate electrode 106. For this reason, the data line 104 should be formed so as not to short with the gate line 102. Accordingly, the data line 104 is formed to be separated from the gate line 102 so as not to be shorted. The data line 104 is connected to the source electrode 108 and the connection electrode 134 as shown in FIGS. 2 and 3. In addition, as illustrated in FIG. 2, data lines adjacent to each other are also connected through the connection electrode 134, and the data line 104 and the data pad are also connected through the connection electrode 134. The connection electrode 134 is formed in the same process during the process of forming the source electrode 108 and the drain electrode 110, and is formed of the same material as the source and drain electrodes 108 and 110.

The pixel electrode 120 directly contacts the drain electrode 110 of the thin film transistor TFT as illustrated in FIG. 3. Accordingly, the pixel electrode 120 is supplied with the pixel signal from the data line 104 through the thin film transistor TFT. In addition, the aperture ratio of the pixel electrode 120 is directly contacted with the drain electrode 110 without being connected to the drain electrode 110 of the thin film transistor TFT through a contact hole. That is, although the aperture ratio is reduced by the region where the contact hole is formed, the present invention improves the aperture ratio by the region where the contact hole is not formed by directly contacting the drain electrode 110 and the pixel electrode 120 without forming the contact hole.

The common electrode 124 receives a reference voltage for driving the liquid crystal, that is, a common voltage through the common line 126. The common electrode 124 and the common line 126 are formed of a transparent conductive layer, and formed in a plurality of slits to form a fringe electric field with the pixel electrode 120. In detail, when the video signal is supplied through the TFT, the pixel electrode 120 forms a fringe electric field with the common electrode 124 supplied with the common voltage, between the TFT and the color filter substrate (not shown). The liquid crystal molecules arranged in the horizontal direction are rotated by the dielectric anisotropy. In addition, the gray scale is realized by varying the light transmittance of the pixel region according to the degree of rotation of the liquid crystal molecules.

The common pad 125 supplies a common voltage to the common line 126 from the printed circuit board. The common pad 125 is formed of the same material on the same layer as the common electrode 124 and the common line 126. Accordingly, the common pad 125 is formed of a transparent conductive layer similarly to the common electrode 124 and the common line 126.

4A to 10B are plan views and cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

4A and 4B are plan views and cross-sectional views illustrating a method of manufacturing a first conductive pattern group in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

4A and 4B, a first conductive pattern group including a gate electrode 106, a gate line 102, a data line 104, and a gate lower electrode 152 is formed on the lower substrate 101. do.

Specifically, the first conductive layer is formed on the lower substrate 101 through a deposition method such as a sputtering method. As the first conductive layer, a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, Al alloy, or the like is used as a single layer, or a double layer stacked structure using the metal. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process to form a first conductive pattern group including the gate line 102, the gate electrode 106, the data line 104, and the gate lower electrode 152.

5A to 5B are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor pattern and a connection contact hole in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIGS. 6A to 6E are FIGS. 5A and 5E. FIG. 5 is a cross-sectional view illustrating a method of manufacturing a semiconductor pattern and a connection contact hole illustrated in FIG. 5B in detail.

Referring to FIG. 6A, the gate insulating layer 112, the amorphous silicon layer 214, and the amorphous silicon layer 216 doped with impurities (n + or p +) are sequentially formed on the lower substrate 101 on which the first conductive pattern group is formed. Is formed. For example, the gate insulating layer 112, the amorphous silicon layer 113, and the impurity doped amorphous silicon layer 216 are formed by a PECVD method. The gate insulating layer 112 is formed of an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or the like. The thickness of the gate insulating film 112 is thickly deposited to 2000 Å to 5000 두, preferably to 2500 3 to 3,500 보상 to compensate for the conventional two-layer protective film. In other words, as shown in the sectional view taken along line III-III 'of FIG. 3, the capacitor is deposited so thick that the value of the capacitor does not increase between the data line 104 and the common electrode 124 overlapping with each other.

Thereafter, the photoresist 220 is applied onto the amorphous silicon layer 216 doped with impurities, and then the photoresist pattern 220a having a step is exposed and developed by a photolithography process using a slit mask or a halftone mask. 220b) is formed.

Specifically, as shown in FIG. 6A, the halftone mask includes a blocking region S1 in which a blocking layer 172 is formed on a substrate 170, and a semi-transmissive layer in which a transflective layer 174 is formed on a substrate 170. The area S2 and the transmission area S3 in which only the substrate 170 exists are provided. The blocking region S1 is positioned in a region where the semiconductor pattern is to be formed to block ultraviolet rays, so that after the development, the first photoresist pattern 220a remains as shown in FIG. 6B. The transmissive region S3 is positioned in the region where the connection contact hole 132 is to be formed and transmits all ultraviolet rays so that the photoresist is removed as shown in FIG. 6B. The semi-transmissive region S2 is formed of a thinner than the first photoresist pattern 220a after the development by adjusting the light transmittance by stacking the semi-transmissive layer 174 in the region where the gate insulating layer 112 remains. 2 photoresist pattern 220b remains.

As shown in FIG. 6C, the amorphous silicon layer 214 and the amorphous silicon layer 216 doped with impurities (n-type or p-type) are patterned by an etching process using photoresist patterns 220a and 220b having a step difference. As shown in FIG. 6C, a connection contact hole 132 is formed. Subsequently, the first photoresist pattern 220a is thinned by ashing the photoresist pattern 220a by an ashing process using an oxygen (O ₂ ) plasma as shown in FIG. 6D, and the second photoresist pattern 220b. To be removed. Subsequently, the amorphous silicon layer exposed through the etching process using the ashed first photoresist pattern 220a and the amorphous silicon layer doped with impurities are removed. As a result, the semiconductor pattern 115 is formed.

Then, as shown in FIG. 6E, the first photoresist pattern 220a remaining on the semiconductor pattern 115 is removed by a strip process.

As such, the semiconductor pattern process and the connection contact hole process may be formed in the same process using a halftone mask or a slit mask.

7A and 7B illustrate a plan view and a cross-sectional view for describing a method of manufacturing a pixel electrode in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

7A and 7B, the pixel electrode 120 is formed on the gate insulating layer 112.

Specifically, the transparent conductive layer is formed on the gate insulating film 112 through a deposition method such as sputtering. Tin oxide (TO), indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), etc. Is used. The transparent conductive layer is patterned by a photolithography process and an etching process to form the pixel electrode 120.

8A and 8B are plan views and cross-sectional views illustrating a method of manufacturing a second conductive pattern group in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

8A and 8B, the source electrode 108, the drain electrode 110, the connection electrode 134, and the data lower electrode 162 are formed on the lower substrate 101 on which the pixel electrode 120 is formed. A second conductive pattern group is formed.

Specifically, the second conductive layer is formed on the lower substrate 101 through a deposition method such as a sputtering method. As the second conductive layer, a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, Al alloy, or the like is used as a single layer, or a double layer stacked structure using the metal. Subsequently, the second conductive layer is patterned by a photolithography process and an etching process to form a second conductive pattern group including the source electrode 108, the drain electrode 110, the connection electrode 134, and the data lower electrode 162. do. In this case, the drain electrode 110 is formed to directly contact the pixel electrode 120 without the contact hole.

9A and 9B illustrate a plan view and a cross-sectional view for describing a method of manufacturing a protective film among the methods of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

9A and 9B, a passivation layer 118 including a gate contact hole 154 and a data contact hole 164 is formed on the lower substrate 101 on which the second conductive pattern group is formed.

Specifically, the protective film 118 is formed on the lower substrate on which the second conductive pattern group is formed by a method such as CVD or PECVD. As the protective film 118, an inorganic insulating material such as the gate insulating film 112 formed by a method such as CVD or PECVD is used. The passivation layer 118 is patterned by a photolithography process and an etching process to form a gate contact hole 154 and a data contact hole 164. The gate contact hole 154 penetrates the gate insulating layer 112 and the passivation layer 118 to expose the gate lower electrode 152, and the data contact hole 164 penetrates the passivation layer 118 to allow the data lower electrode 162. Expose

In addition, the protective film has a thickness of 1500 kPa to 2500 kPa. As shown in FIG. 3, the passivation layer 118 allows the pixel electrode 120 to achieve a low driving voltage between the common electrode 124 and the fringe electric field with the passivation layer 118 interposed therebetween. It is formed thin.

As such, the gate insulating layer is formed thick between the data line and the common electrode so as to have a small capacitor value, and the protective layer is formed thin so that the fringe field between the pixel electrode and the common electrode can be formed at a low driving voltage. Accordingly, even if only one layer of the protective film is formed, the driving voltage can be lowered and the capacitor value can be reduced.

On the other hand, the thickness of the gate insulating film 112 and the thickness of the protective film 118 may define the thickness of the gate insulating film 112 and the thickness of the protective film 118 so that when the two layers are combined, a range of 5500 kV to 8000 kV may be obtained. The thickness may be defined, preferably in the range of 5500 ms to 6500 ms.

10A and 10B are plan views and cross-sectional views illustrating a method of manufacturing a third conductive pattern group in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

10A and 10B, a third electrode including a common electrode 124, a common line 126, a common pad 125, a gate upper electrode 156, and a data upper electrode 166 is disposed on the passivation layer 118. A conductive pattern group is formed.

Specifically, the transparent conductive layer is formed on the protective film 118 through a deposition method such as sputtering. Tin oxide (TO), indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), etc. Is used. The transparent conductive layer is patterned by a photolithography process and an etching process to form a third electrode including a common electrode 124, a common line 126, a common pad 125, a gate upper electrode 156, and a data upper electrode 166. A conductive pattern group is formed. Accordingly, the gate upper electrode 156 is connected to the gate lower electrode 152 through the gate contact hole 154, and the data upper electrode 166 is connected to the data lower electrode 162 through the data contact hole 164. Connected.

As described above, according to the present invention, the aperture ratio may be improved by the area where the contact hole is not formed by directly contacting the drain electrode 110 and the pixel electrode 120 without the contact hole. In addition, the cost is reduced by not having to form one of the two protective layers, and the number of processes and the corresponding cost are reduced by forming the semiconductor pattern 115 and the connection contact hole 132 in the same process.

The foregoing description is merely illustrative of the present invention, and various modifications may be made by those skilled in the art without departing from the spirit of the present invention. Therefore, the embodiments disclosed in the specification of the present invention are not intended to limit the present invention. The scope of the present invention should be construed by the claims below, and all techniques within the scope equivalent thereto will be construed as being included in the scope of the present invention.

10 substrate 12 gate insulating film
20 pixel electrode 30 common electrode
40: data line 52,54: first protective film, second protective film
101: lower substrate 102: gate line
104: data line 106: gate electrode
108: source electrode 110: drain electrode
112 gate insulating film 114 active layer
116: ohmic contact layer 118: protective film
120 pixel electrode 124 common electrode
125: common pad 126: common line
132: connection contact hole 134: connection electrode
152: gate lower electrode 154: gate contact hole
156: gate upper electrode 162: data lower electrode
164: data contact hole 166: data upper electrode
172: barrier layer 174: transflective layer

Claims (11)

A plurality of gate lines formed on the lower substrate;
A plurality of data lines formed on the lower substrate so as to be non-overlapping on the same layer as the gate lines, and adjacent lines separated from each other;
A gate electrode connected to the gate lines, a source electrode connected to the data line, a data electrode formed to face the source electrode, and a semiconductor pattern formed to overlap the gate electrode and the gate insulating layer therebetween; A thin film transistor;
A connection contact hole exposing the separated data lines on the gate insulating layer;
A connection electrode connecting the separated data lines through the connection contact hole and connecting the source electrode and the data lines of the thin film transistor through the connection contact hole;
And a pixel electrode formed in a pixel region formed at the intersection of the gate lines and the data lines, the pixel electrode being in direct contact with the drain electrode of the thin film transistor. The method of claim 1,
The connection contact hole is a thin film transistor substrate, characterized in that formed in the same process as the semiconductor pattern. The method of claim 1,
And a common electrode forming a fringe electric field with the pixel electrode. The method of claim 1,
And the pixel electrode is formed on the gate insulating layer, and the common electrode is formed with the pixel electrode and a passivation layer interposed therebetween to form a fringe electric field with the pixel electrode. A first conductive pattern group including a gate electrode, gate lines connected to the gate electrode, non-overlapping on the same layer as the gate lines, and a plurality of data lines adjacent to each other, the adjacent lines being formed on the substrate. Forming a;
Forming a gate insulating film on the substrate on which the first conductive pattern group is formed, and forming a connection contact hole exposing a semiconductor pattern on which an active layer and an ohmic contact layer are formed and the separated data lines;
Forming a pixel electrode on the substrate on which the first conductive pattern group is formed;
A drain electrode formed to directly contact the pixel electrode on the substrate on which the pixel electrode is formed, a source electrode formed to face the drain electrode, and the separated data lines to be connected through the connection contact hole; Forming a second conductive pattern group including a connection electrode configured to connect the source electrode and the data lines through the connection contact hole;
Forming a protective film on the substrate on which the second conductive pattern group is formed;
Forming a common electrode forming a fringe electric field with the pixel electrode on the passivation layer. The method of claim 5,
The forming of the semiconductor pattern and the connection contact hole may be performed using a halftone mask or a slit mask. The method of claim 5,
And a gate pad connected to the gate line and a data pad connected to the data line. The method of claim 7, wherein
The gate pad is
A gate lower electrode connected to the gate line;
And a gate upper electrode connected to the lower gate electrode through a gate contact hole penetrating the gate insulating layer and the passivation layer. The method of claim 8,
Forming the gate pad
Forming the gate upper electrode in the forming of the first conductive pattern group, forming the gate contact hole penetrating the passivation layer and the gate insulating layer in the forming of the passivation layer, and forming the common electrode And forming the gate upper electrode in the thin film transistor substrate. The method of claim 7, wherein
The data pad is
A data lower electrode connected to the data line;
And a data lower electrode connected to the data lower electrode through the data contact hole penetrating the gate insulating layer and the passivation layer. The method of claim 10,
Forming the data pad
The data upper electrode is formed in the forming of the second conductive pattern group, the data contact hole penetrating the passivation layer is formed in the forming of the passivation layer, and the data upper part is formed in the forming of the common electrode. An electrode is formed, The manufacturing method of the thin film transistor substrate characterized by the above-mentioned.

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