KR101866388B1 - Thin film transistor substrate and method of fabricating the same - Google Patents

Abstract

The present invention provides a thin film transistor substrate which can be applied to a large-area and high-resolution model by lowering power consumption and a manufacturing method thereof.
A method of manufacturing a thin film transistor substrate according to the present invention includes: forming a thin film transistor on a substrate, the thin film transistor being connected to a gate line and a data line formed so as to cross each other with a gate insulating film interposed therebetween; Forming a pixel electrode connected to the thin film transistor in a pixel region provided at an intersection of the gate line and the data line; Forming a protective film thicker than a region corresponding to the pixel electrode except a region corresponding to the pixel electrode; And forming a common electrode between the pixel electrode and the fringe field on the passivation layer.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a thin film transistor substrate,

The present invention relates to a thin film transistor substrate which can be applied to a large-area and high-resolution model by reducing power consumption, and a manufacturing method thereof.

The liquid crystal display device displays an image by adjusting the light transmittance of liquid crystal having dielectric anisotropy using an electric field. Such a liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field.

Among these liquid crystal display devices, a fringe field type liquid crystal display device has a common electrode and a pixel electrode in each pixel region with a protective film interposed therebetween. The liquid crystal molecules filled between the upper substrate and the lower substrate are operated in the respective pixel regions by the fringe field, thereby improving the aperture ratio and the transmissivity.

The common electrode of the fringe field type liquid crystal display panel is formed to overlap with the data line so as to prevent the distortion of the pixel signal supplied to the pixel electrode due to the coupling effect of the parasitic capacitor Cdp formed between the data line and the pixel electrode do. In this case, if the thickness of the protective film located between the common electrode and the data line is increased to reduce the capacitance value of the parasitic capacitor Cdc between the common electrode and the data line, the thickness of the protective film between the pixel electrode and the common electrode is also increased do. The driving voltage applied to the pixel electrode and the common electrode must be increased in order to form a fringe field having a desired intensity between the pixel electrode and the common electrode overlapping each other with the thickened protective film interposed therebetween. As a result, power consumption proportional to the driving voltage is increased, which makes it difficult to apply the conventional fringe field type liquid crystal display panel to a large-area and high-resolution model.

In order to solve the above problems, the present invention provides a thin film transistor substrate and a method of manufacturing the same, which can be applied to a large-area and high-resolution model by lowering power consumption.

According to an aspect of the present invention, there is provided a method of manufacturing a thin film transistor substrate, including: forming a gate line and a thin film transistor connected to a data line on a substrate, the gate line and the data line intersecting each other with a gate insulating film interposed therebetween; Forming a pixel electrode connected to the thin film transistor in a pixel region provided at an intersection of the gate line and the data line; Forming a protective film thicker than a region corresponding to the pixel electrode except a region corresponding to the pixel electrode; And forming a common electrode between the pixel electrode and the fringe field on the passivation layer.

The forming of the passivation layer may include forming a first passivation layer having a first thickness on the entire surface of the substrate on which the pixel electrode is formed; And forming a second protective layer having a second thickness on the first protective layer in regions other than a region corresponding to the pixel electrode.

The forming of the passivation layer may include sequentially forming the first and second passivation layers on the substrate on which the thin film transistor is formed; Patterning the second protective film using a slit mask or a semi-transparent mask so that the second protective film has a step; Etching the gate insulating layer and the first passivation layer using the patterned second passivation layer as a mask; And a step of ashing the second protective film so that the second protective film remains in the remaining region except the region corresponding to the pixel electrode.

The first passivation layer is formed to a thickness of 3 to 4 탆 using an inorganic insulating material including silicon nitride or silicon oxide, and the second passivation layer is formed using an organic insulating material including a photo- And is formed to have a thickness.

And the data line overlaps the common electrode with the first and second protective films interposed therebetween.

The method of manufacturing a thin film transistor substrate may further include the step of forming a shield pattern between the data line and the pixel electrode, wherein the shield pattern is formed on the same plane with the same material as the gate line .

According to an aspect of the present invention, there is provided a thin film transistor substrate comprising: a gate line formed on a substrate; A data line crossing the gate line and providing a pixel region; A thin film transistor connected to the gate line and the data line; A pixel electrode connected to the thin film transistor and formed in the pixel region; A common electrode forming the pixel electrode and the fringe field; And a protective layer formed thicker than a region corresponding to the pixel electrode in a region other than a region corresponding to the pixel electrode.

The passivation layer may include a first passivation layer formed between the pixel electrode and the common electrode; And a second passivation layer formed on the first passivation layer in a region other than a region corresponding to the pixel electrode, wherein the first passivation layer is formed of an inorganic insulating material containing silicon nitride or silicon oxide, And the second protective layer is formed to have a thickness of 2 to 3 占 퐉 by using an organic insulating material including an acrylic resin.

And the data line overlaps the common electrode with the first and second protective films interposed therebetween.

The thin film transistor substrate further includes a shield pattern formed between the data line and the pixel electrode and formed on the same plane as the gate line.

The thin film transistor substrate according to the present invention can reduce the driving voltage by overlapping the common electrode and the pixel electrode in the pixel region with the first protective film sandwiched therebetween and the data line and the common electrode are sandwiched between the first and second protective films The capacitance value of the parasitic capacitor Cdc is reduced as compared with the prior art, so that the power consumption can be reduced. Accordingly, the thin film transistor substrate according to the present invention is applicable to high resolution and large area models. In addition, the thin film transistor substrate according to the present invention has a thinner thickness than the first protective film, so that the deposition ability of the first protective film deposition equipment is improved. In addition, since the second protective film is formed of a photosensitive organic insulating material, a separate photoresist pattern is unnecessary, so that a strip process for removing the photoresist pattern is not required, which simplifies the process. In addition, since the amount of the liquid crystal used decreases by the volume of the second protective film on the data line of the present invention, the cost can be reduced.

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1 is a plan view showing a thin film transistor substrate according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view of a thin film transistor substrate taken along line I-I 'and II-II' in FIG.
FIGS. 3A and 3B are a plan view and a cross-sectional view illustrating a method of manufacturing the first conductive pattern of the thin film transistor substrate shown in FIGS. 1 and 2. FIG.
FIGS. 4A and 4B are a plan view and a cross-sectional view illustrating a method of manufacturing a semiconductor pattern of the thin film transistor substrate shown in FIGS. 1 and 2. FIG.
5A and 5B are a plan view and a cross-sectional view illustrating a method of manufacturing a second conductive pattern of the thin film transistor substrate shown in FIGS. 1 and 2. FIG.
6A and 6B are a plan view and a cross-sectional view illustrating a method of manufacturing a third conductive pattern of the thin film transistor substrate shown in FIGS. 1 and 2. FIG.
FIGS. 7A and 7B are cross-sectional views for explaining a method of manufacturing first and second protective films having a gate contact hole, a pixel contact hole, and a data contact hole of the thin film transistor substrate shown in FIGS. 1 and 2. FIG.
FIGS. 8A to 8C are cross-sectional views for explaining a method of manufacturing the first and second protective films having gate contact holes, pixel contact holes, and data contact holes of the thin film transistor substrate shown in FIGS. 7A and 7B.
FIGS. 9A and 9B are cross-sectional views for explaining a method of manufacturing the fourth conductive pattern of the thin film transistor substrate shown in FIGS. 1 and 2. FIG.
10 is a plan view showing a thin film transistor substrate according to a second embodiment of the present invention.
11 is a cross-sectional view showing a thin film transistor substrate taken along a line III-III 'in FIG.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

FIG. 1 is a plan view showing a thin film transistor substrate according to a first embodiment of the present invention, FIG. 2 is a sectional view taken along the line I-I 'and II-II' to be.

The thin film transistor substrate shown in Figs. 1 and 2 includes a thin film transistor connected to each of the gate line 102 and the data line 104, a pixel electrode 122 formed in a pixel region provided in the crossing structure, A data pad 160 connected to the data line 104, and a common line 126. The data line 104 is connected to the gate line 102, And a common pad 140 connected thereto.

The thin film transistor causes a pixel signal supplied to the data line 104 to be charged and held in the pixel electrode 122 in response to a scan signal supplied to the gate line 102. The thin film transistor 130 includes a gate electrode 106, a source electrode 108, a drain electrode 110, an active layer 114, and an ohmic contact layer 116.

The gate electrode 106 is connected to the gate line 102 so that a scan signal from the gate line 102 is supplied. The source electrode 108 is connected to the data line 104 so that the pixel signal from the data line 104 is supplied. The drain electrode 110 is formed to face the source electrode 108 with the channel portion of the active layer 114 interposed therebetween and supplies a pixel signal from the data line 104 to the pixel electrode 122. The active layer 114 overlaps the gate electrode 106 with the gate insulating film 112 interposed therebetween to form a channel portion between the source and drain electrodes 108 and 110. The ohmic contact layer 116 is formed on the active layer 114 between the source electrode 108 and the drain electrode 110 and the active layer 114, The ohmic contact layer 116 serves to reduce electrical contact resistance between each of the source and drain electrodes 108 and 110 and the active layer 114.

The first passivation layer 118 formed to cover the thin film transistor prevents the channel portion of the thin film transistor from being damaged by the carbon (C) contained in the second passivation layer 128 formed of an organic insulating material. Here, the first protective film 118 is formed to a thickness of 3 to 4 탆 by using an inorganic insulating material including silicon nitride or silicon oxide.

The second protective film 128 is formed on the first protective film 118 in regions other than the pixel region provided at the intersection of the gate line 102, the data line 104 and the common line 126. That is, the second protective film 128 is formed on the first protective film 118 in the region corresponding to the gate line 102, the data line 104, the common line 126, the gate pad 150 and the data pad 160 As shown in FIG. The second protective layer 128 is formed to a thickness of 2 to 3 탆 using an organic insulating material including a photo-acrylic resin having a lower dielectric constant than the first protective layer 118. In this case, the data line 104 and the common electrode 124 located above the data line 104 are overlapped with each other with the first and second protective films 118 and 128 interposed therebetween. Accordingly, the capacitance value of the parasitic capacitor formed by overlapping the data line 104 and the common electrode 124 with the first and second protective films 118 and 128 therebetween can be reduced, thereby reducing power consumption.

In addition, since the second protective film 128 is not formed in the pixel region, the light generated in the backlight unit passes through only the first protective film 118, so that light loss due to the second protective film 128 can be prevented.

The pixel electrode 122 is directly connected to the drain electrode 110 of the thin film transistor. Accordingly, the pixel electrode 122 is supplied with the pixel signal from the data line 104 through the thin film transistor.

The common electrode 124 is connected to the common line 126 and a common voltage is supplied through the common line 126. The common electrode 124 is electrically connected to the common line 126 exposed through the gate insulating film 112 and the connection contact hole 120 passing through the first and second protective films 118 and 128. The common electrode 124 overlaps the pixel electrode 122 with the first protective film 118 interposed therebetween to form a fringe field. By this fringe field, liquid crystal molecules arranged in the horizontal direction between the thin film transistor substrate and the color filter substrate are rotated by dielectric anisotropy. The light transmittance of the liquid crystal molecules varies depending on the degree of rotation of the liquid crystal molecules, thereby realizing an image.

The common electrode 124 overlaps the pixel electrode 122 with the first protective film 118 interposed therebetween so that the distance between the common electrode 124 and the pixel electrode 122 is closer to that of the conventional thin film transistor substrate. Accordingly, the thin film transistor substrate according to the present invention can reduce the driving voltage of the pixel electrode 122 and the common electrode 124, thereby reducing power consumption.

The gate pad 150 supplies the gate line 102 with a scan signal from a gate driver (not shown). The gate pad 150 includes a gate pad lower electrode 152 connected to the gate line 102 and a gate contact hole 154 penetrating the first and second protective layers 118 and 128 and the gate insulating layer 112. [ And a gate pad upper electrode 156 connected to the gate lower electrode 152 through the gate pad upper electrode 156. [

The data pad 160 supplies a pixel signal from a data driver (not shown) to the data line 104. The data pad 160 is connected to the data pad lower electrode 162 through the data pad lower electrode 162 connected to the data line 104 and the data contact hole 164 passing through the first and second protective films 118 and 128. [ And a data pad upper electrode 166 connected to the data pad upper electrode 162.

The common pad 140 supplies a common signal to the common line 126. The common pad 140 includes a common pad lower electrode 142 connected to the common line 126 and a common contact hole 144 penetrating the gate insulating film 112 and the first and second protective films 118 and 128, And a common pad upper electrode 146 connected to the common pad lower electrode 142 through the common pad lower electrode 142.

As described above, in the thin film transistor substrate according to the present invention, since the common electrode 124 and the pixel electrode 122 in the pixel region overlap each other with the first protective film 118 interposed therebetween, the driving voltage can be reduced as compared with the conventional one, The capacitance of the parasitic capacitor Cdc is reduced and the power consumption can be reduced by overlapping the first electrode 104 and the common electrode 124 with the first and second protective films 118 and 128 interposed therebetween. Accordingly, the thin film transistor substrate according to the present invention is applicable to high resolution and large area models. In addition, since the thin film transistor substrate according to the present invention has a thinner thickness than the first protective film 118, the deposition ability of the deposition apparatus of the first protective film 118 is improved. In addition, since the second protective film 128 is formed of a photosensitive organic insulating material, a separate photoresist pattern is unnecessary, so that a strip process for removing the photoresist pattern is not required, thereby simplifying the process. In addition, since the amount of liquid crystal used is reduced by the volume of the second protective layer 128 formed on at least one of the data line 104 and the gate line 102, the present invention can reduce the cost.

3A to 9B are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate shown in FIG.

Referring to FIGS. 3A and 3B, a first conductive pattern including a gate electrode 106, a gate pad lower electrode 152, and a common pad lower electrode 142 is formed on a substrate 101.

Specifically, a gate metal layer is sequentially formed on the substrate 101 through a deposition method such as a sputtering method. Here, the gate metal layer is formed of a metal such as an aluminum-based metal (Al, AlNd), copper (Cu), titanium (Ti), molybdenum (Mo), tungsten (W) Then, a gate metal layer is patterned by a photolithography process and an etching process using the first mask, thereby forming a first conductive pattern including the gate electrode 106, the gate pad lower electrode 152, and the common pad lower electrode 142 .

4A and 4B, a gate insulating layer 112 is formed on a substrate 101 on which a first conductive pattern is formed, and an active layer 114 and an ohmic contact layer (not shown) are formed on a substrate 101 on which a gate insulating layer 112 is formed. A semiconductor pattern including the layer 116 is formed.

Specifically, an inorganic insulating material such as silicon oxide (SiO x) or silicon nitride (SiN x) is formed on the entire surface of the substrate 101 on which the first conductive pattern is formed, thereby forming the gate insulating film 112. Then, an amorphous silicon layer and an amorphous silicon layer doped with an impurity (n + or p +) are sequentially formed on the substrate 101 on which the gate insulating film 112 is formed. Subsequently, the amorphous silicon layer and the amorphous silicon layer doped with the impurity (n + or p +) are patterned by a photolithography process and an etching process using the second mask, thereby forming a semiconductor pattern including the active layer 114 and the ohmic contact layer 116 .

5A and 5B, a second conductive pattern including a pixel electrode 122 is formed on a substrate 101 on which a semiconductor pattern is formed.

Specifically, a first transparent conductive layer such as indium tin oxide (ITO) is formed on a substrate 101 on which a semiconductor pattern is formed through a deposition method such as a sputtering method. Subsequently, the first transparent conductive layer is patterned by a photolithography process and an etching process using a third mask, thereby forming a second conductive pattern including the pixel electrode 122. [

6A and 6B, a substrate 101 having a second conductive pattern is formed on a substrate 101. The substrate 101 includes a source electrode 108, a drain electrode 110, a data line 104, 3 conductive pattern is formed.

Specifically, a data metal layer is sequentially formed on the substrate 101 on which the second conductive pattern group is formed through a deposition method such as a sputtering method. Here, as the data metal layer, titanium (Ti), tungsten (W), aluminum (Al) metal, molybdenum (Mo), copper (Cu) and the like are used. Next, a data metal layer is patterned by a photolithography process and an etching process using a fourth mask to form a third conductive layer including a source electrode 108, a drain electrode 110, a data line 104 and a data pad lower electrode 162 A pattern is formed. Then, the active layer 114 is exposed by removing the ohmic contact layer 116 located between the source electrode 108 and the drain electrode 110 as a mask.

Meanwhile, the second conductive pattern including the pixel electrode 122 is formed before the third conductive pattern including the source and drain electrodes 108 and 110 is formed. Conversely, after the third conductive pattern is formed, 2 conductive pattern may be formed.

7A and 7B, a gate contact hole 154, a data contact hole 164, a common contact hole 144, and a connection contact hole 120 are formed on a substrate 101 on which a third conductive pattern is formed The first and second protective films 118 and 128 are formed. 8A to 8C will be described in detail.

An inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is formed on the entire surface of the substrate 101 on which the third conductive pattern is formed as shown in FIG. 8A, thereby forming the first protective film 118. Then, a second protective film 128 is formed on the first protective film 118 by forming a negative or positive photosensitive organic insulating material, for example, photoacryl on the entire surface. Then, the second protective film 128 is patterned by a photolithography process using a slit mask 170 or a semi-transparent mask. Specifically, the blocking region S1 of the slit mask 170 shields the ultraviolet rays, so that the second protective film 128 corresponding to the blocking region S1 maintains the first thickness which is the coating thickness after the exposure and development process. The slit area S2 of the slit mask 170 is formed with a second thickness that is smaller than the first thickness after the exposure and development process by rotating the ultraviolet light so that the second protective layer 128 corresponding to the slit area S2 is formed. The transmissive region S3 of the slit mask 170 transmits ultraviolet rays so that the second protective film 128 corresponding to the transmissive region S3 is removed after the exposure and development process.

The first passivation layer 118 and the gate insulating layer 128 are etched through the etching process using the second passivation layer 128 as a mask to form gate contact holes 154 and data contact holes 164 are formed. The gate contact hole 154 exposes the gate pad lower electrode 152 through the protective film 104 and the gate insulating film 112. The data contact hole 164 penetrates the protective film 104, (Not shown). Then, the second protective film 128 having a second thickness corresponding to the slit region S2 is removed as shown in FIG. 8C by ashing the second protective film 128 through an ashing process using an oxygen plasma, The second protective film 128 of the first thickness corresponding to the region S1 is thinned. Accordingly, the second protective film 128 is formed on the region corresponding to the data line 104, the gate line 102, the data pad, and the gate pad except for the pixel region.

9A and 9B, the common electrode 124, the gate pad upper electrode 156, the data pad upper electrode 166, and the common pad 124 are formed on the substrate 101 on which the first and second protective films 118 and 128 are formed, A fourth conductive pattern including the upper electrode 146 is formed.

Specifically, a second transparent conductive layer is formed on the substrate 101 on which the first and second protective layers 118 and 128 are formed through a deposition method such as a sputtering method. Then, the second transparent conductive layer is patterned by the photolithography process and the etching process using the sixth mask to form the common electrode 124, the gate pad upper electrode 156, the data pad upper electrode 166, and the common pad upper electrode 146 ) Is formed on the fourth conductive pattern.

FIG. 10 is a plan view showing a thin film transistor substrate according to a second embodiment of the present invention, and FIG. 11 is a sectional view showing a thin film transistor substrate taken along the line "III-III '" in FIG.

The thin film transistor substrate shown in FIGS. 10 and 11 has the same constituent elements as those of the thin film transistor substrate shown in FIGS. 1 and 2 except that the shield pattern 180 has a shield pattern 180, A description thereof will be omitted.

The shield pattern 180 is formed of the same gate metal layer as the gate line 102 on the substrate 101 between the data line 104 and the common electrode 124. The shield pattern 180 shields the light leakage caused by the liquid crystal layer not being properly driven on the alignment layer (not shown) of the unrubbed region because the second patterned protective layer 128 does not contact the rubbing cloth.

Such a shield pattern 180 is simultaneously formed through the same manufacturing method as the gate line 102 shown in FIGS. 3A and 3B.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

106: gate electrode 108: source electrode
110: drain electrode 112: gate insulating film
114: active layer 116: ohmic contact layer
118, 128: protective film 122: pixel electrode
124: common electrode 126: common line
150: gate pad 160: data pad
180: Shield pattern

Claims (10)

A thin film transistor connected to a gate line and a data line formed so as to cross each other with a gate insulating film interposed therebetween; a common line parallel to the gate line; a gate pad lower electrode connected to the gate line; Forming a data pad lower electrode on the substrate;
Forming a pixel electrode connected to the thin film transistor in a pixel region provided at an intersection of the gate line and the data line;
Forming a thick protective film in a region other than the region corresponding to the pixel electrode except the region corresponding to the pixel electrode;
Forming a gate pad upper electrode connected to the gate pad lower electrode and a data pad upper electrode connected to the data pad lower electrode on a common electrode formed of the pixel electrode and the fringe field on the substrate having the protective film formed thereon; Including,
The step of forming the protective film
Wherein the gate electrode, the data line, the common line, the gate pad lower electrode, and the data pad lower electrode except the region corresponding to the pixel electrode correspond to the first protective film on the substrate having the pixel electrode formed thereon And forming a second protective film on the first protective film in the region where the first protective film is formed,
Wherein a sum of thicknesses of the first and second protective films between the data line and the common electrode is greater than a sum of thicknesses of the first and second protective films between the pixel electrode and the common electrode, Thicker than the thickness of the protective film,
Wherein the common electrode is formed on the first protective film in a region overlapping the pixel electrode, and is formed on the second protective film in a region overlapping the data line. delete The method according to claim 1,
The step of forming the protective film
Sequentially forming first and second protective films on the substrate on which the thin film transistor, the common line, the gate pad lower electrode, and the data pad lower electrode are formed;
Patterning the second protective film using a slit mask or a semi-transparent mask so that the second protective film has a step;
Etching the gate insulating layer and the first passivation layer using the patterned second passivation layer as a mask;
And etching the second protective film so that the second protective film remains in a remaining region except a region corresponding to the pixel electrode. The method of claim 3,
The first passivation layer is formed to a thickness of 3 to 4 탆 using an inorganic insulating material including silicon nitride or silicon oxide, and the second passivation layer is formed using an organic insulating material including a photo- Wherein the thickness of the thin film transistor substrate is less than the thickness of the thin film transistor substrate. delete The method according to claim 1,
Further comprising the step of forming a shield pattern between the data line and the pixel electrode,
Wherein the shield pattern is formed on the same plane with the same material as the gate line. A gate line positioned on the substrate;
A data line crossing the gate line and providing a pixel region;
A thin film transistor connected to the gate line and the data line;
A pixel electrode connected to the thin film transistor and located in the pixel region;
A common electrode forming the pixel electrode and the fringe field;
A gate pad connected to the gate line;
A data pad connected to the data line;
A common line connected to the common electrode;
And a protective layer formed thicker than a region corresponding to the pixel electrode, except for a region corresponding to the pixel electrode,
The protective film
A first protective layer disposed between the pixel electrode and the common electrode;
And a second protective film disposed on the first protective film in a region corresponding to the gate line, the data line, the common line, the gate pad, and the data pad excluding a region corresponding to the pixel electrode,
Wherein the common electrode is further positioned to overlap the data line with the first and second protective films interposed therebetween, and a sum of thicknesses of the first and second protective films between the common electrode and the data line is greater than a sum of thicknesses of the pixel electrode And a second protection layer provided between the common electrode and the second protection layer,
Wherein the common electrode is disposed on the first protective film in a region overlapping the pixel electrode, and is disposed on the second protective film in a region overlapping the data line. 8. The method of claim 7,
Wherein the first protective film has a thickness of 3 to 4 탆 using an inorganic insulating material including silicon nitride or silicon oxide and the second protective film has a thickness of 2 to 3 탆 Lt; / RTI > delete 9. The method of claim 8,
And a shield pattern disposed between the data line and the pixel electrode and positioned on the same plane with the same material as the gate line.

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