KR102028982B1 - Liquid display panel and method of fabricating the same - Google Patents

Abstract

The present invention relates to a liquid crystal display panel capable of blocking out-gassing, and a method of manufacturing the same. The present invention relates to a thin film transistor substrate, a color filter substrate bonded to and facing the thin film transistor, and an upper surface of the thin film transistor substrate. A liquid crystal display panel including an antistatic transparent electrode formed on each rear surface of the color filter substrate, wherein the thin film transistor substrate is formed to cover the thin film transistor formed on the substrate and the thin film transistor, and the drain electrode of the thin film transistor. Protective layers including pixel contact holes exposing the light emitting layer, a pixel electrode connected to the drain electrode, a common electrode forming a fringe field with the pixel electrode, and out-gassing generated from the passivation layers covering the thin film transistor. A mold in the pixel contact holes to block And a protruding out-gassing blocking spacer.

Description

Liquid crystal display panel and its manufacturing method {LIQUID DISPLAY PANEL AND METHOD OF FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel and a method for manufacturing the same, and more particularly, to a liquid crystal display panel and a method for manufacturing the same that can block outgassing.

The liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal having dielectric anisotropy using an electric field. Such a liquid crystal display device includes a liquid crystal display panel including a thin film transistor substrate and a color filter substrate bonded to each other, a backlight unit for irradiating light to the liquid crystal display panel, and a driving circuit unit for driving the liquid crystal display panel. .

The thin film transistor substrate may include a gate line and a data line intersecting a gate insulating layer on a lower substrate, a thin film transistor formed at each crossing portion thereof, a drain electrode of the thin film transistor, and a pixel electrode connected through a contact hole. And a lower alignment film applied thereon.

The color filter substrate is composed of a color filter for color implementation and a black matrix for preventing light leakage, a common electrode forming a vertical electric field with the pixel electrode, and an upper alignment applied thereon for liquid crystal alignment.

As described above, the liquid crystal display panel may be formed in a twisted-nematic (TN) method in which electrodes are installed on two substrates and arranged so that the liquid crystal directors are twisted by 90 °, and then a voltage is applied to the electrodes to drive the liquid crystal directors. In-Plane Switching (IPS) mode, which forms two electrodes on one substrate and controls the director of the liquid crystal with a horizontal electric field generated between the two electrodes, while forming two electrodes as transparent conductors A method such as a FFS (Fringe Field Switching) mode in which a liquid crystal molecule is operated by a fringe field formed between two electrodes by forming a narrow gap between the electrodes is used.

In this case, the fringe field type thin film transistor substrate may include a gate line and a data line crossing each other, a thin film transistor connected to the gate line and the data line, a protective film formed to cover the thin film transistor, and a thin film transistor connected to the thin film transistor in a slit form. And a common electrode for forming a fringe electric field with the pixel electrode interposed therebetween.

Here, out-gassing is generated from the protective film formed to cover the thin film transistor, and bubbles are generated in the panel as shown in FIG. In particular, when the protective film is used as the photo acryl, the photo acryl may lower the dielectric constant to reduce the occurrence of parasitic capacitors, but outgassing is most likely among the protective films. Outgassing is thus generated, resulting in bubble failure as shown in FIG. 1.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a liquid crystal display panel and a method of manufacturing the same, which can block out-gassing.

To this end, a liquid crystal display panel comprising a thin film transistor substrate, a color filter substrate bonded to and facing the thin film transistor, and an antistatic transparent electrode formed on each of an upper surface of the thin film transistor substrate and a rear surface of the color filter substrate. The thin film transistor substrate may include a thin film transistor formed on the substrate, protective layers including pixel contact holes formed to cover the thin film transistor and exposing a drain electrode of the thin film transistor, and a pixel connected to the drain electrode. An electrode, a common electrode forming a fringe field with the pixel electrode, and an out-gassing blocking spacer formed and protruding in the pixel contact holes blocking out-gassing generated from the passivation layers covering the thin film transistor. It features.

The display device may further include a common line for supplying a common voltage to the common electrode, wherein the common electrode is connected through a common electrode contact hole formed through the common line and the passivation layers.

The apparatus may further include an out-gassing blocking spacer formed in the common electrode contact hole to protrude.

In addition, manufacturing a liquid crystal display panel including a thin film transistor substrate, a color filter substrate bonded to each other facing the thin film transistor, and an antistatic transparent electrode formed on each of an upper surface of the thin film transistor substrate and a rear surface of the color filter substrate. A method, comprising: forming a first conductive pattern comprising a gate electrode, a gate line, and a common line on a substrate; depositing a gate insulating film on the substrate on which the first conductive pattern is formed; Forming a second conductive pattern including a pattern, a source and a drain electrode, and a data line, depositing first and second passivation layers on the substrate on which the second conductive pattern is formed, and forming the first and second passivation layers. A first pixel contact hole penetrating to expose the drain electrode and a common electrode contact hole exposing the common line; Forming a third conductive pattern on the first and second passivation layers, the third conductive pattern including a common electrode connected to the common line, and depositing a third passivation layer on the substrate on which the third conductive pattern is formed. Forming a second pixel contact hole penetrating the third passivation layer to expose the drain electrode; and a pixel electrode having a plurality of finger parts formed parallel to the data line on a substrate on which the third conductive pattern is formed. And forming column spacers protruding from the first and second pixel contact holes.

The apparatus may further include an out-gassing blocking spacer formed in the common electrode contact hole to protrude.

A liquid crystal display panel and a method of manufacturing the same according to the present invention form a first out-gassing blocking spacer formed and protruding in the pixel contact holes, and a second out-gassing blocking spacer formed and protruding in the common electrode contact hole. As a result, the outgassing generated from the protective film can be prevented by the first and second outgassing blocking spacers, thereby preventing the occurrence of bubbles in the liquid crystal display panel.

1 is an image screen in which bubbles are generated in a liquid crystal display panel using a thin film transistor substrate of a conventional fringe electric field method.
2 is a plan view illustrating a thin film transistor substrate according to an exemplary embodiment of the present invention.
3 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 2 taken along lines II ′, II-II ′, III-III ′, IV-IV ′, and V-V ′.
4A and 4B are plan views and cross-sectional views illustrating a method of manufacturing the first conductive pattern of the thin film transistor substrate illustrated in FIGS. 2 and 3.
5A and 5B are plan views and cross-sectional views illustrating a method of manufacturing the second conductive pattern of the thin film transistor substrate illustrated in FIGS. 2 and 3.
6A and 6B are plan views and cross-sectional views illustrating a method of manufacturing the first and second passivation layers of the thin film transistor substrate illustrated in FIGS. 2 and 3.
7A and 7B are plan views and cross-sectional views illustrating a method of manufacturing the third conductive pattern of the thin film transistor substrate illustrated in FIGS. 2 and 3.
8A and 8B are plan views and cross-sectional views illustrating a method of manufacturing a third passivation film of the thin film transistor substrate illustrated in FIGS. 2 and 3.
9A and 9B are plan views and cross-sectional views illustrating a method of manufacturing a fourth conductive pattern of the thin film transistor substrate illustrated in FIGS. 2 and 3.
FIG. 10 is a cross-sectional view illustrating a method of manufacturing an out gassing blocking spacer of the thin film transistor substrate illustrated in FIGS. 2 and 3.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The construction of the present invention and the effects thereof will be clearly understood through the following detailed description. Prior to the detailed description of the present invention, the same components will be denoted by the same reference numerals as much as possible even if shown on different drawings, and the known components will be omitted if it is determined that the gist of the present invention may obscure the gist of the present invention. do.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS.

FIG. 2 is a plan view illustrating a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIG. 3 illustrates the thin film transistor substrate shown in FIG. 2 as shown in FIGS. Is a cross-sectional view taken along the line VV '.

According to an exemplary embodiment of the present invention, a liquid crystal display panel includes a thin film transistor substrate, a color filter substrate (not shown) formed to face each other, a static electricity formed on each of an upper surface of the thin film transistor substrate and a lower surface of the color filter substrate. It includes a preventive transparent electrode (not shown).

2 and 3 have a gate line 102 and a data line 104, a gate line 102 and data defining a pixel region by crossing the gate insulating layer 112 therebetween on a lower substrate. The thin film transistor connected to the intersection of the line 104, the first and second pixel electrodes 122a and 122b connected to the drain electrode 110 of the thin film transistor, and the first and second pixel electrodes 122a and 122b. The common electrode 124 forming the fringe field, the gate pad 150 connected to the gate line 102, the data pad 160 connected to the data line 104, and the common line 126. The common pads 128 and the out-gassing blocking spacers 230 and 232 to block out-gassing generated from the passivation layer covering the thin film transistors.

The gate line 102 supplies a scan signal from a gate driver (not shown) through the gate pad 150, and the data line 104 receives a pixel signal from a data driver (not shown) through the data pad 160. Supply. The gate line 102 and the data line 104 cross each other with the gate insulating layer 112 therebetween to define respective pixel regions.

The thin film transistor allows the pixel signal supplied to the data line 104 to be charged and held in the pixel electrode 122 in response to the scan signal supplied to the gate line 102. To this end, the thin film transistor 130 includes a gate electrode 106 connected to a gate line, a source electrode 108 connected to a data line, a drain electrode 110 formed to face the source electrode, and a gate insulating film 112. ) And an active layer 114 overlapping the gate electrode 106 to form a channel between the source electrode 108 and the drain electrode 110, and the ohmic contact with the source electrode 108 and the drain electrode 110. The ohmic contact layer 116 is formed on the active layer 114 except for the channel portion. The semiconductor pattern 115 including the active layer 114 and the ohmic contact layer 116 is included in each of the data line 104 and the data pad lower electrode 162.

The pixel electrode is connected to the drain electrode 110 of the thin film transistor through the first and second pixel contact holes 120a and 120b. Accordingly, the pixel electrode is supplied with the pixel signal from the data line 104 through the thin film transistor.

The pixel electrode overlaps the common electrode 124 with the third passivation layer 132b interposed therebetween to form a fringe field. The pixel electrode is formed in parallel with the upper pixel electrode 220a positioned on the common line 124 and the gate line 102, and the lower pixel electrode 220b positioned on the gate line 102 and the data line. It includes a plurality of fingers 122 formed side by side.

In this case, the plurality of fingers are formed parallel to the data line 104, and are formed in an oblique diagonal direction to have a first inclination θ1 while being symmetric with respect to the center of each pixel area parallel to the gate line 102. . At this time, the center portion is inclined to have a second inclination θ2 that is inclined more than an inclined diagonal angle. For example, the angle θ1 of the first slope may be 7 ° and the angle θ2 of the second slope may be 45 °.

Accordingly, the liquid crystal molecules are symmetrically arranged by the fringe electric field formed between the common electrode 124 and the pixel electrode 122 to form a multi-domain, thereby improving the viewing angle.

The common electrode 124 is connected through the common electrode contact hole 226 passing through the common line 126 and the first and second passivation layers 132a and 134. The common electrode 124 overlaps the pixel electrode to form a fringe field. The common electrode 124 is formed of a transparent electrode material, and as the transparent electrode material, tin oxide (TO), indium tin oxide (ITO), indium zinc oxide (IZO), and indium Tin zinc oxide (ITZO) and the like may be used.

The common line 126 supplies a reference voltage for driving the liquid crystal, that is, a common voltage to each common electrode. The common line 126 is formed in parallel with the data line 104 and is formed of the same material as the gate electrode 106.

The common pad includes a common pad lower electrode 226 formed by extending the common line 126, a common pad contact hole 128a formed through the first to third passivation layers 132a, 134, and 132b, and the gate insulating layer 112. The common pad upper electrode 128 is connected to the common pad lower electrode 226 through the common pad upper electrode 128.

The gate pad 150 supplies a scan signal from the gate driver (not shown) to the gate line 102. To this end, the gate pad 150 extends through the gate pad lower electrode 152 formed from the gate line 102, the first to third passivation layers 132a, 134, and 132b, and a first pass through the gate insulating layer 112. And a gate pad upper electrode 156 connected to the gate lower electrode 152 through the second gate contact holes 154a and 154b. The gate pad upper electrode 156 is formed of the same material on the same layer at the same time when forming the pixel electrode.

The data pad 160 supplies a pixel signal from a data driver (not shown) to the data line 104. To this end, the data pad 160 includes first and second data contact holes passing through the data pad lower electrode 162 and the first to third passivation layers 132a, 134, and 132b extending from the data line 104. And a data pad upper electrode 166 connected to the data pad lower electrode 162 through 164a and 164b. The data pad upper electrode 166 is formed of the same material on the same layer at the same time when forming the pixel electrode.

The out-gassing blocking spacers 230 and 232 are formed and protruded in the pixel contact holes 120a and 120b to block out-gassing generated from the second passivation layer 134 formed of photo acryl covering the thin film transistor. The first out-gassing blocking spacer 230 and the second out-gassing blocking spacer 232 protruded in the common electrode contact hole 226. The first and second out-gassing blocking spacers 230 and 232 serve to maintain a cell gap between the thin film transistor substrate and the color filter substrate.

Specifically, in order to reduce the occurrence of parasitic capacitors between the common electrode 124 and the data line 104, the second protective layer 134 is formed of photoacrylic, an organic insulating material, to form a distance between the common electrode 124 and the data line 104. You can widen it. However, photoacryl can reduce parasitic capacitors, but there is a problem that out-gassing occurs.

Outgassing generated from photoacrylic is more formed when the thin film transistor substrate and the color filter substrate are bonded together, and then an antistatic transparent electrode is formed on each of the two substrates. This progresses in a high temperature and high vacuum state during the sputtering process to simultaneously form a high vacuum state at the time of bonding and to form an antistatic transparent electrode, thereby further causing outgassing inside the liquid crystal display panel.

In this case, out-gassing is further generated due to a step between the first to third passivation layers 132a, 134 and 132b, and the pixel contact holes 120a and 120b, and the first and second passivation layers 132a and 134. Outgassing is further generated due to the step between the common electrode contact holes 226.

Thus, the first out-gassing blocking spacer 230 is formed in the pixel contact holes 120a and 120b to block out-gassing coming out of the pixel contact holes 120a and 120b, and the second out-gassing blocking spacer 232 is formed. Is formed in the common electrode contact hole 226 to block out outings coming from the common electrode contact hole 226.

4A through 10B are plan views and cross-sectional views illustrating a method of manufacturing the thin film transistor substrate illustrated in FIG. 3.

4A and 4B, a first conductive pattern including a gate electrode 106, a gate line 102, a common line 126, and a gate pad lower electrode 152 is formed on the substrate 101. .

Specifically, at least two gate metal layers are formed on the substrate 101 through a deposition method such as a sputtering method. As the gate metal layer, Al / Cr, Al / Mo, Al (Nd) / Al, Al (Nd) / Cr, Mo / Al (Nd) / Mo, Cu / Mo, Cu / Mo / Ti, Ti / Al (Nd ) / Ti, Mo / Al, Mo / Ti / Al (Nd), Cu alloy / Mo, Cu alloy / Al, Cu alloy / Mo alloy, Cu alloy / Al alloy, Al / Mo alloy, Mo alloy / Al, Al It is formed in a structure in which two or more layers are laminated, such as alloy / Mo alloy, Mo alloy / Al alloy, Mo / Al alloy, or Mo, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, Al alloy, etc. It can be formed into a single layer. Subsequently, the gate electrode layer 106, the gate line 102, the common line 126, and the gate pad lower electrode are patterned by patterning a gate metal layer using a photoresist pattern formed through an exposure process and a development process using a first mask as a mask. A first conductive pattern including 152 is formed.

5A and 5B, the gate insulating layer 112 is formed on the substrate 101 on which the first conductive pattern is formed, and the active layer 114 and the ohmic contact are formed on the substrate 101 on which the gate insulating layer 112 is formed. A second conductive pattern including the semiconductor pattern 115 including the layer 116, the source and drain electrodes 108 and 110, the data line 104, and the data pad lower electrode 162 is formed.

In detail, the gate insulating layer 112, the amorphous silicon layer, and the amorphous silicon layer doped with impurities (n + or p +) are sequentially formed on the lower substrate 101 on which the first conductive pattern is formed by a deposition method such as PECVD. The data metal layer is formed on the deposition method by sputtering or the like. As the gate insulating layer 112, an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or the like is used, and as the data metal layer, Mo, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, Al Metal materials such as alloys are used as a single layer, or Al / Cr, Al / Mo, Al (Nd) / Al, Al (Nd) / Cr, Mo / Al (Nd) / Mo, Cu / Mo, Ti / Al (Nd) / Ti, Mo / Al, Mo / Ti / Al (Nd), Cu alloy / Mo, Cu alloy / Al, Cu alloy / Mo alloy, Cu alloy / Al alloy, Al / Mo alloy, Mo alloy / Al , Al alloy / Mo alloy, Mo alloy / Al alloy, Mo / Al alloy or the like is used in a structure in which two or more layers are laminated.

After the photoresist is applied on the data metal layer, the active layer 114 formed on the gate insulating layer by patterning the amorphous silicon layer and the data metal layer using a photoresist pattern formed through an exposure process and a development process using a second mask as a mask. ) And a second conductive pattern including a semiconductor pattern 115 including an ohmic contact layer 116, a source electrode 108 and a drain electrode 110, a data line 104, and a data pad lower electrode 162. Is formed. For example, the second mask may be formed using a slit mask or a halftone mask to form photoresist patterns having different thicknesses of the photoresist, thereby forming the semiconductor pattern 115 and the source and drain electrodes 108 and 110 in the same process. Can be formed.

6A and 6B, a first gate contact hole 154a, a first data contact hole 164a, a first pixel contact hole 120a, and a common electrode on a substrate 101 on which a second conductive pattern is formed. First and second passivation layers 132a and 134 having contact holes 226 are formed.

Specifically, the first and second passivation layers 132a and 134 are deposited on the gate insulating layer 112 on which the semiconductor pattern 115 and the second conductive pattern are formed by PECVD or CVD. The first passivation layer 132a may be formed of an inorganic insulating material such as a gate insulating layer, and the second passivation layer 134 may be formed of an organic insulating material such as photoacrylic. The first and second passivation layers 132a and 134 may be formed by patterning the first and second passivation layers 132a and 134 using photoresist patterns formed through exposure and development processes using a third mask as masks. The gate contact hole 154a, the first data contact hole 164a, the first pixel contact hole 120a, and the common electrode contact hole 226 are formed. The first pixel contact hole 120a penetrates the first and second passivation layers 132a and 134 to expose the drain electrode 110, and the first gate contact hole 154a includes the gate insulating layer 112, the first and second The gate pad lower electrode 152 is exposed through the second passivation layers 132a and 134, and the first data contact hole 164a penetrates the first and second passivation layers 132a and 134 to expose the data pad lower electrode ( The common electrode contact hole 226 exposes the gate line 126 through the gate insulating layer 112 and the first and second passivation layers 132a and 134.

7A and 7B, a third conductive pattern including the common electrode 124 is formed on the substrate 101 on which the first and second passivation layers 132a and 134 are formed.

Specifically, a transparent conductive layer is formed on the substrate 101 on which the first and second passivation layers 132a and 134 are formed. The transparent electrode layer may be tin oxide (TO), indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO) by a sputtering method. Can be deposited. Subsequently, a third conductive pattern including the common electrode 124 is formed by patterning the transparent electrode layer using a photoresist pattern formed through an exposure process using a fourth mask and a developing process as a mask.

8A and 8B, a second gate contact hole 154b, a second data contact hole 164b, and a second pixel contact hole 120b are included on a substrate 101 on which a third conductive pattern is formed. The third passivation layer 132b exposing the common electrode 124 is formed.

Specifically, the third passivation layer 132b is deposited on the substrate 101 on which the third conductive pattern is formed by PECVD or CVD. The third passivation layer 132b may be formed of an inorganic insulating material such as a gate insulating layer. The third passivation layer 132b may be formed by patterning the third passivation layer 132b using a photoresist pattern formed through an exposure process and a development process using a fifth mask as a mask, thereby forming the second gate contact hole 154b and the second passivation layer. The data contact hole 164b and the second pixel contact hole 120a are formed, and the common electrode 124 is exposed. The second pixel contact hole 120b penetrates through the third passivation layer 132b to expose the drain electrode 110, and the second gate contact hole 154b penetrates through the third passivation layer 132b to form a gate pad lower electrode ( 152 is exposed, and the second data contact hole 164b penetrates through the third passivation layer 132b to expose the data pad lower electrode 162.

Referring to FIGS. 9A and 9B, a first pixel electrode 122a, a gate pad upper electrode 156, and a data pad upper electrode 166 may be formed on a substrate 101 on which a third passivation layer 132b is formed. 4 A conductive pattern is formed.

Specifically, a transparent electrode layer is formed on the substrate 101 on which the third protective film 132b is formed. The transparent electrode layer may be tin oxide (TO), indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO) by a sputtering method. Can be deposited. Subsequently, the first pixel electrode 122a and the gate pad upper electrode 156 are formed on the third passivation layer 132b by patterning the transparent electrode layer using the photoresist pattern formed through the exposure process and the development process using the sixth mask as a mask. ), A fourth conductive pattern including the data pad upper electrode 166 is formed.

Here, the pixel electrode 122 includes an upper pixel electrode positioned above the common line, a parallel to the gate line, a lower pixel electrode positioned above the gate line, and a plurality of finger parts formed parallel to the data line. .

Accordingly, the pixel electrode is connected to the drain electrode 110 through the first and second pixel contact holes 120a and 120b, and the gate pad upper electrode 156 is connected to the first and second gate contact holes 154a and 154b. The bottom pad electrode 152 is connected to the gate pad lower electrode 152, and the top pad data electrode 166 is connected to the data pad lower electrode 162 through the first and second data contact holes 164a and 164b.

Referring to FIG. 10, first and second out-gassing blocking spacers 230 and 232 are formed on a substrate on which a fourth conductive pattern is formed.

Specifically, a photosensitive material is formed on the substrate 101 on which the fourth conductive pattern is formed. A first out-gassing blocking spacer 230 formed in the first and second pixel contact holes 120a and 120b and protruding by patterning the photosensitive material through an exposure process and a development process using a seventh mask, and a common electrode contact. A second out guest blocking spacer 232 is formed in the hole 226 to protrude.

After bonding the thin film transistor substrate and the color filter substrate provided by the above-described manufacturing process, a transparent electrode for preventing static electricity is formed on each of the upper surface of the thin film transistor substrate and the lower surface of the color filter substrate by a sputtering method or the like.

Accordingly, a liquid crystal display panel on which an antistatic transparent electrode is formed is provided.

The above description is merely illustrative of the present invention, and various modifications may be made by those skilled in the art without departing from the technical spirit of the present invention. Therefore, the embodiments disclosed in the specification of the present invention are not intended to limit the present invention. The scope of the present invention should be construed by the claims below, and all techniques within the scope equivalent thereto will be construed as being included in the scope of the present invention.

106: gate electrode 108: source electrode
110 drain electrode 112 gate insulating film
114: active layer 116: ohmic contact layer
132a, 132b, 134: first to third protective films
122: pixel electrode
124: common electrode 126: common line
150: gate pad 160: data pad
220a: upper pixel electrode 220b: lower pixel electrode
230, 232: first and second out guest blocking spacers

Claims (5)

A liquid crystal display panel comprising a thin film transistor substrate, a color filter substrate bonded to and facing the thin film transistor, and an antistatic transparent electrode formed on each of an upper surface of the thin film transistor substrate and a rear surface of the color filter substrate.
The thin film transistor substrate
A thin film transistor formed on the substrate;
Protective layers formed to cover the thin film transistor and including pixel contact holes exposing a drain electrode of the thin film transistor;
A pixel electrode connected to the drain electrode;
A common electrode forming a fringe field with the pixel electrode;
A common line supplying a common voltage to the common electrode;
A common electrode contact hole formed through the common line and the passivation layers;
First and second protrusions protruding in the pixel contact holes and the common electrode contact hole to block out-gassing generated from the passivation layers covering the thin film transistor and to maintain a cell gap between the thin film transistor substrate and the color filter substrate. And a 2 out-gassing blocking spacer. delete delete A thin film transistor substrate, a color filter substrate bonded to each other facing the thin film transistor, and an antistatic transparent electrode formed on each of the upper surface of the thin film transistor substrate and the rear surface of the color filter substrate. In
Forming a first conductive pattern comprising a gate electrode, a gate line, and a common line on the substrate;
Depositing a gate insulating film on the substrate on which the first conductive pattern is formed, and forming a second conductive pattern including a semiconductor pattern, a source and drain electrode, and a data line on the gate insulating film;
A first pixel contact hole for depositing first and second passivation layers on the substrate on which the second conductive pattern is formed and exposing the drain electrode through the first and second passivation layers, and a common line exposing the common line; Forming an electrode contact hole;
Forming a third conductive pattern on the first and second passivation layers, the third conductive pattern including a common electrode connected to the common line;
Depositing a third passivation layer on the substrate on which the third conductive pattern is formed, and forming a second pixel contact hole penetrating the third passivation layer to expose the drain electrode;
Forming a pixel electrode on the substrate on which the third conductive pattern is formed, the pixel electrode having a plurality of finger portions formed in parallel with the data lines;
First and second protrusions protruding in the pixel contact holes and the common electrode contact hole to block out-gassing generated from the passivation layers covering the thin film transistor and to maintain a cell gap between the thin film transistor substrate and the color filter substrate. Forming an out-gassing blocking spacer. delete

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