KR20130064262A - Thin film transistor substrate and method of fabricating the same - Google Patents

Abstract

PURPOSE: A TFT(Thin Film Transistor) substrate and a manufacturing method thereof are provided to reduce the thickness of a protection film by reducing the capacity of a parasitic capacitor between a common line and a data line, thereby reducing power consumption. CONSTITUTION: A TFT is connected to a gate line(102) and a data line(104). A pixel electrode(122) is formed in a pixel region and is connected to the TFT. A common electrode(136) is formed in the pixel region and forms a fringe field with the pixel electrode. A common line(132) overlaps with the data line with a line width narrower than the data line or is formed on both sides of the data line.

Description

Thin film transistor substrate and manufacturing method therefor {THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF FABRICATING THE SAME}

The present invention relates to a thin film transistor substrate and a method of manufacturing the same, which can reduce power consumption and increase panel size.

In general, the liquid crystal display (Liquid Crystal Display) is a flat panel display device that displays an image using a liquid crystal, it is thinner and lighter than other display devices, and has the advantages of low driving voltage and low power consumption, It is widely used throughout.

Such a liquid crystal display device includes a liquid crystal display panel having a thin film transistor substrate and a color filter substrate facing each other with a liquid crystal therebetween.

The color filter substrate comprises a black matrix formed on the upper substrate for preventing light leakage, a color filter for color implementation, and an upper alignment film formed thereon for liquid crystal alignment.

The thin film transistor substrate includes a gate line and data lines formed on a lower substrate, a thin film transistor formed of a switch element at each intersection of the gate lines and the data lines, a pixel electrode formed of liquid crystal cells and connected to the thin film transistor, and a pixel. It consists of the common electrode which forms an electric field with an electrode, and the orientation film apply | coated on them. Here, the thin film transistor supplies the pixel electrode with a video signal supplied to the data line in response to the scan signal supplied to the gate line.

The data line of the conventional liquid crystal display panel is formed adjacent to the pixel electrode. In this case, due to the coupling action of parasitic capacitance existing between the data line and the pixel electrode, a ripple phenomenon occurs in which the pixel voltage supplied to the pixel electrode swings according to the video signal supplied to the data line, thereby causing crosstalk. There is this.

In order to solve the above problems, the present invention is to provide a thin film transistor substrate and a manufacturing method capable of reducing power consumption and panel size.

In order to achieve the above technical problem, a thin film transistor substrate according to the present invention includes a gate line formed on the substrate; A data line crossing the gate line to provide a pixel area; A thin film transistor connected to the gate line and the data line; A pixel electrode connected to the thin film transistor and formed in the pixel region; A common electrode formed in the pixel region to form a fringe electric field with the pixel electrode; And a common line formed to overlap the data line with a line width smaller than that of the data line or formed on both sides of the data line.

The common line formed to overlap the data line with a line width smaller than the data line may be formed to have a line width of about 2 to 5 μm.

The common line formed on both sides of the data line is formed to be spaced apart from the data line by about 0 to 3㎛.

Common lines formed on both sides of the data line are formed adjacent to the same plane as the pixel electrode positioned at the edge of the pixel area to form a horizontal electric field, and the pixel electrode is formed on the same plane as the gate line. It is characterized in that to form a fringe electric field with the common electrode.

One of the pixel electrode and the common electrode has a plurality of slits parallel to any one of the gate line and the data line, and the slits are inclined diagonally while being symmetric with respect to the center line of each sub-pixel parallel to the gate line. Characterized in that formed.

In order to achieve the above technical problem, a method of manufacturing a thin film transistor substrate according to the present invention is to form a gate line, a gate electrode connected to the gate line, any one of a pixel electrode and a common electrode on the substrate Steps; A semiconductor pattern on the gate line, the gate electrode, a substrate on which the driving electrode is formed, a data line intersecting the gate line to form a pixel region, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode Forming a; Forming a common line in the pixel area and overlapping the data line with a line width smaller than the data line and forming common lines positioned at both sides of the data line at the same time as forming a driving electrode of the other one of the pixel electrode and the common electrode; Characterized in that.

The present invention has a common line formed on both sides of the data line or overlapping the data line with a line width smaller than that of the data line. Accordingly, the present invention can reduce the capacitance of the parasitic capacitor between the common line and the data line, thereby reducing power consumption and increasing the size of the panel by reducing the thickness of the protective film.

1 is a plan view illustrating a thin film transistor substrate according to a first embodiment of the present invention.
2 is a sectional view showing a thin film transistor substrate taken along the line "I-I" in Fig.
3A and 3B are cross-sectional views illustrating aperture ratios according to line widths of the common line illustrated in FIGS. 1 and 2.
4A through 4D are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate illustrated in FIG. 2.
5 is a plan view illustrating a thin film transistor substrate according to a second exemplary embodiment of the present invention.
FIG. 6 is a cross-sectional view illustrating the thin film transistor substrate cut along the line “II-II ′” in FIG. 5.
7A to 7D are cross-sectional views illustrating in detail a method of manufacturing the thin film transistor substrate illustrated in FIG. 6.
8 is a plan view illustrating a thin film transistor substrate according to a third exemplary embodiment of the present invention.
FIG. 9 is a cross-sectional view illustrating the thin film transistor substrate taken along the line “III-III ′” in FIG. 8.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

1 is a plan view illustrating a thin film transistor substrate according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along line II ′.

The thin film transistor substrate illustrated in FIGS. 1 and 2 includes a gate line 102, a data line 104, and a gate line 102 that define a pixel region by crossing a gate insulating layer 112 therebetween on a lower substrate 101. And the thin film transistor TFT connected to the intersection of the data line 104 and the thin film transistor TFT to form a pixel electrode 122 formed in the pixel region, and a pixel electrode 122 and a fringe field in the pixel region. And a common line 132 connected to the common electrode 136.

Gate line 102 supplies a scan signal from a gate driver (not shown) and data line 104 supplies a video signal from a data driver (not shown). The gate line 102 and the data line 104 cross each other with the gate insulating layer 112 therebetween to define respective pixel regions.

The thin film transistor causes the video signal on the data line 104 to be charged and held in the pixel electrode 122 in response to the scan signal of the gate line 102. For this purpose, the thin film transistor is connected to the pixel electrode 122 facing the gate electrode 106 connected to the gate line 102, the source electrode 108 connected to the data line 104, and the source electrode 108. The active layer 114 and the source electrode 108 overlapping the gate line 102 with the drain electrode 110 and the gate insulating layer 112 interposed therebetween to form a channel between the source electrode 108 and the drain electrode 110. And an ohmic contact layer 116 formed on the active layer 114 except for the channel portion for ohmic contact with the drain electrode 110. The semiconductor pattern including the active layer 114 and the ohmic contact layer 116 is formed to overlap the data line 104.

Here, the gate electrode 106 and the gate line 102 are formed on at least a double layered structure including a transparent conductive layer on the substrate 101. For example, as shown in FIG. 2, the gate electrode 106 and the gate line 102 include a first conductive layer 106a using a transparent conductive layer and a second conductive layer 106b using an opaque metal. It is formed into a stacked double structure. In this case, ITO, TO, IZO, ITZO, etc. are used for the 1st conductive layer 106a, and Cu, Mo, Al, Cu alloy, Mo alloy, Al alloy etc. are used for the 2nd conductive layer 106b.

The pixel electrode 122 is formed in a plate shape on the substrate 101 and is formed of a transparent conductive layer. The pixel electrode 122 is exposed through the pixel contact hole 120 passing through the gate insulating layer 112 and the passivation layer 118, and the pixel electrode 122 exposed through the pixel contact hole 120 is formed of the thin film transistor. The drain electrode 110 and the pixel connection part 124 are connected to each other. The pixel electrode 122 overlaps the common electrode 136 with the gate insulating layer 112 and the passivation layer 118 therebetween to form a fringe field in each pixel area. That is, when the video signal is supplied through the thin film transistor, the pixel electrode 122 forms a fringe field with the common electrode 136 supplied with the common voltage to arrange the liquid crystal molecules in a horizontal direction between the thin film transistor substrate and the color filter substrate. Are rotated by dielectric anisotropy. The transmittance of light passing through the pixel region is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing the gradation.

The common electrode 136 is formed in each pixel area and is connected to the common line 132. In particular, the common electrode 136 is connected to the common electrode 136 of an adjacent pixel region with the data line 104 interposed therebetween through the common line 132. The slit 138 of the common electrode 136 is formed in an inclined diagonal direction while being symmetrical with respect to the center line of each pixel area parallel to the gate line 102. Accordingly, liquid crystal molecules are symmetrically arranged with respect to the slit by the fringe electric field formed between the common electrode 136 and the pixel electrode 122, thereby forming a multi-domain, thereby improving the viewing angle.

The common line 132 supplies a reference voltage for driving the liquid crystal, that is, a common voltage, to each common electrode 136. The common line 132 is formed on the passivation layer 118 so as to overlap the data line 104, and is formed in parallel with the data line 104. The common line 132 blocks the video signal supplied to the data line 104 from being coupled to the common electrode 136 through parasitic capacitance formed between the data line 104 and the pixel electrode 122. This minimizes the distortion of the video signal supplied to the pixel electrode 122 in accordance with the video signal of the data line 104, thereby preventing crosstalk.

On the other hand, if the line width WC1 of the common line 132 is larger than the line width WD of the data line 104 as shown in FIG. 3A, an overlapping area between the common line 132 and the data line 104 is formed. This widens. Accordingly, the capacitance of the parasitic capacitor between the common line 132 and the data line 104 is increased, which delays the video signal supplied through the data line 104. Therefore, the line width WC2 of the common line 132 of the present invention is smaller than the line width WD of the data line 104 as shown in FIG. 3B. For example, the common line 132 is formed to have a line width of about 2 ~ 5㎛. Accordingly, the present invention reduces the overlap area between the common line 132 and the data line 104, thereby reducing the capacitance of the parasitic capacitor between the common line 132 and the data line 104 as shown in Table 1 below. . That is, the present invention can reduce the capacitance of the parasitic capacitor between the common line 132 and the data line 104 by about 40% or more as shown in Table 1. Accordingly, the present invention can prevent the delay of the video signal supplied through the data line 104.

Cdc (parasitic capacitor between common line and data line) 3b structure can reduce Cdc by about 41.40% compared to FIG. 3a structure. 3a structure 3b structure 150.83 88.34

 In addition, when the line width WC1 of the common line 132 is formed to be larger than the line width WD of the data line, as shown in FIG. 3A, an intersection area between the common line 132 and the common electrode 136 is defined as the data line ( It is positioned between the 104 and the pixel electrode 122. That is, the intersection area of the common line 132 and the common electrode 136 where the discrimination is mainly generated is positioned between the data line 104 and the pixel electrode 122. Accordingly, since the line width WB1 of the black matrix 105 formed on the upper substrate 103 needs to be widened to block light leakage due to the disclination, the aperture ratio may be reduced.

On the other hand, when the line width WC2 of the common line 132 of the present invention is formed to be smaller than the line width WD of the data line 104 as shown in FIG. 3B, the liquid crystal may be abnormally operated to cause light leakage. An intersection area of the common line 132 and the common electrode 136 where the discrimination occurs mainly is positioned on the data line 104. Accordingly, the present invention can reduce the line width WB2 of the black matrix 105 by blocking the light leakage due to the disclination by the data line 104, thereby improving the aperture ratio compared to the thin film transistor substrate shown in FIG. 3A. .

The thin film transistor substrate according to the first embodiment of the present invention having such a configuration is formed in a four mask process as follows.

Referring to FIG. 4A, a first conductive pattern including a gate line 102, a gate electrode 106, and a pixel electrode 122 is formed on a lower substrate 101 by a first mask process. Specifically, the first and second conductive layers 106a and 106b are stacked on the lower substrate 101 through a deposition method such as a sputtering method. As the first conductive layer 106a, a transparent conductive material such as ITO, TO, IZO, ITZO, or the like, and as the second conductive layer 106b, a metal such as Mo, Ti, Cu, AlNd, Al, Cr, or an alloy thereof, etc. The material is used as a single layer or in a multilayer structure using them. Next, the first and second conductive layers 106a and 106b are patterned by using a photoresist pattern formed through a photolithography process using a halftone mask or a slit mask as a mask, The pixel electrode 122 made of only the first conductive layer 106a is formed.

Referring to FIG. 4B, the gate insulating layer 112 is formed on the lower substrate 101 on which the first conductive pattern is formed, and the active layer 114 and the ohmic contact layer (that are stacked on the gate insulating layer 112 by a second mask process). A semiconductor pattern including the 116 and a second conductive pattern including the data line 104, the source electrode 108, and the drain electrode 110 are formed.

Specifically, an amorphous silicon layer doped with a gate insulating layer 112, an amorphous silicon layer, and impurities (n + or p +) is sequentially formed on a lower substrate 101 on which a first conductive pattern is formed by a deposition method such as PECVD, And a source / drain metal layer is formed thereon by a deposition method such as sputtering. As the gate insulating layer 112, an inorganic insulating material such as SiOx, SiNx, or the like is used. As the source / drain metal layer, a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, or an alloy thereof is used as a single layer or a multilayer structure using them. Then, the gate insulating film is patterned by patterning the amorphous silicon layer, the amorphous silicon layer doped with impurities (n + or p +) and the source / drain metal layer using a photoresist pattern formed through a photolithography process using a halftone mask or a slit mask as a mask. An active layer 114, an ohmic contact layer 116, a data line 104, a source electrode 108 and a drain electrode 110 are formed on the 112.

Referring to FIG. 4C, the passivation layer 118 having the pixel contact hole 120 is formed on the gate insulating layer 112 on which the second conductive pattern is formed in the third mask process.

In detail, the passivation layer 118 is formed on the gate insulating layer 112 on which the second conductive pattern is formed by PECVD, spin coating, spinless coating, or the like. As the passivation layer 118, an inorganic insulating material such as the gate insulating layer 112 is used, or an organic insulating material is used. The pixel contact hole 120 is formed by patterning the passivation layer 118 and the gate insulating layer 112 on the passivation layer 118 by a photolithography process and an etching process using a third photomask. The pixel contact hole 120 may pass through the gate insulating layer 112 and the passivation layer 118 to expose the drain electrode 110 and the pixel electrode 122.

Referring to FIG. 4D, a third conductive pattern including the pixel connection part 124, the common electrode 136, and the common line 132 is formed on the passivation layer 118 by a fourth mask process.

Specifically, a transparent conductive layer is formed on the protective film 118 by a deposition method such as sputtering. As the transparent conductive layer, the same ITO, TO, IZO, ITZO, or the like as the first conductive layer 106a of the first conductive pattern is used. Next, a third conductive pattern including the pixel connection part 124, the common electrode 136, and the common line 132 is formed by patterning the transparent conductive layer through a photolithography process and an etching process using a fourth photo mask. . The pixel connector 124 is connected to the drain electrode 110 and the pixel electrode 122 exposed through the pixel contact hole 108. Therefore, the pixel electrode 122 is connected to the drain electrode 110 through the pixel connection part 124.

Meanwhile, after the third conductive pattern is formed, the slit 138 of the common electrode 136 is formed in parallel with the gate line 102 to form an alignment layer (not shown) through a horizontal rubbing process in parallel with the gate line 102. do.

FIG. 5 is a plan view illustrating a thin film transistor substrate according to a second exemplary embodiment of the present invention, and FIG. 6 is a cross-sectional view illustrating a thin film transistor substrate cut along a line “II-II ′” in FIG. 5.

The thin film transistor substrate shown in FIGS. 5 and 6 has the same components except that the common line is located on both sides of the data line so that the common line is not overlapped with the data line as compared to the thin film transistor substrates shown in FIGS. 1 and 2. Equipped. Accordingly, detailed description of the same constituent elements will be omitted.

The pixel electrode 122 is connected to the drain electrode 110 of the thin film transistor exposed on the passivation layer 118 through the pixel contact hole 120. The pixel electrode 122 overlaps the common electrode 136 with the gate insulating layer 152 and the passivation layer 154 therebetween to form a fringe field in each pixel area. That is, when the video signal is supplied through the thin film transistor, the pixel electrode 122 forms a fringe field with the common electrode 136 supplied with the common voltage to arrange the liquid crystal molecules in a horizontal direction between the thin film transistor substrate and the color filter substrate. Are rotated by dielectric anisotropy. The transmittance of light passing through the pixel region is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing the gradation.

In addition, the slit 128 of the pixel electrode 122 is formed in an inclined diagonal direction while being symmetrical with respect to the center line of each pixel area parallel to the gate line 102. Accordingly, liquid crystal molecules are symmetrically arranged with respect to the slit 128 by a fringe electric field formed between the common electrode 136 and the pixel electrode 122, thereby forming a multi-domain, thereby improving a viewing angle. .

The common electrode 136 is formed in a plate shape on the substrate 101 and is formed of a transparent conductive layer. The common electrode 136 is a common electrode 136 of an adjacent pixel region with the data line 104 interposed therebetween through a first common connector 134 formed to intersect the data line 104 and the common line 132. Connected with. The common electrode 136 is connected to the common electrode 136 of the adjacent pixel region with the gate line 102 interposed therebetween through the second common connection 144 formed to cross the gate line 102.

The common line 132 supplies a reference voltage for driving the liquid crystal, that is, a common voltage, to each common electrode 136 through the common connector 134. The common line 132 is connected to the common connector 134 exposed through the common contact hole 130 penetrating the gate insulating layer 112 and the passivation layer 118.

The common line 132 is formed on the passivation layer 118 on both sides of the data line 104 in parallel with the data line 104. In this case, the common line 132 is formed to be spaced apart at a distance D1 of 0 to 3 μm so as not to overlap with the data line 104.

The common line 132 blocks the video signal supplied to the data line 104 from being coupled to the common electrode 136 through parasitic capacitance formed between the data line 104 and the pixel electrode 122. This minimizes the distortion of the video signal supplied to the pixel electrode 122 in accordance with the video signal of the data line 104, thereby preventing crosstalk.

In addition, since the common line 132 is disposed on both sides of the data line 104 without overlapping the data line 104, the thickness of the passivation layer 118 may be reduced. That is, in the related art, in order to reduce the parasitic capacitance between the common line and the data line, the thickness of the passivation layer is thick, but in the present invention, since the common line 132 does not overlap the data line 104, the common line 132 and the data line The parasitic capacitance between the 104 is reduced, so that the thickness of the protective film 118 can be reduced than before. For example, the conventional protective film is formed to a thickness of about 6000 ~ 7000mmW while the protective film of the present invention is formed to a thickness of 2000 ~ 4000Åm. Accordingly, in the present invention, the distance between the pixel electrode 122 and the common electrode 136 overlapping each other with the gate insulating layer 112 and the passivation layer 118 therebetween is also closer than that of the related art, thereby reducing power consumption and increasing the panel size. It becomes possible.

In addition, the common line 132 positioned at both sides of the data line 104 may improve the transmittance around the data line 104 by forming a horizontal electric field with the pixel electrode 122 positioned at the edge of each sub-pixel. Can be. In this case, the common line 132 is formed to be spaced apart from the pixel electrode 122 positioned at the edge of each sub pixel at a distance D2 of about 7 to 16 μm, and positioned at the edge of each sub pixel. The electrode 122 is formed to be spaced apart from the adjacent pixel electrode 122 with a slit 128 at a distance D3 of about 2 to 5 μm, and the pixel electrode 122 has a line width of about 2 to 5 μm. It is formed to have.

The thin film transistor substrate according to the second embodiment of the present invention having such a configuration is formed by a four mask process as follows.

Referring to FIG. 7A, a first mask process includes a gate line 102, a gate electrode 106, first and second common connectors 134 and 138, and a common electrode 136 on a lower substrate 101. 1 conductive pattern is formed. Specifically, the first and second conductive layers 106a and 106b are stacked on the lower substrate 101 through a deposition method such as a sputtering method. As the first conductive layer 106a, a transparent conductive material such as ITO, TO, IZO, ITZO, or the like, and as the second conductive layer 106b, a metal such as Mo, Ti, Cu, AlNd, Al, Cr, or an alloy thereof, etc. The material is used as a single layer or in a multilayer structure using them. Next, the first and second conductive layers 106a and 106b are patterned by using a photoresist pattern formed through a photolithography process using a halftone mask or a slit mask as a mask, The common electrode 136 consisting of only the first conductive layer 106a and the first and second common connecting portions 134 and 138 are formed. The first and second common connectors 134 and 138 may be formed in a double structure or may be formed only of the first conductive layer 106.

Referring to FIG. 7B, the gate insulating layer 112 is formed on the lower substrate 101 on which the first conductive pattern is formed, and the active layer 114 and the ohmic contact layer (that are stacked on the gate insulating layer 112 by a second mask process). A semiconductor pattern including the 116 and a second conductive pattern including the data line 104, the source electrode 108, and the drain electrode 110 are formed.

Specifically, an amorphous silicon layer doped with a gate insulating layer 112, an amorphous silicon layer, and impurities (n + or p +) is sequentially formed on a lower substrate 101 on which a first conductive pattern is formed by a deposition method such as PECVD, And a source / drain metal layer is formed thereon by a deposition method such as sputtering. As the gate insulating layer 112, an inorganic insulating material such as SiOx, SiNx, or the like is used. As the source / drain metal layer, a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, or an alloy thereof is used as a single layer or a multilayer structure using them. Then, the gate insulating film is patterned by patterning the amorphous silicon layer, the amorphous silicon layer doped with impurities (n + or p +) and the source / drain metal layer using a photoresist pattern formed through a photolithography process using a halftone mask or a slit mask as a mask. An active layer 114, an ohmic contact layer 116, a data line 104, a source electrode 108 and a drain electrode 110 are formed on the 112.

Referring to FIG. 7C, the passivation layer 118 having the pixel contact hole 120 and the common contact hole 130 is formed on the gate insulating layer 112 on which the second conductive pattern is formed in the third mask process.

In detail, the passivation layer 118 is formed on the gate insulating layer 112 on which the second conductive pattern is formed by PECVD, spin coating, spinless coating, or the like. The pixel contact hole 120 and the common contact hole 130 are formed by patterning the passivation layer 118 and the gate insulating layer 112 on the passivation layer 118 by a photolithography process and an etching process using a third photo mask. Here, the pixel contact hole 120 penetrates the passivation layer 118 to expose the drain electrode 110, and the common contact hole 130 penetrates the gate insulating layer 112 and the passivation layer 118 to form the common connection part 134. Expose

Referring to FIG. 7D, a third conductive pattern including the pixel electrode 122 and the common line 132 is formed on the passivation layer 118 by a fourth mask process.

Specifically, a transparent conductive layer is formed on the protective film 118 by a deposition method such as sputtering. As the transparent conductive layer, the same ITO, TO, IZO, ITZO, or the like as the first conductive layer 106a of the first conductive pattern is used. Subsequently, the transparent conductive layer is patterned by a photolithography process and an etching process using a fourth photo mask to form a third conductive pattern including the pixel electrode 122 and the common line 132. The pixel electrode 122 is connected to the drain electrode 110 exposed through the pixel contact hole 120, and the common line 132 is connected to the common connector 134 exposed through the common contact hole 130.

Meanwhile, after the third conductive pattern is formed, the slit 128 of the pixel electrode 122 is formed in parallel with the gate line 102, so that an alignment layer (not shown) is formed through a horizontal rubbing process in parallel with the gate line 102. do.

FIG. 8 is a plan view illustrating a thin film transistor substrate according to a third exemplary embodiment of the present invention, and FIG. 9 is a cross-sectional view illustrating a thin film transistor substrate cut along the line “III-III ′” in FIG. 8.

8 and 9 have the same components except that the slits of the pixel electrodes are formed in parallel with the data lines as compared to the thin film transistor substrates shown in FIGS. 5 and 6. Accordingly, detailed description of the same constituent elements will be omitted.

The pixel electrode 122 is formed on the passivation layer 118 to form a fringe electric field with the common electrode 136 formed on the substrate 101. The pixel electrode 122 is formed to have a plurality of slits 128 parallel to the data line 104. The slit 128 of the pixel electrode 122 is formed in an inclined diagonal direction while being symmetrical with respect to the center line of each sub-pixel parallel to the gate line 102. Accordingly, liquid crystal molecules are symmetrically arranged with respect to the slit 128 by a fringe electric field formed between the common electrode 136 and the pixel electrode 122, thereby forming a multi-domain, thereby improving a viewing angle. . Meanwhile, in the present invention, the slit 128 of the pixel electrode 122 is formed in parallel with the data line 104 to form an alignment layer (not shown) through a vertical rubbing process in parallel with the data line 104.

The common electrode 136 is formed in a plate shape on the substrate 101 and is formed of a transparent conductive layer. The common electrode 136 is connected to the common electrode 136 of an adjacent sub pixel through a common connection part 134 formed to cross the gate line 102.

The common line 132 is formed on the passivation layer 118 on both sides of the data line 104 in parallel with the data line 104. In this case, the common line 132 is formed to be spaced apart at a distance D1 of 0 to 3 μm so as not to overlap with the data line 104. The common line 132 blocks the video signal supplied to the data line 104 from being coupled to the common electrode 136 through parasitic capacitance formed between the data line 104 and the pixel electrode 122. This minimizes the distortion of the video signal supplied to the pixel electrode 122 in accordance with the video signal of the data line 104, thereby preventing crosstalk.

In addition, since the common line 132 is disposed on both sides of the data line 104 without overlapping the data line 104, the thickness of the passivation layer 118 may be reduced. Accordingly, in the present invention, the distance between the pixel electrode 122 and the common electrode 136 overlapping each other with the gate insulating layer 112 and the passivation layer 118 therebetween is also closer than that of the related art, thereby reducing power consumption and increasing the panel size. It becomes possible.

In addition, the common line 132 positioned at both sides of the data line 104 may improve the transmittance around the data line 104 by forming a horizontal electric field with the pixel electrode 122 positioned at the edge of each sub-pixel. Can be.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

102: gate line 104: data line
106: gate electrode 108: source electrode
110 drain electrode 112 gate insulating film
114: active layer 116: ohmic contact layer
118: protective film 120: pixel contact hole
122: pixel electrode 128, 138: slit
130: common contact hole 132: common line
136: common electrode

Claims (10)

A gate line formed on the substrate;
A data line crossing the gate line to provide a pixel area;
A thin film transistor connected to the gate line and the data line;
A pixel electrode connected to the thin film transistor and formed in the pixel region;
A common electrode formed in the pixel region to form a fringe electric field with the pixel electrode;
And a common line formed to overlap the data line with a line width smaller than that of the data line or formed on both sides of the data line. The method of claim 1,
And the common line formed to overlap the data line with a line width smaller than that of the data line, wherein the common line is formed to have a line width of about 2 to 5 μm. The method of claim 1,
The common line formed on both sides of the data line is thin film transistor substrate, characterized in that formed to be spaced apart from the data line by about 0 ~ 3㎛. The method of claim 3, wherein
Common lines formed on both sides of the data line are formed adjacent to the same plane as the pixel electrode positioned at the edge of the pixel area to form a horizontal electric field, and the pixel electrode is formed on the same plane as the gate line. A thin film transistor substrate comprising: forming a fringe electric field with the common electrode. The method of claim 1,
Any one of the pixel electrode and the common electrode has a plurality of slits parallel to any one of the gate line and the data line,
The slit is a thin film transistor substrate, characterized in that formed in the inclined oblique direction symmetrical with respect to the center line of each sub-pixel parallel to the gate line. Forming a gate line, a gate electrode connected to the gate line, and a driving electrode of any one of a pixel electrode and a common electrode on the substrate;
A semiconductor pattern on the gate line, the gate electrode, a substrate on which the driving electrode is formed, a data line intersecting the gate line to form a pixel region, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode Forming a;
Forming a common line in the pixel area and overlapping the data line with a line width smaller than the data line and forming common lines positioned at both sides of the data line at the same time as forming a driving electrode of the other one of the pixel electrode and the common electrode; Method of manufacturing a thin film transistor substrate, characterized in that. The method according to claim 6,
The common line formed to overlap the data line with a line width smaller than the data line is formed to have a line width of about 2 ~ 5㎛. The method according to claim 6,
The common line formed on both sides of the data line is formed so as to be spaced apart from the data line by about 0 ~ 3㎛. The method of claim 8,
Common lines formed on both sides of the data line are formed adjacent to the same plane as the pixel electrode positioned at the edge of the pixel area to form a horizontal electric field, and the pixel electrode is formed on the same plane as the gate line. And forming a fringe electric field with the common electrode. The method according to claim 6,
Any one of the pixel electrode and the common electrode has a plurality of slits parallel to any one of the gate line and the data line,
And wherein the slit is formed in an oblique oblique direction with respect to the center line of each sub-pixel parallel to the gate line.

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