KR102545697B1 - Liquid crystal display device and method for fabricating the same - Google Patents

Abstract

The present invention relates to a liquid crystal display device capable of improving the aperture ratio of the liquid crystal display device and reducing manufacturing cost by simplifying the process, comprising: a lower substrate and an upper substrate comprising a display area and a non-display area and spaced apart from each other; A liquid crystal layer between a lower substrate and an upper substrate; A first insulating layer located in a non-display area of the lower substrate and defining an opening; A common line located in the opening; Located in the opening and exposing a portion of the common line. a gate insulating layer having a common line contact hole; a common electrode disposed on the gate insulating layer and contacted and electrically connected to a common line through the common line contact hole; and wherein the common line contact hole extends along a portion of an edge of the opening.

Description

Liquid crystal display device and manufacturing method thereof

The present invention relates to a liquid crystal display device and a manufacturing method thereof, and more particularly, to a liquid crystal display device capable of reducing manufacturing cost by improving an aperture ratio of the liquid crystal display device and simplifying a process thereof, and a manufacturing method thereof.

A liquid crystal display (LCD) is one of the most widely used flat panel displays (FPD) and is composed of two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween.

A liquid crystal display is a display device that controls the amount of transmitted light by rearranging liquid crystal molecules in a liquid crystal layer by applying a voltage to two electrodes.

When the common line is formed of a low-resistance metal, an aperture ratio is reduced due to a contact hole for connecting the common line and the common electrode. In addition, since the number of processes for forming the low-resistance metal as the common wiring increases, the manufacturing cost of the liquid crystal display device may increase.

An object of the present invention is to provide a liquid crystal display capable of improving the aperture ratio of the liquid crystal display and simplifying the process.

A liquid crystal display device according to the present invention for achieving the above object is composed of a display area and a non-display area, and a lower substrate and an upper substrate spaced apart from each other; a liquid crystal layer between the lower substrate and the upper substrate; A first insulating layer positioned in a non-display area and defining an opening; a common line positioned in the opening; a gate insulating layer positioned in the opening and having a common line contact hole exposing a portion of the common line; positioned on the gate insulating layer; and a common electrode electrically connected to a common line through a common line contact hole, wherein the common line contact hole may extend along a portion of an edge of the opening.

The device may further include a drain electrode positioned on the gate insulating layer; a second insulating layer positioned on the drain electrode and having a drain contact hole; and a pixel electrode electrically connected to the drain electrode through the drain contact hole.

In the opening, the common line and the drain electrode may at least partially overlap.

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The common electrode may be discontinuous in an area overlapping the common line contact hole.

The common electrode may have a smaller area than the second insulating layer.

A method of manufacturing a liquid crystal display device according to the present invention for achieving the above object includes forming a gate line, a gate electrode, and a common line on a lower substrate; a gate insulating layer on the gate line, the gate electrode, and the common line. forming a; forming a semiconductor material on the gate insulating layer; forming a source electrode and a drain electrode on the semiconductor material; forming a first insulating layer on the source electrode and the drain electrode; forming an organic film on the first insulating layer; forming an opening in the first insulating layer and a common line contact hole in the gate insulating layer; forming a common electrode connected to a common line through a common line contact hole; forming a second insulating layer on the common electrode; forming a pixel electrode connected to the drain electrode through the drain contact hole, wherein the opening has a region in which a common line and the drain electrode at least partially overlap, and the common line contact hole and the drain contact hole are formed in the opening; The common line contact hole may extend along a portion of an edge of the opening.

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Forming the common electrode connected to the common line through the common line contact hole may include coating a transparent conductive material on the organic layer and the entire surface of the lower substrate including the organic layer; coating a photosensitive composition on a transparent conductive material; an exposure step of disposing a mask on the photosensitive composition and irradiating light; developing the exposed photosensitive composition; Etching the transparent conductive material using the developed photosensitive composition; ashing the photosensitive composition; may include.

Forming the second insulating layer on the common electrode may include applying a material for forming the second insulating layer to the entire surface of the lower substrate including a transparent conductive material; coating a photosensitive composition on a material for forming a second insulating layer; an exposure step of disposing a mask on the photosensitive composition and irradiating light; developing the exposed photosensitive composition; Etching the material for forming the second insulating layer using the developed photosensitive composition; ashing the photosensitive composition; may include.

Forming the common electrode connected to the common line through the common line contact hole may include coating a transparent conductive material on the entire surface of the lower substrate including the organic layer.

Forming the second insulating layer on the common electrode may include applying a material for forming the second insulating layer to the entire surface of the lower substrate including the transparent conductive material.

The method may further include forming a drain contact hole in the second insulating layer.

Forming the drain contact hole in the second insulating layer may include applying a photosensitive composition on a material for forming the second insulating layer; an exposure step of disposing a mask on the photosensitive composition and irradiating light; developing the exposed photosensitive composition; Etching the material for forming the second insulating layer using the developed photosensitive composition; etching a material for forming a common electrode using the developed photosensitive composition; ashing the photosensitive composition; may include.

A liquid crystal display device and a manufacturing method thereof according to the present invention provide the following effects.

First, the common line can be fabricated with one mask simultaneously with the gate electrode and the gate line. Accordingly, the manufacturing process of the liquid crystal display device can be simplified and the manufacturing cost can be reduced.

Second, since the contact hole for connecting the drain electrode and the pixel electrode and the contact hole for connecting the common line and the common electrode are all located in the opening of the first insulating layer, an aperture ratio can be improved.

1 is a plan view schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along line II′ of FIG. 1 .
3 is a plan view illustrating a gate insulating layer according to an exemplary embodiment of the present invention.
4 is a plan view illustrating a first insulating layer according to an embodiment of the present invention.
5 is a plan view schematically illustrating a liquid crystal display according to another exemplary embodiment of the present invention.
6 is a cross-sectional view taken along line II-II' of FIG. 5 .
7A to 7J are process cross-sectional views of the liquid crystal display of FIG. 1 .
8A to 8J are process cross-sectional views of the liquid crystal display of FIG. 5 .

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention belongs. It is provided to fully inform the holder of the scope of the invention, and the present invention is only defined by the scope of the claims. Thus, in some embodiments, well-known process steps, well-known device structures, and well-known techniques have not been described in detail in order to avoid obscuring the interpretation of the present invention. Like reference numbers designate like elements throughout the specification.

In the drawings, the thickness is shown enlarged to clearly express the various layers and regions. Like reference numerals have been assigned to like parts throughout the specification. When a part such as a layer, film, region, plate, etc. is said to be “on” another part, this includes not only the case where it is “directly on” the other part, but also the case where there is another part in between. Conversely, when a part is said to be "directly on" another part, it means that there is no other part in between. In addition, when a part such as a layer, film, region, plate, etc. is said to be "below" another part, this includes not only the case where it is "directly below" the other part, but also the case where another part is present in the middle. Conversely, when a part is said to be "directly below" another part, it means that there is no other part in between.

The spatially relative terms "below", "beneath", "lower", "above", "upper", etc. It can be used to easily describe the correlation between elements or components and other elements or components. Spatially relative terms should be understood as encompassing different orientations of elements in use or operation in addition to the orientations shown in the figures. For example, when flipping elements shown in the figures, elements described as “below” or “beneath” other elements may be placed “above” the other elements. Thus, the exemplary term “below” may include directions of both below and above. Elements may also be oriented in other orientations, and thus spatially relative terms may be interpreted according to orientation.

In this specification, when a part is said to be connected to another part, this includes not only the case where it is directly connected, but also the case where it is electrically connected with another element interposed therebetween. In addition, when a part includes a certain component, it means that it may further include other components without excluding other components unless otherwise specified.

In this specification, terms such as first, second, and third may be used to describe various components, but these components are not limited by the terms. The terms are used for the purpose of distinguishing one component from other components. For example, a first component may be termed a second or third component, etc., and similarly, a second or third component may be termed interchangeably, without departing from the scope of the present invention.

Unless otherwise defined, all terms (including technical and scientific terms) used in this specification may be used in a meaning commonly understood by those of ordinary skill in the art to which the present invention belongs. In addition, terms defined in commonly used dictionaries are not interpreted ideally or excessively unless explicitly specifically defined.

Hereinafter, a liquid crystal display device and a manufacturing method thereof according to the present invention will be described in detail with reference to FIGS. 1 to 8J.

FIG. 1 is a plan view schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II' of FIG. 1 . 3 is a plan view showing a gate insulating layer according to an embodiment of the present invention, and FIG. 4 is a plan view showing a first insulating layer according to an embodiment of the present invention.

Referring to FIGS. 1 and 2 , a liquid crystal display device according to an exemplary embodiment includes a lower panel and an upper panel facing each other and a liquid crystal layer positioned therebetween.

The lower panel includes a lower substrate 101, a gate line GL, a common line CL, a gate electrode GE, a gate insulating layer 121, a semiconductor layer SM, a data line DL, and a drain electrode DE. ), source electrode SE, first insulating layer 131, organic film 151, common electrode CE, second insulating layer 141, pixel electrode PE, upper substrate 201, light blocking layer 251 , a color filter 252 and a liquid crystal layer 300 .

The lower substrate 101 may be an insulating substrate having light transmission characteristics and flexible characteristics, such as a plastic substrate. However, it is not limited thereto, and the lower substrate 101 may be made of a hard substrate such as a glass substrate.

The gate line GL is positioned on the lower substrate 101 .

The gate line GL is made of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, or a copper-based metal such as copper (Cu) or a copper alloy. Alternatively, it may be made of a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy. Alternatively, the gate line GL may be made of any one of chromium (Cr), tantalum (Ta), and titanium (Ti). Meanwhile, the gate line GL may have a multilayer structure including at least two conductive layers having different physical properties.

Meanwhile, although not shown, an end portion of the gate line GL may be connected to another layer or an external driving circuit. An end portion of the gate line GL may have a larger area than other portions of the gate line GL.

The gate electrode GE is positioned on the lower substrate 101 .

As shown in FIG. 1 , the gate electrode GE may protrude from the gate line GL. Meanwhile, the gate electrode GE may be part of the gate line GL.

The gate electrode GE may have the same material and structure (multilayer structure) as that of the gate line GL. The gate line GL and the gate electrode GE may be simultaneously formed through the same process.

The common line CL is positioned on the lower substrate 101 .

According to one embodiment of the present invention, as shown in FIGS. 1 and 2 , the common line CL partially overlaps the drain electrode DE in the opening OP, which will be described later. Since the common line CL and the drain electrode DE are positioned on different layers, the common line CL and the drain electrode DE do not contact each other, so that a short circuit does not occur. Accordingly, the aperture ratio of the liquid crystal display device may be improved by overlapping the common line CL and the drain electrode DE on a plane.

The common line CL is spaced apart from the gate line GL and the gate electrode GE. Accordingly, the common line CL is electrically insulated from the gate line GL and the gate electrode GE to prevent a short circuit.

The common line CL may have the same material and structure (multilayer structure) as that of the gate line GL. The gate line GL and the common line CL may be simultaneously formed through the same process.

Meanwhile, although not shown, an end portion of the common line CL may be connected to another layer or an external driving circuit. An end portion of the common line CL may have a larger area than other portions of the common line CL.

Referring to FIG. 2 , the gate insulating layer 121 is positioned on the gate line GL, the gate electrode GE, and the common line CL.

According to an embodiment of the present invention, the gate insulating layer 121 has a common line contact hole 123 penetrating a portion thereof. A portion of the common line CL is exposed through the common line contact hole 123 , and the common line CL contacts and is electrically connected to a common electrode CE, which will be described later.

According to an embodiment of the present invention, as shown in FIG. 2 , the common line CL and the drain electrode DE are located on different layers and do not contact each other even when overlapped on a plane, resulting in a short circuit. I never do that. Accordingly, the aperture ratio of the liquid crystal display device may be improved by overlapping the common line CL and the drain electrode DE on a plane.

According to an embodiment of the present invention, the common line contact hole 123 may extend along an edge of the opening OP. For example, as shown in FIGS. 1 , 3 and 4 , a C shape may be formed along a portion of an edge of the opening OP on a plane.

According to an embodiment of the present invention, as shown in FIG. 1 , the common line contact hole 123 is spaced apart from the gate electrode GE and the gate line GL. Accordingly, the gate electrode GE and the gate line GL are insulated from the common line CL to prevent a short circuit.

The gate insulating layer 121 may be made of silicon nitride (SiNx) or silicon oxide (SiOx). The gate insulating layer 121 may have a multilayer structure including at least two insulating layers having different physical properties.

The semiconductor layer SM is positioned on the gate insulating layer 121 . The semiconductor layer SM overlaps at least a portion of the gate electrode GE. The semiconductor layer SM may be made of amorphous silicon or polycrystalline silicon.

The data line DL is positioned on the gate insulating layer 121 . Although not shown, an end of the data line DL may be connected to another layer or an external driving circuit. An end portion of the data line DL may have a larger area than other portions of the data line DL.

The data line DL crosses the gate line GL. Although not shown, where the data line DL and the gate line GL intersect, the data line DL may have a smaller line width than other portions thereof. Accordingly, the size of parasitic capacitance between the data line DL and the gate line GL may be reduced.

The data line DL may be made of refractory metals such as molybdenum, chromium, tantalum, and titanium or alloys thereof. The data line DL may have a multilayer structure including a refractory metal layer and a low resistance conductive layer. Examples of the multilayer structure include a double layer of chromium or molybdenum (or molybdenum alloy) lower layer and aluminum (or aluminum alloy) upper layer, molybdenum (or molybdenum alloy) lower layer and aluminum (or aluminum alloy) intermediate layer and molybdenum (or molybdenum alloy) layer. ) may include a triple layer of the upper layer. Meanwhile, the data line DL may be made of various other metals or conductors.

The source electrode SE is positioned on the semiconductor layer SM. Meanwhile, the source electrode SE is also positioned on the gate insulating layer 121 . As shown in FIG. 1 , the source electrode SE may be part of the data line DL. Although not shown, the source electrode SE may protrude from the data line DL. At least a portion of the source electrode SE overlaps the semiconductor layer SM and the gate electrode GE. The source electrode SE may have the same material and structure (multilayer structure) as the above-described data line DL. The source electrode SE and the data line DL may be simultaneously formed through the same process.

The drain electrode DE is positioned on the gate insulating layer 121 . At least a portion of the drain electrode DE overlaps the semiconductor layer SM and the gate electrode GE. The drain electrode DE is connected to the pixel electrode PE. The drain electrode DE may have the same material and structure (multilayer structure) as the aforementioned data line DL. The drain electrode DE and the data line DL may be simultaneously formed through the same process.

According to an exemplary embodiment, the drain electrode DE partially overlaps the common line CL in the opening OP, which will be described later, as shown in FIGS. 1 and 2 . The common line CL and the drain electrode DE are positioned on different layers.

Although not shown in the drawing, an ohmic contact layer may be positioned between the semiconductor layer SM and the drain electrode DE and between the semiconductor layer SM and the source electrode SE. The ohmic contact layer may be made of a material such as n+ hydrogenated amorphous silicon doped with an n-type impurity such as phosphorus at a high concentration or may be made of silicide. The ohmic contact layer may form a pair and be positioned on the semiconductor layer SM.

The first insulating layer 131 is positioned on the data line DL, the drain electrode DE, the source electrode SE, the semiconductor layer SM, and the gate insulating layer 121 .

According to one embodiment of the present invention, as shown in FIGS. 1 and 4 , the first insulating layer 131 has at least one opening OP.

The opening OP has a region where the common line CL and the drain electrode DE partially overlap.

The opening OP has a common line contact hole 123 and a drain contact hole 143 to be described later. Accordingly, the total area on a plane occupied by the contact holes 123 and 143 is reduced, thereby improving the aperture ratio of the liquid crystal display.

The first insulating layer 131 may be made of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). In this case, the inorganic insulating material has photosensitivity and has a dielectric constant. ) of about 4.0 may be used. Alternatively, the first insulating layer 131 may have a double-layer structure of a lower inorganic layer and an upper organic layer so as not to damage the exposed portion of the semiconductor layer SM while having excellent insulating properties. The thickness of the first insulating layer 131 may be about 5000 Å or more, and may be about 6000 Å to about 8000 Å.

The organic layer 151 is positioned on the first insulating layer 131 .

According to an embodiment of the present invention, the organic layer 151 may be located in an area excluding the opening OP.

The organic layer 151 may have a single layer or multilayer structure including silicon oxide, silicon nitride, a photosensitive organic material, or a silicon-based low dielectric constant insulating material.

The organic layer 151 may be made of a negative type photosensitive composition in which an exposed portion remains and an unexposed portion is developed. Meanwhile, the organic layer 151 may be made of a positive type photosensitive composition. For example, the organic layer 151 may be made of a photosensitive organic material.

The common electrode CE is positioned on the organic layer 151 and the drain electrode DE.

According to an exemplary embodiment, the common electrode CE is electrically connected to the common line CL through the common line contact hole 123 .

Since an undercut occurs at the side of the common line contact hole 123 , the common electrode CE is discontinuous in an area overlapping the common line contact hole 123 . For example, as shown in FIG. 2 , the common electrode CE positioned on the common line contact hole 123 and the common electrode CE positioned on the drain electrode DE have discontinuous shapes. . Accordingly, the common electrode CE positioned on the common line contact hole 123 and the common electrode CE positioned on the drain electrode DE may be insulated.

The common electrode CE may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). In this case, ITO may be a polycrystalline or single crystal material, and IZO may also be a polycrystalline or single crystal material. Meanwhile, the common electrode CE may be made of a material used for the gate line GL or a material used for the data line DL.

The second insulating layer 141 is positioned on the common electrode CE, the drain electrode DE, and the organic layer 151 .

The second insulating layer 141 may be made of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). In this case, the inorganic insulating material has photosensitivity and has a dielectric constant. ) of about 4.0 may be used. Alternatively, the second insulating layer 141 may have a double-layer structure of a lower inorganic layer and an upper organic layer so as not to damage the exposed portion of the semiconductor layer SM while having excellent insulating properties. The thickness of the second insulating layer 141 may be about 5000 Å or more, and may be about 6000 Å to about 8000 Å.

According to an embodiment of the present invention, as shown in FIGS. 1 and 2 , the second insulating layer 141 has a drain contact hole 143 penetrating a portion thereof. A portion of the drain electrode DE is exposed through the drain contact hole 143, and the drain electrode DE contacts and is electrically connected to a pixel electrode PE, which will be described later.

The pixel electrode PE and the common electrode CL generate a horizontal electric field. The pixel electrode PE is positioned on the second insulating layer 141 . Specifically, the pixel electrode PE is positioned on the second insulating layer 141 corresponding to the pixel area of the lower substrate 101 .

Since an undercut occurs at the side of the common line contact hole 123 , the pixel electrode PE may be discontinuous in the common line contact hole 123 . For example, as shown in FIG. 2 , the pixel electrode PE disposed on the common line contact hole 123 and the pixel electrode PE disposed on the drain electrode DE may have discontinuous shapes. can

The pixel electrode PE may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). In this case, ITO may be a polycrystalline or single crystal material, and IZO may also be a polycrystalline or single crystal material.

Meanwhile, although not shown, a lower alignment layer may be positioned on the pixel electrode PE and the second insulating layer 141 . The lower alignment layer may be a vertical alignment layer or an alignment layer including a photoreactive material.

The lower alignment layer may be made of any one of polyamic acid, polysiloxane, and polyimide.

The upper panel includes an upper substrate 201 , a light blocking layer 251 and a color filter 252 .

The upper substrate 201 may be an insulating substrate made of transparent glass or plastic.

The light blocking layer 251 is positioned on the upper substrate 201 . The light blocking layer 251 according to an embodiment of the present invention is illustrated as being disposed on one surface of the upper substrate 201, but is not limited thereto, and the light blocking layer 251 may be disposed on the lower substrate 101. may be

The light blocking layer 251 blocks light from being emitted from areas other than the pixel area. That is, the light blocking layer 251 prevents light leakage in the non-pixel area. To this end, the light blocking layer 251 has an opening corresponding to the pixel area and covers all areas except for the pixel area. A pixel area is defined by the light blocking layer 251 .

A color filter 252 is positioned on the upper substrate 201 . Specifically, the color filter 252 is positioned on the upper substrate 201 corresponding to the pixel area of the lower substrate 101 . The color filter 252 may include a red color filter, a green color filter, and a blue color filter.

Meanwhile, although not shown, the upper panel may further include an upper alignment layer. An upper alignment layer is positioned on the upper substrate.

The upper alignment layer may be made of the same material as the aforementioned lower alignment layer.

When facing surfaces between the lower substrate 101 and the upper substrate 102 are defined as the upper surface of the corresponding substrate, respectively, and surfaces located opposite to the upper surfaces are defined as the lower surface of the corresponding substrate, respectively, the lower substrate 101 ), an upper polarizing plate may be further positioned on the lower surface of the upper substrate 201, and a lower polarizing plate may be further positioned on the lower surface of the upper substrate 201.

Since the transmission axis of the upper polarizer and the transmission axis of the lower polarizer are orthogonal to each other, one transmission axis and the gate line GL are arranged parallel to each other. Meanwhile, the display device may include only one of an upper polarizing plate and a lower polarizing plate.

The liquid crystal layer 300 may include a nematic liquid crystal material having positive dielectric constant anisotropy. The liquid crystal molecules of the liquid crystal layer 300 are arranged parallel to either one of the upper substrate 201 and the lower substrate 101 in the long axis direction, and the direction is from the rubbing direction of the alignment layer of the lower substrate 101 to the upper substrate. (201) may have a structure twisted 90 degrees in a spiral shape. Alternatively, instead of the nematic liquid crystal material, the liquid crystal layer 300 may include vertically aligned liquid crystal materials.

5 is a plan view schematically illustrating a liquid crystal display device according to another exemplary embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along line II-II′ of FIG. 5 .

Among the descriptions of the liquid crystal display according to another exemplary embodiment of the present invention, descriptions overlapping with those of the liquid crystal display according to the exemplary embodiment will be omitted.

Referring to FIGS. 5 and 6 , a liquid crystal display device according to an exemplary embodiment includes a lower panel and an upper panel facing each other and a liquid crystal layer positioned therebetween.

The lower panel includes a lower substrate 101, a gate line GL, a common line CL, a gate electrode GE, a gate insulating layer 121, a semiconductor layer SM, a data line DL, and a drain electrode DE. ), source electrode SE, first insulating layer 131, organic film 151, common electrode CE, second insulating layer 141, pixel electrode PE, upper substrate 201, light blocking layer 251 , a color filter 252 and a liquid crystal layer 300 .

According to another embodiment of the present invention, as shown in FIG. 6, the common electrode CE overlaps the second insulating layer 141, and although not shown, the common electrode CE is the second insulating layer 141. may have an area smaller than (141). Accordingly, the common electrode CE does not come into contact with the pixel electrode PE, so that a short circuit does not occur.

According to another embodiment of the present invention, as shown in FIG. 6 , the common electrode CE and the second insulating layer 141 are positioned on the common line contact hole 123 . Also, since an undercut occurs at the side of the common line contact hole 123 , the common electrode CE is discontinuous in an area overlapping the common line contact hole 123 . For example, as shown in FIG. 6 , the common electrode CE positioned on the common line contact hole 123 and the common electrode CE positioned on the drain electrode DE have discontinuous shapes. . Accordingly, the common electrode CE positioned on the common line contact hole 123 and the common electrode CE positioned on the drain electrode DE may be insulated.

The upper panel includes an upper substrate 201 , a light blocking layer 251 and a color filter 252 .

7A to 7J are process cross-sectional views of the liquid crystal display of FIG. 1 .

First, a gate metal layer is deposited on the entire surface of the lower substrate 701 . The gate metal layer may be deposited using a physical vapor deposition (PVD) method such as sputtering.

Then, as shown in FIGS. 1 and 7A , the gate line GL, the gate electrode GE, and the common line CL are patterned by a photolithography process and an etching process.

According to the manufacturing method of an embodiment of the present invention, the common line CL is simultaneously formed using the gate line GL and the gate electrode GE using one mask. Accordingly, since a separate process for forming the common line CL is not required, the manufacturing process according to the present invention is simplified and manufacturing cost can be reduced.

As shown in FIG. 7B , the gate insulating layer 721 may be deposited on the entire surface of the lower substrate 701 including the gate metal layer by chemical vapor deposition.

The gate insulating layer 721 may be made of a material used for manufacturing the gate insulating layer 121 described above.

A semiconductor material is formed on the gate insulating layer 721 . The semiconductor material may be deposited using a chemical vapor deposition (CVD) method. The semiconductor material 721 may be made of a material used for manufacturing the above-described semiconductor layer SM.

Then, although not shown, the above-described semiconductor material is patterned by a photolithography process and an etching process.

The semiconductor material 721_ may be removed by a dry-etch method using an etching gas.

Subsequently, a data wiring metal layer is deposited on the entire surface of the lower substrate 701 . The data wire metal layer may be deposited using a physical vapor deposition (PVD) method such as sputtering.

Then, as shown in FIGS. 1 and 7C , the above-described data line DL, source electrode SE, and data electrode DE are patterned by a photolithography process and an etching process.

The data metal layer may be removed by a wet-etch method using an etchant.

Next, as shown in FIG. 7D , a first insulating layer 731 is formed on the lower substrate 701, the semiconductor layer SM, the data line DL, the source electrode SE, and the data electrode DE. deposited The first insulating layer 731 is deposited on the entire surface of the lower substrate 701 including the semiconductor layer SM, the data line DL, the source electrode SE, and the data electrode DE.

The first insulating layer 731 may be deposited by chemical vapor deposition.

The first insulating layer 731 may be made of a material used for manufacturing the first insulating layer 131 described above.

Subsequently, a photosensitive organic material is formed on the entire surface of the lower substrate 701 including the first insulating layer 731 .

Thereafter, as shown in FIG. 7E , the photosensitive organic material is patterned through a photolithography process, so that an organic layer 751 is formed in an area excluding the opening OP.

Next, as shown in FIG. 7F , the gate insulating layer 721 is selectively removed by an etching process to form a common line contact hole 723 exposing the common line CL. In addition, at the same time, the first insulating layer 731 is selectively removed by an etching process, thereby forming an opening OP.

In this case, the common line CL and the drain electrode DE are positioned on different layers and do not contact each other, so that a short circuit does not occur. Accordingly, the aperture ratio of the liquid crystal display device may be improved by overlapping the common line CL and the drain electrode DE on a plane.

The common line contact hole 723 may be formed to extend along a portion of an edge of the opening OP. For example, the common line contact hole 723 may be formed in a C shape along a portion of an edge of the opening OP on a plane.

According to an exemplary embodiment, the opening OP is formed in a region where the common line CL and the drain electrode DE overlap at least partially.

According to an exemplary embodiment, the common line contact hole 723 is formed to be spaced apart from the gate electrode GE and the gate line GL. Accordingly, the gate electrode GE and the gate line GL are insulated from the common line CL to prevent a short circuit.

A common line contact hole 723 and a drain contact hole 743 to be described later are located in the opening OP. Accordingly, the area occupied by the contact holes 723 and 743 on a plane is reduced, thereby improving the aperture ratio of the liquid crystal display.

The gate insulating layer 721 and the first insulating layer 731 may be removed by dry-etching using an etching gas.

Subsequently, as shown in FIG. 7G, an ashing process is performed. At this time, the ashing process is performed until the exposed lower surface of the organic layer 751 is removed. That is, when the exposed lower surface of the organic layer 751 is removed, the ashing process ends.

Thereafter, a transparent conductive material is deposited on the entire surface of the lower substrate 701 including the organic layer 751, the data line DL, the source electrode SE, and the drain electrode DE.

The transparent conductive material may be made of a material used in manufacturing the above-described common electrode CE.

Since an undercut occurs on the side of the common line contact hole 723 , the transparent conductive material is discontinuously formed in an area overlapping the common line contact hole 723 . For example, a transparent conductive material positioned on the common line contact hole 723 and a transparent conductive material positioned on the drain electrode DE have discontinuous shapes. Accordingly, the transparent conductive material positioned on the common line contact hole 723 and the transparent conductive material positioned on the drain electrode DE may be insulated from each other.

Next, as shown in FIG. 7H , the transparent metal layer is patterned by a photolithography process and an etching process, so that the common electrode CE connected to the common line CL through the common line contact hole 723 is a pixel. formed in the area.

Then, a second insulating layer (whole surface) of the lower substrate 701 including the data line DL, the source electrode SE, the drain electrode DE, the organic layer 751, and the common electrode CE is formed. 741) is deposited.

The second insulating layer 741 may be deposited by chemical vapor deposition.

The second insulating layer 741 may be made of the same material as the material used for manufacturing the first insulating layer 131 described above.

Thereafter, as shown in FIG. 7I , the second insulating layer 741 is selectively removed through a photolithography process and an etching process, thereby forming a drain contact hole 743 exposing the drain electrode DE.

Next, a transparent metal layer is deposited on the entire surface of the lower substrate 701 including the organic layer 751 , the drain electrode DE, and the second insulating layer 741 .

The transparent metal layer may be made of a material used in manufacturing the aforementioned pixel electrode PE.

Next, as shown in FIG. 7J , the transparent metal layer is patterned through a photolithography process and an etching process, so that the pixel electrode PE connected to the drain electrode DE through the drain contact hole 743 is formed in the pixel area. is formed in

8A to 8J are process cross-sectional views of the liquid crystal display of FIG. 5 .

First, a gate metal layer is deposited on the entire surface of the lower substrate 801 . The gate metal layer may be deposited using a physical vapor deposition (PVD) method such as sputtering.

Then, as shown in FIGS. 5 and 8A , the gate line GL, the gate electrode GE, and the common line CL are patterned by a photolithography process and an etching process.

According to the manufacturing method of another embodiment of the present invention, the common line CL is simultaneously formed using a single mask along with the gate line GL and the gate electrode GE. Accordingly, since a separate process for forming the common line CL is not required, the manufacturing process according to the present invention is simplified and manufacturing cost can be reduced.

As shown in FIG. 8B , the gate insulating layer 821 may be deposited on the entire surface of the lower substrate 801 including the gate metal layer by chemical vapor deposition.

The gate insulating layer 821 may be made of a material used for manufacturing the gate insulating layer 121 described above.

Then, although not shown, a semiconductor material is formed on the gate insulating layer 821 . The semiconductor material may be deposited using a chemical vapor deposition (CVD) method. The semiconductor material may be made of a material used in manufacturing the above-described semiconductor layer SM.

Although not shown, the semiconductor material described above is patterned by a photolithography process and an etching process.

The semiconductor material may be removed by a dry-etch method using an etching gas.

Subsequently, a data wiring metal layer is deposited on the entire surface of the lower substrate 801 . The data wire metal layer may be deposited using a physical vapor deposition (PVD) method such as sputtering.

Then, as shown in FIGS. 5 and 8C , the above-described data line DL, source electrode SE, and data electrode DE are patterned by a photolithography process and an etching process.

The data metal layer may be removed by a wet-etch method using an etchant.

Next, as shown in FIG. 8D, a first insulating layer 831 is formed on the lower substrate 801, the semiconductor layer SM, the data line DL, the source electrode SE, and the data electrode DE. deposited The first insulating layer 831 is deposited on the entire surface of the lower substrate 801 including the semiconductor layer SM, the data line DL, the source electrode SE, and the data electrode DE.

The first insulating layer 831 may be deposited by chemical vapor deposition.

The first insulating layer 831 may be made of a material used for manufacturing the first insulating layer 131 described above.

Subsequently, a photosensitive organic material is formed on the entire surface of the lower substrate 801 including the first insulating layer 831 .

Thereafter, as shown in FIG. 8E , the photosensitive organic material is patterned through a photolithography process, so that an organic layer 851 is formed in an area excluding the opening OP.

Next, as shown in FIG. 8F , the gate insulating layer 821 is selectively removed by an etching process to form a common line contact hole 823 exposing the common line CL. In addition, at the same time, the first insulating layer 831 is selectively removed by an etching process, thereby forming an opening OP.

The common line CL and the drain electrode DE are positioned on different layers and do not contact each other, so that a short circuit does not occur. Accordingly, the aperture ratio of the liquid crystal display device may be improved by overlapping the common line CL and the drain electrode DE on a plane.

The common line contact hole 823 may be formed to extend along an edge of the opening OP. For example, the common line contact hole 823 may be formed in a C shape along a portion of an edge of the opening OP on a plane.

According to an exemplary embodiment, the common line contact hole 823 is formed to be spaced apart from the gate electrode GE and the gate line GL. Accordingly, the gate electrode GE and the gate line GL are insulated from the common line CL to prevent a short circuit.

According to an exemplary embodiment, the opening OP is formed in a region where the common line CL and the drain electrode DE overlap at least partially.

A common line contact hole 823 and a drain contact hole 843 to be described later are located in the opening OP. Accordingly, the area on a plane occupied by the contact holes 823 and 843 is reduced, thereby improving the aperture ratio of the liquid crystal display.

The gate insulating layer 821 and the first insulating layer 831 may be removed by dry-etching using an etching gas.

Subsequently, as shown in FIG. 8G, an ashing process is performed. At this time, the ashing process is performed until the exposed lower surface of the organic layer 851 is removed. That is, when the exposed lower surface of the organic layer 851 is removed, the ashing process ends.

8H, a transparent metal layer is formed on the entire surface of the lower substrate 801 including the organic layer 851, the data line DL, the source electrode SE, and the drain electrode DE. deposited

The transparent metal layer may be made of a material used in manufacturing the above-described common electrode CE.

Since an undercut occurs on the side of the common line contact hole 823 , the transparent conductive material is discontinuously formed in an area overlapping the common line contact hole 823 . For example, a transparent conductive material positioned on the common line contact hole 823 and a transparent conductive material positioned on the drain electrode DE have discontinuous shapes. Accordingly, the transparent conductive material positioned on the common line contact hole 823 and the transparent conductive material positioned on the drain electrode DE may be insulated from each other.

Next, as shown in FIG. 8I , the entire surface of the lower substrate 801 including the data line DL, the source electrode SE, the drain electrode DE, the organic layer 851, and the common electrode CE. A second insulating layer 841 is deposited on the entire surface.

The second insulating layer 841 may be deposited by chemical vapor deposition.

The second insulating layer 841 may be made of the same material as the material used for manufacturing the first insulating layer 131 described above.

Thereafter, the second insulating layer 841 and the common electrode CE are selectively removed at the same time by a photolithography process and an etching process, thereby forming a drain contact hole exposing the drain electrode DE, although not shown.

The second insulating layer 841 may be removed by a dry-etch method using an etching gas. The common electrode CE may be removed by a wet-etch method using an etchant.

The common electrode CE and the second insulating layer 841 are simultaneously patterned using one mask. Accordingly, since a separate process for patterning the common electrode CE is not required, the manufacturing process according to the present invention is simplified and manufacturing cost can be reduced.

In this case, the common electrode CE may be over etched and may have a smaller area than the second insulating layer 841 . Accordingly, although not shown, the common electrode CE does not contact the pixel electrode PE, so that a short circuit does not occur.

Next, a transparent metal layer is deposited on the entire surface of the lower substrate 701 including the organic layer 851 , the drain electrode DE, and the second insulating layer 841 .

The transparent metal layer may be made of a material used in manufacturing the aforementioned pixel electrode PE.

Next, as shown in FIG. 8J , the transparent metal layer is patterned through a photolithography process and an etching process, so that the pixel electrode PE connected to the drain electrode DE through the drain contact hole 843 is formed in the pixel area. is formed in

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which the present invention belongs that various substitutions, modifications, and changes are possible within a range that does not deviate from the technical spirit of the present invention. It will be clear to those who have knowledge of

Lower board: 101
Top board: 201
Liquid crystal layer: 300
Gate insulation layer: 121
1st insulating layer: 131
Second insulating layer: 141
Common line contact hole: 123
Opening: OP
Drain contact hole: 143

Claims (14)

a lower substrate and an upper substrate comprising a display area and a non-display area and spaced apart from each other;
a liquid crystal layer between the lower and upper substrates;
a first insulating layer positioned in the non-display area of the lower substrate and defining an opening;
a common line located in the opening;
a gate insulating layer positioned in the opening and having a common line contact hole exposing a portion of the common line;
a common electrode disposed on the gate insulating layer and contacted and electrically connected to a common line through the common line contact hole; Including,
The common line contact hole extends along a portion of an edge of the opening. According to claim 1,
a drain electrode positioned on the gate insulating layer;
a second insulating layer positioned on the drain electrode and having a drain contact hole;
a pixel electrode electrically connected to the drain electrode through the drain contact hole; A liquid crystal display device further comprising a. According to claim 2,
The liquid crystal display device at least partially overlaps the common line and the drain electrode in the opening. delete 4. The liquid crystal display of claim 3, wherein the common electrode is discontinuous in an area overlapping the common line contact hole. The liquid crystal display device of claim 3 , wherein the common electrode has a smaller area than the second insulating layer. forming a gate line, a gate electrode and a common line on a lower substrate;
forming a gate insulating layer on the gate line, the gate electrode and the common line;
forming a semiconductor material on the gate insulating layer;
forming a source electrode and a drain electrode on the semiconductor material;
forming a first insulating layer on the source electrode and the drain electrode;
forming an organic film on the first insulating layer;
forming an opening in the first insulating layer and a common line contact hole in the gate insulating layer;
forming a common electrode connected to the common line through the common line contact hole;
forming a second insulating layer on the common electrode;
forming a pixel electrode connected to the drain electrode through a drain contact hole;
The opening has a region where the common line and the drain electrode at least partially overlap,
The common line contact hole and the drain contact hole are formed in an opening,
The common line contact hole extends along a portion of an edge of the opening. delete 8. The method of claim 7, wherein forming a common electrode connected to the common line through the common line contact hole comprises:
coating a transparent conductive material on the organic layer and on the entire surface of the lower substrate including the organic layer;
coating a photosensitive composition on the transparent conductive material;
an exposure step of disposing a mask on the photosensitive composition and irradiating light;
developing the exposed photosensitive composition;
etching the transparent conductive material using the developed photosensitive composition;
A method of manufacturing a liquid crystal display device comprising ashing the photosensitive composition. The method of claim 7, wherein forming the second insulating layer on the common electrode comprises:
coating a material for forming a second insulating layer on the entire surface of the lower substrate including the common electrode;
coating a photosensitive composition on the material for forming the second insulating layer;
an exposure step of disposing a mask on the photosensitive composition and irradiating light;
developing the exposed photosensitive composition;
etching the material for forming the second insulating layer using the developed photosensitive composition;
A method of manufacturing a liquid crystal display device comprising ashing the photosensitive composition. 8. The method of claim 7, wherein forming a common electrode connected to the common line through the common line contact hole comprises:
and coating a transparent conductive material on the entire surface of the lower substrate including the organic layer. 12. The method of claim 11, wherein forming the second insulating layer on the common electrode comprises:
and applying a material for forming a second insulating layer to the entire surface of the lower substrate including the transparent conductive material. 13. The method of claim 12, further comprising forming a drain contact hole in the second insulating layer. 14. The method of claim 13, wherein forming the drain contact hole in the second insulating layer comprises:
coating a photosensitive composition on the material for forming the second insulating layer;
an exposure step of disposing a mask on the photosensitive composition and irradiating light;
developing the exposed photosensitive composition;
etching the material for forming the second insulating layer using the developed photosensitive composition;
etching the transparent conductive material using the developed photosensitive composition;
A method of manufacturing a liquid crystal display device comprising ashing the photosensitive composition.

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