KR101799032B1 - Array substrate for liquid crystal display and Method for fabricating the same - Google Patents

Abstract

The present invention relates to an array substrate of a liquid crystal display device including a connection pattern connecting a source electrode and an active layer, and a pixel electrode connecting a drain electrode and an active layer, and a method of manufacturing the same, wherein the array substrate of the liquid crystal display device is formed A gate wiring which is used as a gate electrode and which defines a pixel region in the form of a matrix perpendicular to the data wiring; An active layer formed over the data line and formed in the pixel region, the data line adjacent to the active layer and used as a source electrode, a drain electrode adjacent to the active layer and formed in the pixel region, A thin film transistor including the gate wiring superimposed on the active layer and used as a gate electrode, a connection pattern connecting the active layer and the data line, and a connection part connecting the active layer and the drain electrode; A pixel electrode including the connection portion; And a common electrode which generates a vertical electric field with the pixel electrode and is formed in the pixel region.

Description

[0001] The present invention relates to an array substrate for a liquid crystal display device,

The present invention relates to an array substrate of a liquid crystal display device including a connection pattern connecting a source electrode and an active layer, and a pixel electrode connecting a drain electrode and an active layer, and a method of manufacturing the same.

In general, a liquid crystal display device is driven by using optical anisotropy and polarization properties of a liquid crystal. Liquid crystals are narrow and long in structure, so they have a directionality in the arrangement of molecules and can control the direction of the molecular arrangement by artificially applying an electric field to the liquid crystal. Therefore, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal by optical anisotropy, so that image information can be expressed.

Currently, an active matrix liquid crystal display (AM-LCD: hereinafter referred to as liquid crystal display) in which pixel electrodes connected to a thin film transistor and a thin film transistor are arranged in a matrix manner has excellent resolution and video realization capability, .

The liquid crystal display device includes a color filter substrate on which a common electrode is formed, an array substrate on which pixel electrodes are formed, and a liquid crystal interposed between the two substrates. In such a liquid crystal display device, And the characteristics such as the transmittance and the aperture ratio are excellent. Since the liquid crystal driving by the vertical electric field has a disadvantage that the viewing angle characteristic is not excellent, a transverse electric field type liquid crystal display device having a superior viewing angle characteristic has been proposed to overcome the disadvantage of the viewing angle. However, the transverse electric-field-type liquid crystal display device has the advantage of improving the viewing angle, but has a disadvantage in that the aperture ratio and transmittance are low. A fringe field switching mode liquid crystal display (LCD) has been developed which is characterized in that a liquid crystal is operated by a fringe field in order to realize a disadvantage of such a lateral electric field type liquid crystal display device.

The array substrate of the conventional liquid crystal display device will be described in detail with reference to the drawings.

1 is a cross-sectional view of an array substrate for a liquid crystal display according to the prior art. 1 shows an array substrate of a fringe field switching mode liquid crystal display device in which liquid crystal is driven by a vertical electric field generated between a pixel electrode and a common electrode.

1, an array substrate 10 of a liquid crystal display device according to the related art includes a gate electrode 12 formed on an active layer 24 via an active layer 24, a gate insulating layer 46, The pixel electrode 18 connected to the source and drain electrodes 26a and 26b and the drain electrode 26b connected to the pixel electrode 18 and the common electrode 20 for generating an electric field for driving the liquid crystal together with the pixel electrode 18, .

The array substrate 10 is formed in the following process order.

Forming an active layer 24 using a first mask on the substrate 40, forming a gate insulating layer 46 on the substrate 40 including the active layer 24, forming a gate insulating layer 46 Forming a first interlayer insulating layer 42 formed on the gate insulating layer 46 including the gate electrode 12, forming a second interlayer insulating layer 42 on the gate insulating layer 46, Forming source and drain contact holes 50a and 50b exposing the active layer 24 located on both sides of the gate electrode 12 by selectively etching the first interlayer insulating layer 42 using the third mask, A step of forming source and drain electrodes 26a and 26b connected to the active layer 24 using a fourth mask and a step of forming a protective layer on the first interlayer insulating layer 42 including the source and drain electrodes 26a and 26b And the step of forming the layer 52 are sequentially performed.

A step of forming a first connection contact hole 68a for exposing the drain electrode 26b by selective etching of the protection layer 52 using the fifth mask; A step of forming a second interlayer insulating layer 66 on the protective layer 52 including the connection pattern 64 and the common electrode 20, , And a second connection contact hole (68b) exposing the connection pattern (64) by selective etching of the second interlayer insulating layer (66) and the protection layer (52) using the seventh mask, And forming a pixel electrode 18 connected to the connection pattern 64 through the second connection contact hole 68b using a mask.

The array substrate 10 of the conventional liquid crystal display device has the source and drain electrodes 26a and 26b and the connection pattern 64 connecting the drain electrode 26a and the pixel electrode 18, 20, and the pixel electrode 18 are sequentially laminated to form an insulating layer for insulating each constituent element, a step of forming a contact hole for connecting the constituent elements, and a step of patterning the constituent elements The number of mask processes used increases. Therefore, there is a problem that the manufacturing time of the liquid crystal display device becomes long and the manufacturing cost rises.

In order to solve the above problems, the present invention is characterized in that a source electrode and an active layer are connected in a connection pattern, and first to fourth contact holes for connecting the drain electrode and the active layer to the pixel electrode are simultaneously formed, And an object of the present invention is to provide an array substrate of a liquid crystal display device and a method of manufacturing the same.

Another object of the present invention is to provide an array substrate of a liquid crystal display device and a method of manufacturing the same that can maximize the aperture ratio by superimposing a connection pattern connecting a source electrode and an active layer with data lines.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: forming a data line and a drain electrode to be used as a source electrode on a substrate including a pixel region; Forming an interlayer insulating layer on the substrate including the data line and the drain electrode, and forming an active layer on the data line and the interlayer insulating layer corresponding to the pixel region; Forming a gate insulating layer on the interlayer insulating layer including the active layer, forming a gate electrode on the gate insulating layer, the gate electrode being perpendicular to the data line and used as a gate electrode; Forming a protective layer on the gate insulating layer including the gate wiring and the common electrode; selectively etching the interlayer insulating layer, the gate insulating layer, and the protective layer to form the data line, the active layer, Forming a plurality of contact holes to expose a plurality of contact holes; And forming a connection pattern connecting the source electrode and the active layer through the plurality of contact holes and a pixel electrode connecting the drain electrode and the active layer and generating a vertical electric field with the common electrode, A method of manufacturing an array substrate for a display device is provided.

And the drain electrode is formed in an isolated pattern. The present invention also provides a method of manufacturing an array substrate for a liquid crystal display device.

Wherein the active layer includes a first active layer overlapping the data line and the gate line, and a second active layer formed in the pixel region.

A first contact hole through which the data line used as the source electrode is exposed, a second contact hole through which the first active layer is exposed by selective etching of the interlayer insulating layer, the gate insulating layer, and the protective layer, A third contact hole through which the active layer is exposed, and a fourth contact hole through which the drain electrode is exposed, are formed at the same time.

The connection pattern connects the data line and the first active layer through the first and second contact holes and the pixel electrode connects the second active layer and the drain electrode through the third and fourth contact holes The present invention also provides a method of manufacturing an array substrate for a liquid crystal display device.

And the common electrode has a first opening corresponding to the first and second contact holes and a second opening corresponding to the third and fourth contact holes.

And one of the pixel electrode and the common electrode has a plurality of openings.

Wherein forming the gate electrode and the common electrode comprises: forming a lower and an upper metal material layer on the gate insulating layer; Forming a photosensitive layer on the upper metal material layer; Forming a first photosensitive layer pattern having a first thickness on the gate electrode by exposure and development of the photosensitive layer to which a halftone mask is applied and a second photosensitive layer pattern having a second thickness thinner than the first thickness step; And patterning the lower and upper metal material layers using the first and second photosensitive layer patterns as an etching mask. The present invention also provides a method of manufacturing an array substrate for a liquid crystal display.

According to an aspect of the present invention, there is provided a liquid crystal display comprising: a data line formed on a substrate and used as a source electrode; a gate line crossing the data line perpendicularly to define a pixel region in the form of a matrix and used as a gate electrode; An active layer formed over the data line and formed in the pixel region, the data line adjacent to the active layer and used as a source electrode, a drain electrode adjacent to the active layer and formed in the pixel region, A thin film transistor including the gate wiring superimposed on the active layer and used as a gate electrode, a connection pattern connecting the active layer and the data line, and a connection part connecting the active layer and the drain electrode; A pixel electrode including the connection portion; And a common electrode which generates a vertical electric field with the pixel electrode and is formed in the pixel region.

And the drain electrode is formed in an isolated pattern.

The active layer includes a first active layer overlapping the data line and the gate line, and a second active layer formed in the pixel region.

An active layer is formed on the interlayer insulating layer, a gate insulating layer is formed on the interlayer insulating layer including the active layer, the gate insulating layer is formed on the interlayer insulating layer, Wherein the gate wiring and the common electrode are formed on the gate insulating layer and the common electrode, and a protective layer is formed on the gate insulating layer including the gate wiring and the common electrode, and the interlayer insulating layer, the gate insulating layer, A first contact hole exposing the data line used as a source electrode, a second contact hole exposing the first active layer, a third contact hole exposing the second active layer, and a fourth contact hole exposing the drain electrode. Is provided on the substrate.

Wherein the connection pattern connects the data line and the first active layer through the first and second contact holes and the connection portion of the pixel electrode is electrically connected to the second active layer and the drain electrode through the third and fourth contact holes, An array substrate of a liquid crystal display device for connecting electrodes is provided.

The common electrode has a first opening corresponding to the first connection pattern and a second opening corresponding to the second connection pattern.

And one of the pixel electrode and the common electrode has a plurality of openings.

The present invention can simultaneously form the first through fourth contact holes for connecting the source electrode and the active layer in the connection pattern and connecting the drain electrode and the active layer to the pixel electrode by using one mask, And the manufacturing cost can be reduced.

In the present invention, a gate electrode is used as a gate wiring, a source electrode is used as a data wiring, a part of the active layer is overlapped with the data wiring, and a contact hole for connecting the source electrode and the active layer is formed over the data wiring, The area of the electrode can be maximized and the aperture ratio can be improved.

1 is a cross-sectional view of an array substrate for a liquid crystal display according to the related art
2 is a plan view of an array substrate for a liquid crystal display according to a first embodiment of the present invention
3 is a cross-sectional view of the array substrate for a liquid crystal display according to the first embodiment of the present invention
4A to 4F are cross-sectional views showing steps of a method of manufacturing an array substrate for a liquid crystal display according to a first embodiment of the present invention
FIGS. 5A to 5F are cross-sectional views showing steps of a method of manufacturing an array substrate for a liquid crystal display according to a second embodiment of the present invention

Hereinafter, various embodiments of the present invention will be described in detail with reference to the drawings.

1st Example

2 is a plan view of an array substrate for a liquid crystal display according to a first embodiment of the present invention. 2 is a plan view of an array substrate of a fringe field switching mode liquid crystal display device in which liquid crystal is driven by a vertical electric field generated between a pixel electrode and a common electrode.

2, the array substrate 110 of the liquid crystal display according to the first embodiment of the present invention includes a plurality of gate wirings 112, a plurality of data wirings 114, a plurality of gate wirings 112, A plurality of pixel regions PA defined by the intersections of the wirings 114 and a plurality of thin film transistors PA1, PA1, PA2, A plurality of pixel electrodes 118 located in each of the plurality of pixel regions PA and connected to each of the plurality of thin film transistors 116 and a plurality of pixel electrodes 118 to generate a vertical electric field, And a plurality of common electrodes 120 which are formed on the substrate.

The thin film transistor 116 includes a gate wiring 112 used as a gate electrode, a gate insulating layer (not shown), an active layer 124, a data wiring 114 used as a source electrode, and a drain electrode 126 . The active layer 124 includes a first active layer 124a overlapping the data line 114 and the gate line 112 and a second active layer 124b extending from the first active layer 124a to the pixel area PA . The second active layer 124b extends perpendicularly to the first active layer 124a at the end of the first active layer 124a and is arranged in parallel with the gate wiring 112. [

A gate wiring 112 overlapping the first active layer 124a is used as a gate electrode of the thin film transistor 116. [ 2, a part of the gate wiring 112 overlapping with the active layer 124 is used as the gate electrode, but a protrusion pattern (not shown) is extended from the gate wiring 112 It can be used as a gate electrode. In other words, it is possible to operate in the dual gate mode in which the gate electrode is used for both the gate wiring 112 and the protruding pattern which is branched at the gate wiring 112.

The data line 114 used as the source electrode is connected to the first active layer 124a by the connection pattern 130 through the first and second contact holes CNT1 and CNT2. The drain electrode 126 is formed simultaneously with the data line 114 and is provided in the form of an isolated pattern in the pixel region PA. The second active layer 124b and the drain electrode 126 are connected by the pixel electrode 118 through the third and fourth contact holes CNT3 and CNT4. The pixel electrode 118 includes a connection portion for connecting the second active layer 124b and the drain electrode 126 through the third and fourth contact holes CNT3 and CNT4.

The pixel electrode 118 connected to the drain electrode 126 and formed in the pixel region PA is formed in a plate shape having a plurality of openings 118a. The common electrode 120 is arranged so as to pass through a plurality of pixel regions PA arranged between the two gate wirings 112 in parallel with the gate wirings 112. The plurality of common electrodes 120 are all connected at the periphery of the array substrate 110, and the same voltage is applied.

The first opening 120a and the third and fourth contact holes CNT3 and CNT4 in which the first and second contact holes CNT1 and CNT2 are positioned are formed in the common electrode 120 corresponding to one pixel region PA. The second opening 120b is formed. The common electrode 120 is formed over the entire pixel area PA except for the first and second openings 120a and 120b. Accordingly, the same voltage is applied to the common electrode 120 corresponding to each of the plurality of pixel regions PA, and the fringe generated between the common electrode 120 and the pixel electrode 118 corresponding to the plurality of openings 118a The liquid crystal can be driven by a field (fringe field).

The pixel electrode 118 is formed over the entire pixel area PA without forming the plurality of openings 118a in the pixel electrode 118 and a plurality of pixel electrodes 118 are formed in the common electrode 120 corresponding to the pixel area PA. The opening 118a can be formed. In other words, if the plurality of openings 118a are formed in either the common electrode 120 or the pixel electrode 118, the liquid crystal can be driven by the fringe field. The pixel electrode 118 is partially overlapped with the gate line 112 passing through the adjacent lower pixel region PA to form a storage capacitor Cst. In other words, a protective layer (not shown) of an insulating material interposed between the gate wiring 112 and the pixel electrode 118 at the bottom and the gate wiring 112 and the pixel electrode 118, respectively, And constitutes a dielectric layer with the second electrode.

Although not shown in the figure, the array substrate 110 includes a plurality of gate pad portions connected to the ends of the plurality of gate wirings 112 and receiving scan signals from the outside, and a plurality of gate wirings And a plurality of data pad units connected to the data bus and receiving image signals from the outside.

3 is a cross-sectional view of an array substrate for a liquid crystal display according to the first embodiment of the present invention. FIG. 3 shows a cross-sectional view of the array substrate 110 of FIG. 2 taken along line I-I '. For convenience of explanation, the insulating substrate 140 is divided into a pixel region PA and a data line DA.

The data line 114 and the drain electrode 126 are simultaneously formed on the insulating substrate 140 corresponding to the data wiring region DA and the pixel region PA. The data lines 114 are arranged in the first direction and the drain electrodes 126 located in the pixel area PA are formed in an isolated pattern. The data line 114 and the drain electrode 126 may be formed of a single layer, a double layer, or a single layer using a conductive metal such as copper (Cu), molybdenum (Mo), aluminum (Al), aluminum alloy (AlNd), and chromium It can be formed as a triple layer.

The interlayer insulating layer 142 is formed on the insulating substrate 140 including the data line 114 and the drain electrode 126 and the active layer 124 is formed on the interlayer insulating layer 142. [ The active layer 124 is composed of a first active layer 124a overlapping the data line 114 and the gate line 112 of FIG. 2 and a second active layer 124b formed on the pixel area PA. The interlayer insulating layer 142 is formed using an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx). The active layer 124 is composed of a first amorphous silicon layer (not shown) not doped with an impurity and a second amorphous silicon layer (not shown) doped with an N-type impurity, and the gate wiring 112 ), That is, the second amorphous silicon layer in the channel region.

A gate insulating layer 146 is formed on the interlayer insulating layer 142 including the active layer 124 and the gate wiring 112 and the common electrode 120 are formed on the gate insulating layer 146. The gate wirings 112 are arranged in a second direction perpendicular to the data wirings 112. The gate insulating layer 146 is formed using an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx). The gate wiring 112 may include a second lower metal material layer pattern 144a made of a transparent conductive material such as ITO (indium tin oxide) and IZO (indium zinc oxide), and a second lower metal material layer pattern 144b made of copper (Cu), molybdenum And a second upper metal material layer pattern 144b made of a conductive metal material such as aluminum alloy (AlNd) and chromium (Cr). The common electrode 120 is made of ITO (indium tin oxide) and IZO and a second lower metal material layer pattern 144a made of a transparent conductive material such as oxide.

In the first embodiment of the present invention, a portion of the gate wiring 112 overlapped with the active layer 124 is used as the gate electrode, but a protruding pattern extending from the gate wiring 112 can be used as the gate electrode. The common electrode 120 is arranged so as to pass through a plurality of pixel regions PA arranged between the two gate wirings 112 in parallel with the gate wirings 112. The plurality of common electrodes 120 are connected to each other at the periphery of the array substrate 110, and the same voltage is applied to the plurality of common electrodes 120.

A protective layer 150 is formed on the gate insulating layer 146 including the gate wiring 112 and the common electrode 120 and the interlayer insulating layer 142, the gate insulating layer 146, And selectively etched to form the first to fourth contact holes CNT1, CNT2, CNT3, and CNT4. The passivation layer 150 may be formed of an inorganic insulating material including silicon oxide (SiO2) and silicon nitride (SiNx), or an organic insulating material including photoacrylic and benzocyclobutene.

The first contact hole CNT1 exposes the data line 114 used as a source electrode by selectively etching the interlayer insulating layer 142, the gate insulating layer 146 and the protective layer 150, The second contact hole CNT2 exposes the second active layer 124b by selective etching of the gate insulating layer 146 and the protective layer 150 and the third contact hole CNT3 exposes the gate insulating layer 146 and the protective layer 150 The fourth contact hole CNT4 is formed by selectively etching the interlayer insulating layer 142, the gate insulating layer 146 and the passivation layer 150 to expose the first active layer 124a, (Not shown).

The data line 114 used as the source electrode is connected to the first active layer 124a by the connection pattern 130 through the first and second contact holes CNT1 and CNT2. The second active layer 124b and the drain electrode 126 are connected by the pixel electrode 118 through the third and fourth contact holes CNT3 and CNT4. The pixel electrode 118 connected to the drain electrode 126 and formed in the pixel region PA is formed in a plate shape having a plurality of openings 118a. The pixel electrode 118 includes a connection portion for connecting the second active layer 124b and the drain electrode 126 through the third and fourth contact holes CNT3 and CNT4. The pixel electrode 118 and the connection pattern 130 are formed of a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO).

4A to 4F are process cross-sectional views showing steps of a method of manufacturing an array substrate for a liquid crystal display according to the first embodiment of the present invention. FIGS. 4A to 4F show a step-by-step method of manufacturing the array substrate 110 by cutting the array substrate 110 of FIG. 2 into I-I '. For convenience of explanation, the insulating substrate 140 is divided into a pixel region PA and a data line DA.

4A, a first metal material layer (not shown) is formed on an insulating substrate 140, and a first metal material layer is patterned to form a drain wiring 114 and a drain electrode 126. Next, as shown in FIG. The data line 114 is a line pattern extending in the first direction and the drain electrode 126 is an isolated pattern formed in the pixel area PA. A buffer layer may be formed on the insulating substrate 140 before forming the first metal material layer. The buffer layer serves to prevent the impurities from eluting from the insulating substrate 140.

The first metal material layer may be formed of a single layer, a double layer, or a triple layer using a conductive metal such as copper (Cu), molybdenum (Mo), aluminum (Al), aluminum alloy (AlNd) have. Although not shown in the drawing, when the first metal material layer is formed as a double layer, a first lower metal material layer made of molybdenum (Mo) or titanium (Ti) or an alloy thereof and a second lower metal material layer made of copper Cu). ≪ / RTI > When the first metal material layer is formed as a triple layer, a first lower metal material layer made of molybdenum (Mo) or titanium (Ti) or an alloy thereof and a second lower metal material layer made of copper (Cu) And a first upper metal material layer made of molybdenum (Mo) or titanium (Ti) or an alloy thereof.

The method of forming the data line 114 and the drain electrode 126 includes forming a first metal material layer on the insulating substrate 140, forming a first photosensitive layer (not shown) on the first metal material layer, Forming a first photosensitive layer pattern by exposure and development of a first photosensitive layer using a first mask (not shown), and forming a first photosensitive layer pattern using the first photosensitive layer pattern as an etching mask And patterning the material layer.

An interlayer insulating layer 142 and an active layer 124 are formed on the insulating substrate 140 including the data wiring 114 and the drain pattern 126 as shown in FIG. do. The active layer 124 includes a first active layer 124a overlapping the data line 114 and the gate line 112 of FIG. 2 and a second active layer 124b formed on the pixel area PA.

The interlayer insulating layer 142 is formed using an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx), for example, by a method such as PECVD. The interlayer insulating layer 142 is stacked over the entire insulating substrate 140 including the data line 114 and the drain pattern 126.

The method of forming the active layer 124 includes forming a first amorphous silicon layer (not shown) not doped with an impurity on the interlayer insulating layer 142, forming a first amorphous silicon layer doped with an N- (Not shown), forming a second photosensitive layer (not shown) on the second amorphous silicon layer, forming a second photosensitive layer (not shown) using a second mask Forming a second photosensitive layer pattern by exposure and development of a layer, and patterning the first and second amorphous silicon layers using the second photosensitive layer pattern as an etching mask. In the process of patterning the first and second amorphous silicon layers, the second amorphous silicon layer of the active layer 124 overlapping the gate wiring 112 of FIG. 2 used as the gate electrode can be etched.

The gate insulating layer 146 is formed on the interlayer insulating layer 142 including the active layer 124 and the gate wiring 112 and the common electrode 120 A second metal material layer pattern 144 patterned to form a second metal material layer (not shown) is formed.

The gate insulating layer 146 is formed using an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx), for example, by a method such as PECVD. The second metal material layer pattern 144 includes a second lower metal material layer pattern 144a made of a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO), copper (Cu), molybdenum (Mo) , A second upper metal material layer pattern 144b made of a conductive metal material such as aluminum (Al), an aluminum alloy (AlNd), and chromium (Cr). The second upper metal material layer pattern 144b may be formed of a conductive metal such as copper (Cu), molybdenum (Mo), aluminum (Al), aluminum alloy (AlNd), and chromium (Cr) .

The method of forming the second metal material layer pattern 144 may include forming a second metal material layer (not shown) on the gate insulating layer 146, forming a third photosensitive layer (not shown) on the second metal material layer The first pattern 148a of the third photosensitive layer and the second pattern 148b of the third photosensitive layer are exposed and developed by applying a third mask 160 having a halftone pattern, 2 pattern 148b and patterning the second metal material layer using the first and second patterns 148a and 148b of the third photosensitive layer as an etching mask.

The third photosensitive layer uses a positive type photosensitive material from which light is irradiated. It is possible to use a negative type photosensitive material in which a region not irradiated with light is removed as needed. The third mask 160 includes a transmissive area TA for transmitting all the irradiated light, a shielding area BA for completely blocking the irradiated light, and a semi-transmissive area HTA for transmitting a part of the irradiated light. The gate line 112 of FIG. 3 corresponds to the blocking region BA of the third mask 160 and the common electrode 120 of FIG. 3 corresponds to the semi-transparent region HTA of the third mask 160 . 3, the region other than the gate line 112 and the common electrode 120 corresponds to the transmissive region TA of the third mask 160. [

2 and the first pattern 148a of the third photosensitive layer corresponds to the common electrode 120 of FIG. 2 (corresponding to the common electrode 120 of FIG. 2) And has a thickness thicker than the second pattern 148b of the third photosensitive layer. The second metal material layer pattern 144 is formed by etching the second metal material layer using the first and second patterns 148a and 148b of the third photosensitive layer as an etching mask.

The gate wiring 112 and the common electrode 120 are formed on the gate insulating layer 146 as shown in FIG. In the first embodiment of the present invention, as shown in FIG. 2, a part of the gate wiring 112 overlapping with the active layer 124 is used as a gate electrode, but a protruding pattern extending from the gate wiring 112 can be used as a gate electrode have. The gate wirings 112 are arranged in a second direction perpendicular to the data wirings 114 arranged in the first direction.

In FIG. 4C, while the first and second patterns 148a and 148b of the third photosensitive layer are etched using the etching mask to form the second metal material layer pattern 144, The second pattern 148b of the third photosensitive layer having a second thickness that is thinner than the first thickness of the first pattern 148a is removed as shown in Figure 4d and the second upper metal material layer pattern 144b , A common electrode 120 composed of the second lower metal material layer pattern 144a of FIG. 4C is formed.

When the second pattern 148b of the third photosensitive layer and the second upper metal material layer pattern 144b of FIG. 4c are removed and the first pattern 148a of the third photosensitive layer of FIG. 4c is thinned, A portion of the first pattern 148a of the third photosensitive layer remains on the gate wiring 112 as shown in FIG. 4D, and finally the first pattern 148a of the third photosensitive layer is removed. 4D, the gate wiring 112 is composed of the second lower and upper metal material layer patterns 144a and 144b, and the common electrode 120 is formed of the second lower metal material layer pattern 144a of FIG. .

A protective layer 150 is formed on the gate insulating layer 146 including the gate wiring 112 and the common electrode 120 and the drain electrode 126 and the first active layer 124a First to fourth contact holes CNT1, CNT2, CNT3, and CNT4 are formed to expose the first active layer 124, the second active layer 124b, and the data line 114 used as the source electrode. The passivation layer 150 may be formed of an inorganic insulating material including silicon oxide (SiO2) and silicon nitride (SiNx), or an organic insulating material including photoacrylic and benzocyclobutene.

The method of forming the first through fourth contact holes CNT1, CNT2, CNT3 and CNT4 includes the steps of forming a fourth photosensitive layer (not shown) on the protective layer 150, forming a fourth mask Forming a fourth photosensitive layer pattern (not shown) by exposing and developing the fourth photosensitive layer to which the first photosensitive layer pattern is applied, and forming the fourth photosensitive layer pattern using the etching interlayer insulating layer 142, the gate insulating layer 146 And the protective layer 150, as shown in FIG.

The first contact hole CNT1 exposes the data line 114 used as a source electrode by selectively etching the interlayer insulating layer 142, the gate insulating layer 146 and the protective layer 150, The second contact hole CNT2 exposes the second active layer 124b by selective etching of the gate insulating layer 146 and the protective layer 150 and the third contact hole CNT3 exposes the gate insulating layer 146 and the protective layer 150 The fourth contact hole CNT4 is formed by selectively etching the interlayer insulating layer 142, the gate insulating layer 146 and the passivation layer 150 to expose the first active layer 124a, (Not shown).

A connection pattern 130 connecting the first active layer 124a and the data line 114 used as the source electrode through the first and second contact holes CNT1 and CNT2, The second active layer 124b and the drain electrode 126 are connected to each other through the third and fourth contact holes CNT3 and CNT4 to form the pixel electrode 118 formed on the pixel region PA. The pixel electrode 118 includes a connection portion for connecting the second active layer 124b and the drain electrode 126 through the third and fourth contact holes CNT3 and CNT4. The pixel electrode 118 and the connection pattern 130 are formed of a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO).

The method of forming the pixel electrode 118 and the connection pattern 130 includes forming a transparent conductive material layer (not shown) on the protective layer 150 including the first to fourth contact holes CNT1, CNT2, CNT3, Forming a fifth photosensitive layer (not shown) on the transparent conductive material layer, and exposing and developing the fifth photosensitive layer to which a fifth mask (not shown) is applied to form a fifth photosensitive layer Forming a layer pattern (not shown), and patterning the transparent conductive material layer using the fifth photosensitive layer pattern as an etching mask.

The pixel electrode 118 connected to the drain electrode 126 and formed in the pixel region PA is formed in a plate shape having a plurality of openings 118a. The liquid crystal can be driven by the fringe field induced between the pixel electrode 118 and the common electrode 120 corresponding to the plurality of openings 118a.

Second Embodiment

5A to 5F are process cross-sectional views showing steps of a method of manufacturing an array substrate for a liquid crystal display according to a second embodiment of the present invention. FIGS. 5A to 5F show a step-by-step method of manufacturing the array substrate 110 by cutting the array substrate 110 of FIG. 2 into I-I '. For convenience of description, the insulating substrate 140 is divided into a pixel region PA and a data line DA. In the second embodiment of the present invention, the same reference numerals are used for the same components as in the first embodiment .

5A, a first metal material layer (not shown) is formed on an insulating substrate 140, and a first metal material layer is patterned to form a drain wiring 114 and a drain electrode 126. [ The data line 114 is a line pattern extending in the first direction and the drain electrode 126 is an isolated pattern formed in the pixel area PA. A buffer layer may be formed on the insulating substrate 140 before forming the first metal material layer. The buffer layer serves to prevent the impurities from eluting from the insulating substrate 140.

The method of forming the data line 114 and the drain electrode 126 includes forming a first metal material layer on the insulating substrate 140, forming a first photosensitive layer (not shown) on the first metal material layer, Forming a first photosensitive layer pattern by exposure and development of a first photosensitive layer using a first mask (not shown), and forming a first photosensitive layer pattern using the first photosensitive layer pattern as an etching mask Layer patterning step.

An interlayer insulating layer 142 and an active layer 124 are formed on the insulating substrate 140 including the data line 114 and the drain electrode 126 as shown in FIG. do. The active layer 124 includes a first active layer 124a overlapping the data line 114 and the gate line 112 of FIG. 2 and a first active layer 124b formed on the pixel area PA.

The method of forming the active layer 124 includes forming a first amorphous silicon layer (not shown) not doped with an impurity on the interlayer insulating layer 142, forming a first amorphous silicon layer doped with an N- (Not shown), forming a second photosensitive layer (not shown) on the second amorphous silicon layer, forming a second photosensitive layer (not shown) using a second mask Forming a second photosensitive layer pattern by exposure and development of a layer, and patterning the first and second amorphous silicon layers using the second photosensitive layer pattern as an etching mask. In the process of patterning the first and second amorphous silicon layers, the second amorphous silicon layer of the active layer 121 overlapping the gate wiring 112 used as the gate electrode in FIG. 3 may be etched.

The first gate insulating layer 146a is formed on the interlayer insulating layer 142 including the active layer 124 and the common electrode 120 is formed on the first gate insulating layer 146a. The common electrode 120 is formed using a transparent conductive material such as ITO (indium tin oxide) and IZO (indium zinc oxide). As shown in FIG. 2, the common electrode 120 includes first and second openings 120a and 120b.

The method of forming the common electrode 120 includes forming a first transparent conductive material layer (not shown) on the first gate insulating layer 146a, forming a third photosensitive layer (not shown) on the first transparent conductive material layer A step of forming a third photosensitive layer pattern (not shown) by exposure and development of a third photosensitive layer to which a third mask (not shown) is applied, and a step of forming a third photosensitive layer pattern And patterning the first transparent conductive material layer using the first transparent conductive material layer as an etch mask.

A second gate insulating layer 146b is formed on the first gate insulating layer 146a including the common electrode 120 and a gate wiring 112 is formed on the second gate insulating layer 146b, . 2, a part of the gate wiring 112 overlapping with the active layer 124 is used as a gate electrode, but a protruding pattern extending from the gate wiring 112 can be used as a gate electrode have. The gate wirings 112 are arranged in a second direction perpendicular to the data wirings 114 arranged in the first direction.

The method of forming the gate wiring 112 includes forming a second metal material layer (not shown) on the second gate insulating layer 146a, forming a fourth photosensitive layer (not shown) on the second metal material layer, Forming a fourth photosensitive layer pattern (not shown) by exposure and development of a fourth photosensitive layer to which a fourth mask (not shown) is applied, and a step of forming a fourth photosensitive layer pattern And patterning the second metal material layer used as a mask. The gate wiring 112 may be formed of a single layer or a double layer using a conductive metal such as copper (Cu), molybdenum (Mo), aluminum (Al), aluminum alloy (AlNd), and chromium (Cr).

The protective layer 150 is formed on the second gate insulating layer 146b including the gate wiring 112 and the drain electrode 126, the first active layer 124a, the second active layer 124b, And first to fourth contact holes CNT1, CNT2, CNT3 and CNT4 are formed to expose the data lines 114 used as the source electrodes. The passivation layer 150 may be formed of an inorganic insulating material including silicon oxide (SiO2) and silicon nitride (SiNx), or an organic insulating material including photoacrylic and benzocyclobutene.

The method of forming the first to fourth contact holes CNT1, CNT2, CNT3 and CNT4 includes the steps of forming a fifth photosensitive layer (not shown) on the protective layer 150, forming a fifth mask Forming a fifth photosensitive layer pattern (not shown) by the exposure and development of the fifth photosensitive layer to which the first photosensitive layer pattern is applied, and forming the fifth photosensitive layer pattern using the etching mask in the interlayer insulating layer 142, And selectively etching the gate insulating layers 146a and 146b and the protective layer 150. [

The first contact hole CNT1 is formed by selectively etching the interlayer insulating layer 142, the first and second gate insulating layers 146a and 146b and the protective layer 150 to form the data wiring 114 The second contact hole CNT2 exposes the first active layer 124a by selective etching of the first and second gate insulating layers 146a and 146b and the passivation layer 150 and exposes the third contact hole CNT3 exposes the second active layer 124b by selective etching of the first and second gate insulating layers 146a and 146b and the passivation layer 150 and the fourth contact hole CNT4 exposes the interlayer insulating layer 142 ), The first and second gate insulating layers 146a and 146b, and the passivation layer 150 are selectively etched to expose the drain electrode 126.

A connection pattern 130 connecting the first active layer 124a and the data line 114 used as the source electrode through the first and second contact holes CNT1 and CNT2, The second active layer 124b and the drain electrode 126 are connected to each other through the third and fourth contact holes CNT3 and CNT4 to form the pixel electrode 118 formed on the pixel region PA. The pixel electrode 118 includes a connection portion for connecting the second active layer 124b and the drain electrode 126 through the third and fourth contact holes CNT3 and CNT4. The pixel electrode 118 and the connection pattern 130 are formed of a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO).

The method of forming the pixel electrode 118 and the connection pattern 130 includes forming a second transparent conductive material layer (not shown) on the passivation layer 150 including the first through fourth contact holes CNT1, CNT2, CNT3, and CNT4 Forming a sixth photosensitive layer (not shown) on the second transparent conductive material layer, exposing and developing the sixth photosensitive layer to which a sixth mask (not shown) is applied Forming a sixth photosensitive layer pattern (not shown) on the first photosensitive layer pattern, and patterning the second transparent conductive material layer using the sixth photosensitive layer pattern as an etching mask.

The pixel electrode 118 connected to the drain electrode 126 and formed in the pixel region PA is formed in a plate shape having a plurality of openings 118a. The liquid crystal can be driven by the fringe field induced between the pixel electrode 118 and the common electrode 120 corresponding to the plurality of openings 118a.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

Claims (15)

Forming a data line and a drain electrode to be used as a source electrode on a substrate including a pixel region;
Forming an interlayer insulating layer on the substrate including the data line and the drain electrode, and forming an active layer on the data line and the interlayer insulating layer corresponding to the pixel region;
Forming a gate insulating layer on the interlayer insulating layer including the active layer, forming a gate electrode on the gate insulating layer, the gate electrode being perpendicular to the data line and used as a gate electrode;
Forming a protective layer on the gate insulating layer including the gate wiring and the common electrode; selectively etching the interlayer insulating layer, the gate insulating layer, and the protective layer to form the data line, the active layer, Forming a plurality of contact holes to expose a plurality of contact holes; And
Forming a connection pattern connecting the source electrode and the active layer through the plurality of contact holes and a pixel electrode connecting the drain electrode and the active layer and generating a vertical electric field with the common electrode;
And forming a plurality of pixel electrodes on the array substrate.
The method according to claim 1,
And the drain electrode is formed in an isolated pattern.
The method according to claim 1,
Wherein the active layer includes a first active layer overlapping the data line and the gate line, and a second active layer formed in the pixel region.
The method of claim 3,
A first contact hole through which the data line used as the source electrode is exposed, a second contact hole through which the first active layer is exposed by selective etching of the interlayer insulating layer, the gate insulating layer, and the protective layer, The third contact hole exposing the active layer, and the fourth contact hole exposing the drain electrode are formed at the same time.
5. The method of claim 4,
The connection pattern connects the data line and the first active layer through the first and second contact holes and the pixel electrode connects the second active layer and the drain electrode through the third and fourth contact holes Wherein the first substrate and the second substrate are bonded to each other.
5. The method of claim 4,
Wherein the common electrode has a first opening corresponding to the first and second contact holes and a second opening corresponding to the third and fourth contact holes.
The method according to claim 1,
Wherein one of the pixel electrode and the common electrode has a plurality of openings.
The method according to claim 1,
Wherein forming the gate electrode and the common electrode comprises:
Forming a lower and upper metal material layer on the gate insulating layer;
Forming a photosensitive layer on the upper metal material layer;
Forming a first photosensitive layer pattern having a first thickness on the gate electrode by exposure and development of the photosensitive layer to which a halftone mask is applied and a second photosensitive layer pattern having a second thickness thinner than the first thickness step; And
Patterning the lower and upper metal material layers using the first and second photosensitive layer patterns as an etching mask;
And forming a plurality of pixel electrodes on the array substrate.
A substrate having a pixel region defined therein;
A data line disposed on the substrate and extending in a first direction;
A drain electrode located on the substrate and spaced apart from the data line;
An interlayer insulating layer covering the data line and the drain electrode;
An active layer located on the interlayer insulating layer and overlapping a source electrode which is a part of the data line;
A gate insulating layer covering the active layer;
A gate line extending on the gate insulating layer and extending in a second direction to intersect the data line to define the pixel region and a portion overlapping the active layer is used as a gate electrode;
A protective layer covering the gate wiring;
A connection part located on the protection layer and connecting the drain electrode and the active layer;
A connection pattern located on the protection layer and connecting the source electrode and the active layer;
A pixel electrode extending from the connection portion and located in the pixel region;
And a common electrode formed in the pixel region to generate an electric field with the pixel electrode,
And an array substrate on which the liquid crystal panel is mounted.
10. The method of claim 9,
And the drain electrode is formed in an isolated pattern.
10. The method of claim 9,
Wherein the active layer includes a first active layer overlapping the data line and the gate line, and a second active layer formed in the pixel region.
12. The method of claim 11,
A first contact hole through which the data line used as the source electrode is exposed by removing the interlayer insulating layer, the gate insulating layer, and the protective layer, a second contact hole through which the first active layer is exposed, A third contact hole to be exposed, and a fourth contact hole to expose the drain electrode.
13. The method of claim 12,
The connection pattern connects the data line and the first active layer through the first and second contact holes and the connection unit connects the second active layer and the drain electrode through the third and fourth contact holes And a plurality of pixel electrodes formed on the substrate.
10. The method of claim 9,
Wherein the common electrode has a first opening corresponding to the connection portion and a second opening corresponding to the connection pattern.
10. The method of claim 9,
And one of the pixel electrode and the common electrode has a plurality of openings.

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