CN114594639A

CN114594639A - Array substrate and manufacturing method

Info

Publication number: CN114594639A
Application number: CN202210231854.5A
Authority: CN
Inventors: 钟德镇; 郑会龙; 刘厚锋
Original assignee: InfoVision Optoelectronics Kunshan Co Ltd
Current assignee: InfoVision Optoelectronics Kunshan Co Ltd
Priority date: 2022-03-09
Filing date: 2022-03-09
Publication date: 2022-06-07

Abstract

The invention discloses an array substrate and a manufacturing method thereof, wherein the array substrate comprises: a substrate; the data line, the bottom gate and the conductive part are arranged on the substrate; a first insulating layer covering the data line, the bottom gate and the conductive portion; an active layer, a source electrode, a drain electrode and a pixel electrode which are arranged on the first insulating layer; the active layer is arranged on the substrate, the projection of the active layer on the substrate corresponds to an overlapping region of the projection of the top grid and the bottom grid on the substrate, and the bottom grid is in conductive connection with the scanning line through the conductive part. The top gate and the bottom gate are respectively arranged on the upper side and the lower side of the active layer, the top gate and the bottom gate can respectively shield external environment light and backlight for the active layer, the top gate and the bottom gate can also be used as shielding electrodes to avoid the active layer from being interfered by data signals, and the bottom gate and the data line are both made of the same metal layer, so that the manufacturing process is greatly simplified; in addition, the active layer is simultaneously controlled by the top gate and the bottom gate, so that the performance of the TFT is better.

Description

Array substrate and manufacturing method

Technical Field

The invention relates to the technical field of displays, in particular to an array substrate and a manufacturing method thereof.

Background

With the development of display technology, a light and thin display panel is popular with consumers, especially a light and thin Liquid Crystal Display (LCD).

When the display device works, a driving voltage is respectively applied to a pixel electrode of the Thin Film Transistor Array Substrate and a common electrode of the Color Film Substrate or applied to a common electrode and a pixel electrode of the Thin Film Transistor Array Substrate, and a rotation direction of liquid crystal molecules between the two substrates is controlled, so that backlight provided by a backlight module of the display device is refracted, and a picture is displayed.

An oxide Thin Film Transistor (TFT) in the prior art has the advantages of excellent electrical property, large-area manufacturing uniformity, low manufacturing cost and the like, and is expected to be applied to various flat panel display products. When the bottom gate type TFT is applied to an LCD display panel, the grid electrode of the bottom gate type TFT can be used as a light shielding layer, and the characteristic degradation of an oxide active layer caused by illumination can be avoided. In addition to the bottom gate TFT, the top gate TFT is provided in the prior art, and in order to save the manufacturing process, the source electrode, the drain electrode, and the active layer are usually made of the same metal oxide semiconductor layer, and then the metal oxide semiconductor layer is subjected to conductor processing by using the gate of the top gate TFT as a shield, so that the overlapping amount of the gate and the source/drain electrode is reduced, and the parasitic capacitance of the device is reduced. However, in order to avoid the device characteristics degradation of the oxide active layer due to the exposure to light, the top gate TFT also needs to separately provide a light shielding layer at the bottom, which increases the manufacturing process.

In order to simultaneously take the advantages of a bottom gate type TFT and a top gate type TFT into account, a double-gate type TFT is provided, and the double-gate type TFT has the characteristic advantages of larger driving current, steeper sub-threshold slope and the like compared with a single-gate device, but a yellow light manufacturing process is always the bottleneck of factory productivity, and the manufacturing process of the double-gate type TFT is more complex compared with the single-gate device.

Disclosure of Invention

In order to overcome the defects and shortcomings in the prior art, the invention aims to provide an array substrate and a manufacturing method thereof, so as to solve the problem that the manufacturing process of a double-gate type TFT in the prior art is complex.

The purpose of the invention is realized by the following technical scheme:

the invention provides an array substrate, comprising:

a substrate;

the first metal layer is arranged on the upper surface of the substrate and comprises a data line, a bottom gate insulated from the data line and a conductive part in conductive connection with the bottom gate;

the first insulating layer is arranged on the upper surface of the first metal layer and covers the data line, the bottom gate and the conductive part;

a metal oxide semiconductor layer disposed over the first insulating layer, the metal oxide semiconductor layer including a conductor portion and a semiconductor portion, the semiconductor portion including an active layer, the conductor portion including a source electrode, a drain electrode, and a pixel electrode, the source electrode and the drain electrode being connected through the active layer, the source electrode being conductively connected to the data line, the pixel electrode being conductively connected to the drain electrode;

the metal oxide semiconductor layer comprises a grid electrode insulating layer and a second metal layer, the grid electrode insulating layer is arranged above the metal oxide semiconductor layer, the second metal layer is arranged above the grid electrode insulating layer and comprises scanning lines and a top grid, the projection of the active layer on the substrate corresponds to the overlapped area of the projection of the top grid and the projection of the bottom grid on the substrate, the overlapped area of the scanning lines and the active layer serves as the top grid, and the conducting part is in conductive connection with the scanning lines.

Further, the active layer, the source electrode, the drain electrode, the bottom gate and the top gate are all located on a central line of the data line.

Furthermore, the first metal layer further comprises a first connection portion located at the periphery of the bottom gate, and the first connection portion connects two portions of the data line located at two sides of the bottom gate.

Further, the array substrate further includes: the second insulating layer is arranged above the second metal layer, and the transparent conducting layer is arranged above the second insulating layer and comprises a common electrode, and a slit is formed in the region, corresponding to the pixel electrode, of the common electrode.

Furthermore, the transparent conducting layer also comprises a second connecting part insulated from the common electrode, and the second connecting part connects two parts of the data line, which are positioned at two sides of the bottom gate; one end of the second connecting portion is in conductive connection with the data line, and the other end of the second connecting portion is in conductive connection with the source electrode.

Further, the transparent conductive layer further includes a third connecting portion insulated from the common electrode, and the third connecting portion electrically connects the conductive portion and the scan line.

The invention also provides a manufacturing method of the array substrate, which comprises the following steps:

providing a substrate;

forming a first metal layer on the substrate, etching the first metal layer, and patterning the first metal layer to form a data line, a bottom gate insulated from the data line, and a conductive part conductively connected with the bottom gate;

forming a first insulating layer covering the data line, the bottom gate and the conductive part on the upper surface of the first metal layer;

forming a metal oxide semiconductor layer over the first insulating layer, etching the metal oxide semiconductor layer, the metal oxide semiconductor layer being patterned to form an active layer, a source electrode, a drain electrode, and a pixel electrode, the source electrode and the drain electrode being connected through the active layer, the source electrode being conductively connected to the data line, the pixel electrode being conductively connected to the drain electrode;

sequentially forming a gate insulating layer and a second metal layer above the metal oxide semiconductor layer, etching the second metal layer, patterning the second metal layer to form a scanning line and a top gate, wherein the projection of the active layer on the substrate corresponds to the overlapping region of the projection of the top gate and the projection of the bottom gate on the substrate, the overlapping region of the scanning line and the active layer serves as the top gate, and the conductive part is in conductive connection with the scanning line;

and conducting the metal oxide semiconductor layer using the second metal layer as a mask, wherein regions of the metal oxide semiconductor layer corresponding to the source electrode, the drain electrode, and the pixel electrode are made conductive, and regions of the metal oxide semiconductor layer corresponding to the active layer are kept as a semiconductor.

Further, the active layer, the source electrode, the drain electrode, the bottom gate, and the top gate are all located on a central line of the data line.

Furthermore, when the first metal layer is etched, a first connecting portion located at the periphery of the bottom gate is further formed, and the two portions of the data line located at the two sides of the bottom gate are connected through the first connecting portion.

Further, the manufacturing method further comprises: forming a second insulating layer above the second metal layer and a transparent conductive layer above the second insulating layer, etching the transparent conductive layer, patterning the transparent conductive layer to form a common electrode and second and third connection portions insulated from the common electrode, the common electrode having a slit in a region corresponding to the pixel electrode, the second connection portion connecting two portions of the data line on both sides of the bottom gate, and the third connection portion electrically connecting the conductive portion with the scan line.

The invention has the beneficial effects that: the top grid and the bottom grid are respectively arranged on the upper side and the lower side of the active layer, the top grid and the bottom grid can respectively shield external environment light and backlight for the active layer, a light shielding layer is not required to be additionally arranged, the problem of TFT device characteristic degradation caused by illumination of the active layer can be avoided, the top grid and the bottom grid can also be used as shielding electrodes, shielding electrodes are not required to be additionally arranged, the active layer can be prevented from being interfered by data signals, and the bottom grid and the data wire are both made of the same metal layer, so that the manufacturing process is greatly simplified; in addition, the active layer, the source electrode, the drain electrode and the pixel electrode are all made of metal oxide semiconductor layers, so that the manufacturing process is further simplified, and the aperture opening ratio of the pixel can be increased; the active layer is simultaneously controlled by the top gate and the bottom gate, so that the TFT has the characteristics of larger driving current, steeper sub-threshold slope and the like.

Drawings

Fig. 1 is a schematic plan view of an array substrate according to an embodiment of the invention;

FIG. 2 is a schematic cross-sectional view of the array substrate along the direction A-A in FIG. 1 according to one embodiment of the present invention;

FIG. 3 is a schematic cross-sectional view of the array substrate along the direction B-B in FIG. 1 according to one embodiment of the present invention;

FIG. 4 is a schematic cross-sectional view of the array substrate along the direction C-C in FIG. 1 according to one embodiment of the present invention;

FIGS. 5a-5h are schematic diagrams illustrating a method of fabricating the array substrate along a direction B-B in FIG. 1 according to an embodiment of the invention;

FIGS. 6a-6e are schematic views illustrating a method of fabricating the array substrate along the direction C-C in FIG. 1 according to one embodiment of the present invention;

FIGS. 7a to 7e are schematic plan views illustrating a method for fabricating an array substrate according to an embodiment of the invention;

FIG. 8 is a schematic plan view of a substrate and a first metal layer in a second embodiment of the present invention;

FIG. 9 is a schematic cross-sectional view of the array substrate along the direction B-B in FIG. 1 according to a second embodiment of the present invention;

fig. 10 is a schematic cross-sectional view of a display panel according to the present invention.

Detailed Description

To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description of the embodiments, structures, features and effects of the array substrate and the manufacturing method according to the present invention will be made with reference to the accompanying drawings and preferred embodiments:

[ example one ]

Fig. 1 is a schematic plan view of an array substrate according to an embodiment of the invention. Fig. 2 is a schematic cross-sectional view of the array substrate along the direction a-a in fig. 1 according to an embodiment of the invention. Fig. 3 is a schematic cross-sectional view of the array substrate along the direction B-B in fig. 1 according to an embodiment of the invention. Fig. 4 is a schematic cross-sectional view of the array substrate along the direction C-C in fig. 1 according to an embodiment of the invention.

As shown in fig. 1 to 4, an array substrate according to a first embodiment of the present invention includes:

the substrate 10, the substrate 10 may be made of glass, quartz, silicon, acrylic or polycarbonate, etc., and the substrate 10 may also be a flexible substrate, and suitable materials for the flexible substrate include, for example, Polyethersulfone (PES), polyethylene naphthalate (PEN), Polyethylene (PE), Polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET), or a combination thereof.

A first metal layer 11 disposed on the upper surface of the substrate 10, wherein the first metal layer 11 includes a data line 111, a bottom gate 112 insulated from the data line 111, and a conductive portion 114 electrically connected to the bottom gate 112 (fig. 4 and 7 a). Among them, the first metal layer 11 may employ a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or the like, or employ a combination of the above metals such as Al/Mo, Cu/Mo, or the like.

And a first insulating layer 101 disposed on the upper surface of the first metal layer 11, wherein the first insulating layer 101 covers the data line 111, the bottom gate 112 and the conductive portion 114. In this embodiment, the first insulating layer 101 is provided with a first contact hole 104 (fig. 5b) at a position corresponding to the data line 111, and the data line 111 is exposed from the first contact hole 104. The material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof.

A metal oxide semiconductor layer 12 (fig. 5c, 7b) provided over the first insulating layer 101, preferably, the metal oxide semiconductor layer 12 is provided directly on the upper surface of the first insulating layer 101. The metal oxide semiconductor layer 12 includes a conductor part including an active layer 121, a source electrode 122, a drain electrode 123, and a pixel electrode 124, the source electrode 122 and the drain electrode 123 are connected through the active layer 121, the source electrode 122 is electrically connected to the data line 111 through the first contact hole 104, and the pixel electrode 124 is directly electrically connected to the drain electrode 123.

Specifically, the partial region of the metal oxide semiconductor layer 12 may be made conductive by conducting a conductive treatment to the metal oxide semiconductor layer 12, for example, a treatment using plasma, ion bombardment, hydrogen (H2) doping, helium (He) doping, argon (Ar) doping, and the like, to form the conductive source and drain

electrodes

122 and 123 and the pixel electrode 124, but the active layer 121 is not made conductive and remains as a semiconductor. Alternatively, the metal oxide semiconductor layer 12 may be subjected to a conductor forming process using ultraviolet light. The metal oxide semiconductor layer 12 is preferably made of a transparent metal oxide semiconductor material such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), Indium Gallium Zinc Oxide (IGZO), or Indium Gallium Zinc Tin Oxide (IGZTO). By forming the active layer 121, the source electrode 122, the drain electrode 123, and the pixel electrode 124 using the metal oxide semiconductor layer 12, the source electrode 122, the drain electrode 123, and the pixel electrode 124 do not need to be formed by an additional process, and thus the manufacturing process can be simplified. In addition, the metal oxide semiconductor layer 12 is in a transparent state, so that the source electrode 122, the drain electrode 123 and the pixel electrode 124 are all in a transparent state, and the aperture ratio of the pixel can be increased.

Preferably, the active layer 121, the source electrode 122, the drain electrode 123 and the bottom gate 112 are all located on a central line of the data line 111, that is, the active layer 121, the source electrode 122, the drain electrode 123 and the bottom gate 112 are all located on the same straight line with the data line 111, and the central line of the data line 111 is parallel to the length direction of the data line 111. So that the lengths of the source and drain

electrodes

122 and 123 can be reduced and the aperture ratio of the pixel can be improved. Since the resistivity of the metal oxide semiconductor layer 12 is large relative to the resistivity of metal, reducing the lengths of the source and drain

electrodes

122 and 123 may increase the signal conductivity.

A gate insulating layer 102 disposed on the metal oxide semiconductor layer 12, and a second metal layer 13 disposed on the gate insulating layer 102 (fig. 7c), wherein the gate insulating layer 102 is preferably disposed directly on the upper surface of the metal oxide semiconductor layer 12, and the second metal layer 13 is preferably disposed directly on the upper surface of the gate insulating layer 102. The second metal layer 13 includes a scan line 131 and a top gate 132, and preferably, the scan line 131 and the data line 111 extend in a direction perpendicular to each other, and a region where the scan line 131 overlaps the active layer 121 serves as the top gate 132. The projection of the active layer 121 on the substrate 10 corresponds to the overlapping area of the top gate 132 and the bottom gate 112 projected on the substrate 10, and the size of the active layer 121 is smaller than or equal to the size of the overlapping area of the top gate 132 and the bottom gate 112 projected on the substrate 10. The top gate 132 and the bottom gate 112 are respectively arranged on the upper side and the lower side of the active layer 121 to form a double-gate TFT device, the top gate 132 and the bottom gate 112 can respectively shield external environment light and backlight for the active layer 121, a light shielding layer is not required to be additionally arranged, the problem of characteristic degradation of the TFT device caused by illumination on the active layer 121 can be avoided, the top gate 132 and the bottom gate 112 can also be used as shielding electrodes, the shielding electrodes are not required to be additionally arranged, the active layer 121 can be prevented from being interfered by data signals, the bottom gate 112 and the data line 111 are both made of the first metal layer 11, and the manufacturing process is greatly simplified; the active layer 121 is simultaneously controlled by the top gate 132 and the bottom gate 112, so that the TFT has characteristics of larger driving current, steeper subthreshold slope, and the like. The material of the gate insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof. The second metal layer 13 may use a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al/Mo, Cu/Mo, etc.

In this embodiment, the array substrate further includes a second insulating layer 103 disposed above the second metal layer 13 and a transparent conductive layer 14 disposed above the second insulating layer 103, the transparent conductive layer 14 includes a common electrode 141, and a region of the common electrode 141 corresponding to the pixel electrode 124 has a slit. Thereby making the array substrate suitable for a Fringe Field Switching (FFS) or In-Plane Switching (IPS) display panel. Of course, in other embodiments, the common electrode 141 may not be disposed on the array substrate, but the common electrode 141 is disposed on the color film substrate 20 (fig. 10), so that the array substrate may be suitable for a TN mode or VA mode display panel. The material of the second insulating layer 103 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof. The material of the transparent conductive layer 14 is Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), or the like.

Further, the transparent conductive layer 14 further includes a second connection portion 142 insulated from the common electrode 141, and the second connection portion 142 connects two portions of the data line 111 on both sides of the bottom gate 112, referring to fig. 7a and 7 e. Preferably, the second connection portion 142 is located on a center line of the data line 111, i.e., the second connection portion 142 has a partial overlap with a projection of the data line 111 on the substrate 10. Although the second connection portion 142 and the projection of the active layer 121 on the substrate 10 also have a partial overlap, the top gate 132 is disposed between the active layer 121 and the second connection portion 142, and the top gate 132 can shield the data signal on the second connection portion 142, thereby effectively preventing the active layer 121 from being interfered by the data signal.

In this embodiment, the second insulating layer 103 and the gate insulating layer 102 are provided with a second contact hole 105 (fig. 5g) corresponding to the source electrode 122, the source electrode 122 is exposed from the second contact hole 105, preferably, the second contact hole 105 is vertically aligned with the first contact hole 104, and one end of the second connecting portion 142 is electrically connected to the source electrode 122 through the second contact hole 105, that is, one end of the second connecting portion 142 is indirectly electrically connected to the data line 111 through the source electrode 122. The first insulating layer 101, the gate insulating layer 102 and the second insulating layer 103 are provided with a third contact hole 106 (fig. 5g) corresponding to the data line 111, that is, the third contact hole 106 penetrates the first insulating layer 101, the gate insulating layer 102 and the second insulating layer 103, and the data line 111 is exposed from the third contact hole 106, so that the other end of the second connection portion 142 is conductively connected to the data line 111 through the third contact hole 106.

Further, as shown in fig. 4, the transparent conductive layer 14 further includes a third connecting portion 143 insulated from the common electrode 141, and the third connecting portion 143 electrically connects the conductive portion 114 and the scan line 131. Preferably, the third connecting portion 143 and the conductive portion 114 are located on a central line of the scan line 131, that is, the third connecting portion 143 has a partial overlap with a projection of the scan line 131 on the substrate 10, the third connecting portion 143 has a partial overlap with a projection of the conductive portion 114 on the substrate 10, and the scan line 131 has a partial non-overlap with a projection of the conductive portion 114 on the substrate 10.

In this embodiment, the second insulating layer 103 is provided with a fourth contact hole 107 (fig. 6e) corresponding to the scan line 131, the scan line 131 is exposed from the fourth contact hole 107, and one end of the third connecting portion 143 is electrically connected to the scan line 131 through the fourth contact hole 107. The first insulating layer 101, the gate insulating layer 102 and the second insulating layer 103 are provided with a fifth contact hole 108 (fig. 6e) corresponding to the conductive portion 114, i.e., the fifth contact hole 108 penetrates through the first insulating layer 101, the gate insulating layer 102 and the second insulating layer 103, and the conductive portion 114 is exposed from the fifth contact hole 108, so that the other end of the third connecting portion 143 is conductively connected to the conductive portion 114 through the fifth contact hole 108.

Fig. 5a to 5h are schematic diagrams illustrating a method for manufacturing the array substrate along a direction B-B in fig. 1 according to an embodiment of the invention. Fig. 6a to 6e are schematic diagrams illustrating a method for manufacturing the array substrate along a direction C-C in fig. 1 according to an embodiment of the invention. Fig. 7a to 7e are schematic plan views illustrating a manufacturing method of an array substrate according to an embodiment of the invention. As shown in fig. 5a to 7e, the present embodiment further provides a manufacturing method of an array substrate, the manufacturing method is used for manufacturing the array substrate, and the manufacturing method includes:

as shown in fig. 5a, 6a and 7a, a substrate 10 is provided, the substrate 10 may be made of glass, quartz, silicon, acrylic or polycarbonate, etc., the substrate 10 may also be a flexible substrate, and suitable materials for the flexible substrate include, for example, Polyethersulfone (PES), polyethylene naphthalate (PEN), Polyethylene (PE), Polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET), or a combination thereof.

A first metal layer 11 is formed on a substrate 10, the first metal layer 11 is etched, and the first metal layer 11 is patterned to form a data line 111, a bottom gate 112 insulated from the data line 111, and a conductive portion 114 conductively connected to the bottom gate 112. Among them, the first metal layer 11 may employ a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al/Mo, Cu/Mo, etc.

As shown in fig. 5b and 6b, a first insulating layer 101 covering the data line 111, the bottom gate 112, and the conductive portion 114 is formed on the upper surface of the first metal layer 11. The first insulating layer 101 is etched such that the first insulating layer 101 is provided with a first contact hole 104 at a position corresponding to the data line 111, and the data line 111 is exposed from the first contact hole 104. The material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof.

As shown in fig. 5c, 5d, and 7b, the metal oxide semiconductor layer 12 is formed over the first insulating layer 101, the metal oxide semiconductor layer 12 is etched, the metal oxide semiconductor layer 12 is patterned to form an active layer 121, a source electrode 122, a drain electrode 123, and a pixel electrode 124, the source electrode 122 and the drain electrode 123 are connected through the active layer 121, the source electrode 122 is electrically connected to the data line 111 through the first contact hole 104, and the pixel electrode 124 is directly electrically connected to the drain electrode 123. Among them, the metal oxide semiconductor layer 12 is preferably made of a transparent metal oxide semiconductor material such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), Indium Gallium Zinc Oxide (IGZO), or Indium Gallium Zinc Tin Oxide (IGZTO). By forming the active layer 121, the source electrode 122, the drain electrode 123, and the pixel electrode 124 using the metal oxide semiconductor layer 12, the source electrode 122, the drain electrode 123, and the pixel electrode 124 do not need to be formed by an additional process, and thus the manufacturing process can be simplified. In addition, the metal oxide semiconductor layer 12 is in a transparent state, so that the source electrode 122, the drain electrode 123, and the pixel electrode 124 are also in a transparent state, thereby increasing the aperture ratio of the pixel.

electrodes

122 and 123 may increase the signal conductivity.

As shown in fig. 5e, 6c and 7c, the gate insulating layer 102 and the second metal layer 13 are sequentially formed above the metal oxide semiconductor layer 12, preferably, the gate insulating layer 102 is directly provided on the upper surface of the metal oxide semiconductor layer 12, and the second metal layer 13 is directly provided on the upper surface of the gate insulating layer 102. The second metal layer 13 is etched, the second metal layer 13 is patterned to form a scan line 131 and a top gate 132, preferably, the scan line 131 and the data line 111 extend in a direction perpendicular to each other, and a region where the scan line 131 overlaps the active layer 121 serves as the top gate 132. The projection of the active layer 121 on the substrate 10 corresponds to the overlapping area of the top gate 132 and the bottom gate 112 projected on the substrate 10, and the size of the active layer 121 is smaller than or equal to the size of the overlapping area of the top gate 132 and the bottom gate 112 projected on the substrate 10. The top gate 132 and the bottom gate 112 are respectively arranged on the upper side and the lower side of the active layer 121 to form a double-gate TFT device, the top gate 132 and the bottom gate 112 can respectively shield external environment light and backlight for the active layer 121, a light shielding layer is not required to be additionally arranged, the problem of characteristic degradation of the TFT device caused by illumination on the active layer 121 can be avoided, the top gate 132 and the bottom gate 112 can also be used as shielding electrodes, the shielding electrodes are not required to be additionally arranged, the active layer 121 can be prevented from being interfered by data signals, the bottom gate 112 and the data line 111 are both made of the first metal layer 11, and the manufacturing process is greatly simplified; the active layer 121 is simultaneously controlled by the top gate 132 and the bottom gate 112, so that the TFT has characteristics of larger driving current, steeper subthreshold slope, and the like. The material of the gate insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof. The second metal layer 13 may use a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al/Mo, Cu/Mo, etc.

As shown in fig. 5f and 7d, the metal oxide semiconductor layer 12 is subjected to a conductor-forming process using the second metal layer 13 as a mask, so that the regions of the metal oxide semiconductor layer 12 corresponding to the source electrode 122, the drain electrode 123, and the pixel electrode 124 are made conductive, and the region of the metal oxide semiconductor layer 12 corresponding to the active layer 121 remains a semiconductor. Specifically, the exposed region of the metal oxide semiconductor layer 12 may be subjected to a conductor forming process by plasma treatment, and the exposed region of the metal oxide semiconductor layer 12, that is, the source electrode 122, the drain electrode 123, and the pixel electrode 124 may be subjected to a conductor forming process by ion bombardment, hydrogen (H2) doping, helium (He) doping, and argon (Ar) doping. Of course, in other embodiments, the metal oxide semiconductor layer 12 may be subjected to a conductor treatment by using ultraviolet light, so that the gate insulating layer 102 is not required to be etched, thereby reducing the etching process. By using the second metal layer 13 as a barrier, the top gate 112 is aligned with the active layer 121 up and down, and the overlapping amount with the source 122 and the drain 123 is small, so as to reduce the parasitic capacitance.

As shown in fig. 5g and 6d, a second insulating layer 103 is formed over the second metal layer 13, the second insulating layer 103 and the gate insulating layer 102 are etched, the second insulating layer 103 and the gate insulating layer 102 form a second contact hole 105 in a region corresponding to the source electrode 122, preferably, the second contact hole 105 is aligned with the first contact hole 104 up and down, and the source electrode 122 is exposed from the second contact hole 105. In this embodiment, the first insulating layer 101, the gate insulating layer 102, and the second insulating layer 103 are simultaneously etched, so that a third contact hole 106 corresponding to the data line 111 and a fifth contact hole 108 corresponding to the conductive portion 114 are formed in the first insulating layer 101, the gate insulating layer 102, and the second insulating layer 103, that is, the third contact hole 106 and the fifth contact hole 108 penetrate the first insulating layer 101 and the second insulating layer 103, the data line 111 is exposed from the third contact hole 106, and the conductive portion 114 is exposed from the fifth contact hole 108. Meanwhile, the second insulating layer 103 is etched, so that fourth contact holes 107 corresponding to the scan lines 131 are formed on the second insulating layer 103, and the scan lines 131 are exposed from the fourth contact holes 107. The material of the second insulating layer 103 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof. Since the second contact hole 105 needs to expose the source electrode 122, the third contact hole 106 needs to expose the data line 111, the fourth contact hole 107 needs to expose the scan line 131, and the fifth contact hole 10 needs to expose the conductive portion 114, the same mask can be used for etching the second contact hole 105, the third contact hole 106, the fourth contact hole 107, and the fifth contact hole 108. Of course, in other embodiments, before the metal oxide semiconductor layer 12 is covered, the lower half portion of the third contact hole 106 is also formed on the first insulating layer 101 when the first insulating layer 101 is etched, and the upper half portion of the third contact hole 106 is formed on the second insulating layer 103 when the second insulating layer 103 is etched, while the second contact hole 105 is aligned above and below the first contact hole 104, so that the same mask can be used when the first insulating layer 101 and the second insulating layer 103 are etched, thereby saving one mask.

As shown in fig. 5h, 6e and 7e, the transparent conductive layer 14 is formed over the second insulating layer 103, the transparent conductive layer 14 is etched, and the transparent conductive layer 14 is patterned to form the common electrode 141 and the second and

third connection portions

142 and 143 insulated from the common electrode 141. The common electrode 141 has a slit in a region corresponding to the pixel electrode 124, the second connecting portion 142 connects two portions of the data line 111 on both sides of the bottom gate 112, and the third connecting portion 143 electrically connects the conductive portion 114 with the scan line 131. Specifically, one end of the second connection portion 142 is electrically connected to the data line 111 through the third contact hole 106, and the other end of the second connection portion 142 is electrically connected to the source electrode 122 through the second contact hole 105, that is, the other end of the second connection portion 142 is indirectly electrically connected to the data line 111 through the source electrode 122. One end of the third connecting portion 143 is electrically connected to the scan line 131 through the fourth contact hole 107, and the other end of the third connecting portion 143 is electrically connected to the conductive portion 114 through the fifth contact hole 108. The transparent conductive layer 14 is made of Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), or the like. Of course, in other embodiments, the transparent conductive layer 14 may also be formed on the color film substrate 20 (fig. 10) without forming the common electrode 141, so that the array substrate may be suitable for a TN mode or VA mode display panel.

Preferably, the second connection portion 142 is located on a center line of the data line 111, i.e., the second connection portion 142 has a partial overlap with a projection of the data line 111 on the substrate 10. Although the second connection portion 142 and the projection of the active layer 121 on the substrate 10 also have a partial overlap, the top gate 132 is disposed between the active layer 121 and the second connection portion 142, and the top gate 132 can shield the data signal on the second connection portion 142, thereby effectively preventing the active layer 121 from being interfered by the data signal.

Preferably, the third connecting portion 143 and the conductive portion 114 are located on a central line of the scan line 131, that is, the third connecting portion 143 has a partial overlap with a projection of the scan line 131 on the substrate 10, the third connecting portion 143 has a partial overlap with a projection of the conductive portion 114 on the substrate 10, and the scan line 131 has a partial non-overlap with a projection of the conductive portion 114 on the substrate 10.

[ example two ]

Fig. 8 is a schematic plan view of the substrate and the first metal layer in the second embodiment of the present invention. Fig. 9 is a schematic cross-sectional view of the array substrate along the direction B-B in fig. 1 according to a second embodiment of the invention. As shown in fig. 8 and 9, the array substrate and the manufacturing method according to the second embodiment of the present invention are substantially the same as the array substrate and the manufacturing method according to the first embodiment (fig. 1 to 7e), except that in this embodiment, the first metal layer 11 further includes a first connection portion 113 located at the periphery of the bottom gate 112, and the first connection portion 113 connects two portions of the data line 111 located at two sides of the bottom gate 112, that is, in this embodiment, the first connection portion 113 replaces the second connection portion 142 in the first embodiment, so as to reduce the number of times of the opening process and simplify the manufacturing process.

The present embodiment further provides a manufacturing method of an array substrate, which is substantially the same as the manufacturing method in the first embodiment (fig. 1 to 7e), except that in the present embodiment, as shown in fig. 8, when the first metal layer 11 is etched, the first connection portion 113 around the bottom gate 112 is further formed, and the first connection portion 113 connects two portions of the data line 111 located at two sides of the bottom gate 112, that is, the first connection portion 113 replaces the second connection portion 142 in the first embodiment, so as to reduce the number of times of the opening process, and simplify the manufacturing process.

Compared with the first embodiment, in the present embodiment, the first connection portion 113 is formed by using the first metal layer 11, and the first connection portion 113 bypasses the bottom gate 112 and connects two portions of the data line 111 located at two sides of the bottom gate 112, so as to reduce the number of times of the opening process and simplify the manufacturing process.

It should be understood by those skilled in the art that the rest of the structure and the operation principle of the present embodiment are the same as those of the first embodiment, and are not described herein again.

Fig. 10 is a schematic cross-sectional view of a display panel according to the present invention. As shown in fig. 10, the present invention also provides a display panel including the array substrate, a counter substrate 20 disposed opposite to the array substrate, and a liquid crystal layer 30 disposed between the array substrate and the counter substrate 20. The opposite substrate 20 is provided with an upper polarizer 41, the array substrate is provided with a lower polarizer 42, and a transmission axis of the upper polarizer 41 is perpendicular to a transmission axis of the lower polarizer 42. In the liquid crystal layer 30, positive liquid crystal molecules (liquid crystal molecules having positive dielectric anisotropy) are used, and in an initial state, the positive liquid crystal molecules are in a lying posture, and the alignment direction of the positive liquid crystal molecules close to the counter substrate 20 is parallel to the alignment direction of the positive liquid crystal molecules 131 close to the array substrate. It is understood that the array substrate and the opposite substrate 20 are further provided with an alignment layer at a layer facing the liquid crystal layer 30, thereby aligning the positive liquid crystal molecules in the liquid crystal layer 30.

In this embodiment, the opposite substrate 20 is a color film substrate, a black matrix 21 and a color resistance layer 22 are disposed on the opposite substrate 20, the black matrix 21 corresponds to the scan line 131, the data line 111, the thin film transistor and the peripheral non-display region, and the black matrix 21 separates the color resistance layers 22. The color resist layer 22 includes color resist materials of three colors of red (R), green (G), and blue (B), and sub-pixels of the three colors of red (R), green (G), and blue (B) are correspondingly formed.

In this document, the terms of upper, lower, left, right, front, rear and the like are used to define the positions of the structures in the drawings and the positions of the structures relative to each other, and are only used for the sake of clarity and convenience in technical solution. It is to be understood that the use of the directional terms should not be taken to limit the scope of the claims. It is also to be understood that the terms "first" and "second," etc., are used herein for descriptive purposes only and are not to be construed as limiting in number or order.

Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. An array substrate, comprising:

a substrate (10);

the first metal layer (11) is arranged on the upper surface of the substrate (10), and the first metal layer (11) comprises a data line (111), a bottom grid (112) mutually insulated from the data line (111) and a conducting part (114) in conducting connection with the bottom grid (112);

a first insulating layer (101) disposed on the upper surface of the first metal layer (11), wherein the first insulating layer (101) covers the data line (111), the bottom gate (112) and the conductive portion (114);

a metal oxide semiconductor layer (12) disposed over the first insulating layer (101), the metal oxide semiconductor layer (12) including a conductor portion and a semiconductor portion, the semiconductor portion including an active layer (121), the conductor portion including a source electrode (122), a drain electrode (123), and a pixel electrode (124), the source electrode (122) and the drain electrode (123) being connected through the active layer (121), the source electrode (122) being electrically connected to the data line (111), the pixel electrode (124) being electrically connected to the drain electrode (123);

the gate electrode structure comprises a gate insulation layer (102) arranged above the metal oxide semiconductor layer (12) and a second metal layer (13) arranged above the gate insulation layer (102), wherein the second metal layer (13) comprises a scanning line (131) and a top gate (132), the projection of the active layer (121) on the substrate (10) corresponds to the overlapping area of the projection of the top gate (132) and the bottom gate (112) on the substrate (10), the overlapping area of the scanning line (131) and the active layer (121) serves as the top gate (132), and the conducting part (114) is in conductive connection with the scanning line (131).

2. The array substrate of claim 1, wherein the active layer (121), the source electrode (122), the drain electrode (123), the bottom gate (112), and the top gate (132) are all located on a center line of the data line (111).

3. The array substrate of claim 2, wherein the first metal layer (11) further comprises a first connection portion (113) at the periphery of the bottom gate (112), and the first connection portion (113) connects two portions of the data line (111) at two sides of the bottom gate (112).

4. The array substrate of claim 2, further comprising: the second insulating layer (103) is arranged above the second metal layer (13), the transparent conducting layer (14) is arranged above the second insulating layer (103), the transparent conducting layer (14) comprises a common electrode (141), and a slit is formed in the region, corresponding to the pixel electrode (124), of the common electrode (141).

5. The array substrate of claim 4, wherein the transparent conductive layer (14) further comprises a second connecting portion (142) insulated from the common electrode (141), the second connecting portion (142) connecting two portions of the data line (111) on two sides of the bottom gate (112); one end of the second connecting portion (142) is electrically connected with the data line (111), and the other end of the second connecting portion (142) is electrically connected with the source electrode (122).

6. The array substrate according to claim 4, wherein the transparent conductive layer (14) further comprises a third connecting portion (143) insulated from the common electrode (141), the third connecting portion (143) electrically connecting the conductive portion (114) and the scan line (131).

7. A manufacturing method of an array substrate is characterized by comprising the following steps:

providing a substrate (10);

forming a first metal layer (11) on the substrate (10), etching the first metal layer (11), and patterning the first metal layer (11) to form a data line (111), a bottom gate (112) insulated from the data line (111), and a conductive part (114) conductively connected with the bottom gate (112);

forming a first insulating layer (101) on the upper surface of the first metal layer (11) to cover the data line (111), the bottom gate (112), and the conductive portion (114);

forming a metal oxide semiconductor layer (12) above the first insulating layer (101), etching the metal oxide semiconductor layer (12), wherein the metal oxide semiconductor layer (12) is patterned to form an active layer (121), a source electrode (122), a drain electrode (123) and a pixel electrode (124), the source electrode (122) and the drain electrode (123) are connected through the active layer (121), the source electrode (122) is electrically connected with the data line (111), and the pixel electrode (124) is electrically connected with the drain electrode (123);

sequentially forming a gate insulating layer (102) and a second metal layer (13) above the metal oxide semiconductor layer (12), etching the second metal layer (13), wherein the second metal layer (13) is patterned to form a scanning line (131) and a top gate (132), the projection of the active layer (121) on the substrate (10) corresponds to the overlapping region of the projection of the top gate (132) and the bottom gate (112) on the substrate (10), the region where the scanning line (131) overlaps with the active layer (121) serves as the top gate (132), and the conductive part (114) is in conductive connection with the scanning line (131);

and conducting the metal oxide semiconductor layer (12) by using the second metal layer (13) as a shield, wherein the regions of the metal oxide semiconductor layer (12) corresponding to the source electrode (122), the drain electrode (123) and the pixel electrode (124) are made conductive, and the region of the metal oxide semiconductor layer (12) corresponding to the active layer (121) is kept as a semiconductor.

8. The array substrate of claim 7, wherein the active layer (121), the source electrode (122), the drain electrode (123), the bottom gate (112), and the top gate (132) are all located on a center line of the data line (111).

9. The method for manufacturing the array substrate according to claim 8, wherein when the first metal layer (11) is etched, a first connection portion (113) located at the periphery of the bottom gate (112) is further formed, and the first connection portion (113) connects two portions of the data line (111) located at two sides of the bottom gate (112).

10. The method for manufacturing the array substrate according to claim 8, further comprising:

forming a second insulating layer (103) above the second metal layer (13) and a transparent conductive layer (14) above the second insulating layer (103), etching the transparent conductive layer (14), wherein the transparent conductive layer (14) is patterned to form a common electrode (141) and a second connecting portion (142) and a third connecting portion (143) which are insulated from the common electrode (141), the common electrode (141) has a slit in a region corresponding to the pixel electrode (124), the second connecting portion (142) connects two portions of the data line (111) on both sides of the bottom gate (112), and the third connecting portion (143) electrically connects the conductive portion (114) and the scan line (131).