CN114660862B - Array substrate, manufacturing method and display panel - Google Patents

Abstract

The application discloses an array substrate, a manufacturing method and a display panel, wherein the array substrate comprises the following components: a substrate; a data line and a light shielding portion disposed on the substrate; a first insulating layer covering the data lines and the light shielding portions; an active layer, a source electrode, a drain electrode and a pixel electrode disposed on the first insulating layer; the grid insulating layer is arranged on the first insulating layer, the scanning line and the grid are arranged on the grid insulating layer, and the projection of the active layer on the substrate corresponds to the overlapping area of the projection of the scanning line and the shading part on the substrate. The scanning lines and the shading parts are respectively arranged on the upper side and the lower side of the active layer, so that the scanning lines and the shading parts can respectively shade external environment light and backlight for the active layer, and the scanning lines and the shading parts can also be used as shielding electrodes so as to prevent the active layer from being interfered by data signals, and greatly simplify the manufacturing process; in addition, the active layer, the source electrode, the drain electrode and the pixel electrode are all made of metal oxide semiconductor layers, so that the manufacturing process is further simplified, and the aperture opening ratio of the pixel can be increased.

Description

Array substrate, manufacturing method and display panel

Technical Field

The application relates to the technical field of displays, in particular to an array substrate, a manufacturing method and a display panel.

Background

With the development of display technology, light and thin display panels are popular with consumers, especially light and thin display panels (liquid crystal display, LCD).

The conventional display device includes a thin film transistor array Substrate (abbreviated as array Substrate Thin Film Transistor Array Substrate, TFT Array Substrate), a color film Substrate (Color Filter Substrate, CF Substrate) and liquid crystal molecules filled between the thin film transistor array Substrate and the color film Substrate, and when the display device is in operation, a driving voltage is respectively applied to a pixel electrode of the thin film transistor array Substrate and a common electrode of the color film Substrate or a driving voltage is respectively applied to the common electrode and the pixel electrode of the thin film transistor array Substrate, so as to control a rotation direction of the liquid crystal molecules between the two substrates, and refract a backlight provided by a backlight module of the display device, thereby displaying a picture.

The oxide Thin Film Transistor (TFT) in the prior art has the advantages of excellent electrical property, large-area manufacturing uniformity, low manufacturing cost and the like, and is expected to be applied to various flat panel display products. When the bottom gate type TFT grid electrode is applied to an LCD display panel, the bottom gate type TFT grid electrode can be used as a shading layer, and the degradation of device characteristics caused by illumination of an oxide active layer can be avoided. Commonly used bottom gate oxide TFTs are mainly of the back channel etch type (BCE) and the etch barrier type (ESL). Wherein the back channel etch type TFT is simpler to fabricate but is subject to ambient light. The etching barrier type TFT is required to consider the alignment of the grid electrode, the source electrode and the drain electrode and the ESL layer, so that the length of the grid electrode cannot be shortened, the overlapping amount of the grid electrode and the source electrode and the drain electrode is larger, and the parasitic capacitance of the device is larger. But the ESL layer can effectively protect the active layer, so that the characteristics and the stability of the TFT device are better. The channel protection layer of the etching barrier layer type TFT is usually made of silicon oxide (SiOx) or silicon nitride (SiNx), and an independent etching process is needed when the etching barrier layer type TFT is used for manufacturing the channel protection layer (ESL), and the patterning is realized after film forming, photoetching, etching and photoresist removing cleaning, so that the process steps are complex, the overlapping area of a grid electrode and a source electrode and a drain electrode region determines the parasitic capacitance of the device, the overlapping area is determined by the alignment of the ESL and the grid electrode, and the parasitic capacitance is difficult to be small.

In addition, since the active layer in the bottom gate TFT is also susceptible to the data signal, the gate electrode and the active layer are usually disposed so as to avoid the data line in the related art, but such a disposition results in a significant reduction in the aperture ratio of the pixel. Further, a shielding electrode is additionally arranged between the active layer and the data line, and the arrangement of the shielding electrode and the active protection layer greatly increase the complexity of the manufacturing process, so that the cost is increased.

Disclosure of Invention

In order to overcome the defects and shortcomings in the prior art, the application aims to provide an array substrate, a manufacturing method and a display panel, so as to solve the problems of complex manufacturing process and low aperture opening ratio of the array substrate in the prior art.

The aim of the application is achieved by the following technical scheme:

the application provides an array substrate, comprising:

a substrate;

the first metal layer is arranged on the upper surface of the substrate and comprises a data line and a shading part mutually insulated from the data line, and the shading part is positioned on the central line of the data line;

the first insulating layer is arranged on the upper surface of the first metal layer and covers the data line and the shading part;

a metal oxide semiconductor layer disposed over the first insulating layer, the metal oxide semiconductor layer including a conductor portion and a semiconductor portion, the semiconductor portion including an active layer, the conductor portion including a source electrode, a drain electrode, and a pixel electrode, the source electrode and the drain electrode being connected through the active layer, the source electrode being conductively connected to the data line, the pixel electrode being conductively connected to the drain electrode;

the second metal layer comprises a scanning line and a grid electrode, wherein the projection of the active layer on the substrate corresponds to the overlapping area of the scanning line and the projection of the shading part on the substrate, and the overlapping area of the scanning line and the active layer is used as the grid electrode.

Further, the first metal layer further comprises a first connecting part located at the periphery of the light shielding part, and the first connecting part connects the two parts of the data line located above and below the light shielding part.

Further, the array substrate further includes:

the transparent conductive layer comprises a common electrode, and a slit is arranged in the area of the common electrode corresponding to the pixel electrode.

Further, the transparent conductive layer further includes a second connection portion insulated from the common electrode, the second connection portion connecting the data line to the upper and lower portions of the light shielding portion.

Further, one end of the second connection part is in conductive connection with the data line, and the other end of the second connection part is in conductive connection with the source electrode.

Further, the source electrode and the drain electrode are both located on a center line of the data line.

The application also provides a manufacturing method of the array substrate, which comprises the following steps:

providing a substrate;

forming a first metal layer on the substrate, etching the first metal layer, patterning the first metal layer to form a data line and a shading part mutually insulated from the data line, wherein the shading part is positioned on a central line of the data line;

forming a first insulating layer on an upper surface of the first metal layer to cover the data line and the light shielding portion;

forming a metal oxide semiconductor layer over the first insulating layer, etching the metal oxide semiconductor layer, patterning the metal oxide semiconductor layer to form an active layer, a source electrode, a drain electrode, and a pixel electrode, the source electrode and the drain electrode being connected through the active layer, the source electrode being conductively connected to the data line, the pixel electrode being conductively connected to the drain electrode;

forming a gate insulating layer and a second metal layer above the metal oxide semiconductor layer in sequence, etching the second metal layer, patterning the second metal layer to form a scanning line and a gate, wherein the projection of the active layer on the substrate corresponds to an overlapping area of the scanning line and the projection of the shading part on the substrate, and the overlapping area of the scanning line and the active layer is used as the gate;

and conducting a conductive treatment on the metal oxide semiconductor layer by taking the second metal layer as a shielding part, wherein the regions of the metal oxide semiconductor layer corresponding to the source electrode, the drain electrode and the pixel electrode are conducted, and the region of the metal oxide semiconductor layer corresponding to the active layer is kept as a semiconductor.

Further, when the first metal layer is etched, a first connection portion is formed at the periphery of the light shielding portion, and the first connection portion connects two portions of the data line located above and below the light shielding portion.

Further, the manufacturing method further comprises the following steps: and forming a second insulating layer above the second metal layer and forming a transparent conductive layer above the second insulating layer, etching the transparent conductive layer, patterning the transparent conductive layer to form a common electrode and a second connecting part mutually insulated from the common electrode, wherein a slit is formed in a region of the common electrode corresponding to the pixel electrode, and the second connecting part connects two parts of the data line above and below the light shielding part.

The application also provides a display panel which comprises the array substrate, a counter substrate arranged opposite to the array substrate and a liquid crystal layer arranged between the array substrate and the counter substrate.

The application has the beneficial effects that: the scanning line and the shading part are respectively arranged on the upper side and the lower side of the active layer, so that the scanning line and the shading part can respectively shade external environment light and backlight for the active layer, the shading layer is not required to be additionally arranged, the problem of characteristic degradation of a TFT device caused by illumination of the active layer can be avoided, the scanning line and the shading part can also be used as shielding electrodes, the shielding electrodes are not required to be additionally arranged, the active layer is also prevented from being interfered by data signals, and the manufacturing process is greatly simplified; in addition, the active layer, the source electrode, the drain electrode and the pixel electrode are all made of metal oxide semiconductor layers, so that the manufacturing process is further simplified, and the aperture opening ratio of the pixel can be increased.

Drawings

FIG. 1 is a schematic plan view of an array substrate according to a first embodiment of the application;

FIG. 2 is a schematic cross-sectional view of an array substrate along the direction A-A in FIG. 1 according to a first embodiment of the present application;

FIG. 3 is a schematic cross-sectional view of an array substrate along the direction B-B in FIG. 1 according to a first embodiment of the present application;

FIGS. 4a-4h are schematic diagrams illustrating a method for fabricating an array substrate along the direction B-B in FIG. 1 according to a first embodiment of the present application;

FIGS. 5a-5e are schematic plan views illustrating a method for fabricating an array substrate according to a first embodiment of the application;

FIG. 6 is a schematic plan view of a substrate and a first metal layer according to a second embodiment of the present application;

FIG. 7 is a schematic cross-sectional view of an array substrate along the direction B-B in FIG. 1 according to a second embodiment of the present application;

fig. 8 is a schematic cross-sectional structure of a display panel according to the present application.

Detailed Description

In order to further describe the technical means and effects adopted by the application to achieve the preset aim, the following detailed description is given of the specific implementation, structure, characteristics and effects of the array substrate, the manufacturing method, the display panel according to the application by combining the accompanying drawings and the preferred embodiment, wherein:

example one

Fig. 1 is a schematic plan view of an array substrate according to an embodiment of the present application, fig. 2 is a schematic sectional view of the array substrate according to the embodiment of the present application along the direction A-A in fig. 1, fig. 3 is a schematic sectional view of the array substrate according to the embodiment of the present application along the direction B-B in fig. 1, fig. 4a-4h are schematic plan views of a method for manufacturing the array substrate according to the embodiment of the present application along the direction B-B in fig. 1, and fig. 5a-5e are schematic plan views of a method for manufacturing the array substrate according to the embodiment of the present application.

As shown in fig. 1 to 3, an array substrate according to a first embodiment of the present application includes:

the substrate 10, the substrate 10 may be made of glass, quartz, silicon, acrylic or polycarbonate, and the substrate 10 may also be a flexible substrate, with suitable materials for the flexible substrate including, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinylchloride (PVC), polyethylene terephthalate (PET), or combinations thereof.

The first metal layer 11 is disposed on the upper surface of the substrate 10, the first metal layer 11 includes a data line 111 and a light shielding portion 112 insulated from the data line 111, the light shielding portion 112 is disposed on a center line of the data line 111, that is, the light shielding portion 112 is disposed on the same line as the data line 111, and a center line of the data line 111 is parallel to a length direction of the data line 111. The first metal layer 11 may be made of a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or the like, or a combination of the above metals such as Al/Mo, cu/Mo, or the like.

The first insulating layer 101 is provided on the upper surface of the first metal layer 11, and the first insulating layer 101 covers the data line 111 and the light shielding portion 112. In this embodiment, the first insulating layer 101 is provided with the first contact hole 104 (fig. 4 b) at a position corresponding to the data line 111, and the data line 111 is exposed from the first contact hole 104. The material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

The metal oxide semiconductor layer 12 (fig. 5 b) is disposed over the first insulating layer 101, and preferably the metal oxide semiconductor layer 12 is disposed directly on the upper surface of the first insulating layer 101. The metal oxide semiconductor layer 12 includes a conductor portion including an active layer 121, a drain electrode 123, and a pixel electrode 124, the source electrode 122 and the drain electrode 123 are connected through the active layer 121, the source electrode 122 is electrically connected to the data line 111 through the first contact hole 104, and the pixel electrode 124 is directly electrically connected to the drain electrode 123.

Specifically, the metal oxide semiconductor layer 12 may be subjected to a conductive treatment, for example, a plasma treatment, such as ion bombardment, hydrogen (H2) doping, helium (He) doping, or argon (Ar) doping, to form a conductive source electrode 122, drain electrode 123, and pixel electrode 124 in a partial region of the metal oxide semiconductor layer 12, but the active layer 121 is not conductive and remains as a semiconductor. Alternatively, the metal oxide semiconductor layer 12 may be subjected to a conductive treatment using ultraviolet light. The metal oxide semiconductor layer 12 is preferably made of a transparent metal oxide semiconductor material such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium Gallium Zinc Oxide (IGZO), or Indium Gallium Zinc Tin Oxide (IGZTO). By forming the active layer 121, the source electrode 122, the drain electrode 123, and the pixel electrode 124 of the metal oxide semiconductor layer 12, the fabrication process can be simplified without using an additional process to fabricate the source electrode 122, the drain electrode 123, and the pixel electrode 124. The metal oxide semiconductor layer 12 is transparent, so that the source electrode 122, the drain electrode 123 and the pixel electrode 124 are transparent, and the aperture ratio of the pixel can be increased.

Preferably, both the source electrode 122 and the drain electrode 123 are located on the center line of the data line 111, so that the lengths of the source electrode 122 and the drain electrode 123 can be reduced. Since the resistivity of the metal oxide semiconductor layer 12 is relatively large with respect to the resistivity of the metal, decreasing the lengths of the source electrode 122 and the drain electrode 123 may increase the signal conductivity.

The gate insulating layer 102 disposed over the metal oxide semiconductor layer 12 and the second metal layer 13 disposed over the gate insulating layer 102 (fig. 5 c), preferably, the gate insulating layer 102 is disposed directly on the upper surface of the metal oxide semiconductor layer 12 and the second metal layer 13 is disposed directly on the upper surface of the gate insulating layer 102. The second metal layer 13 includes a scan line 131 and a gate electrode 132, and preferably, the scan line 131 and the data line 111 extend in directions perpendicular to each other, and a region where the scan line 131 and the active layer 121 overlap is used as the gate electrode 132. The projection of the active layer 121 on the substrate 10 corresponds to an overlapping area of the scan line 131 and the light shielding part 112 projected on the substrate 10, and the size of the active layer 121 is smaller than or equal to the size of the overlapping area of the scan line 131 and the light shielding part 112 projected on the substrate 10. By arranging the scanning line 131 and the light shielding part 112 on the upper and lower sides of the active layer 121 respectively, the scanning line 131 and the light shielding part 112 can shield external environment light and backlight for the active layer 121 respectively, no additional light shielding layer is needed, the problem of TFT device characteristic degradation of the active layer 121 caused by illumination can be avoided, the scanning line 131 and the light shielding part 112 can also be used as shielding electrodes, no additional shielding electrode is needed, the active layer 121 can be prevented from being interfered by data signals, and the manufacturing process is greatly simplified. The material of the gate insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both. The second metal layer 13 may employ a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al/Mo, cu/Mo, etc.

In this embodiment, the array substrate further includes a second insulating layer 103 disposed above the second metal layer 13 and a transparent conductive layer 14 disposed above the second insulating layer 103, where the transparent conductive layer 14 includes a common electrode 141, and a region of the common electrode 141 corresponding to the pixel electrode 124 has a slit. So that the array substrate can be applied to a display panel of a fringe field Switching mode (Fringe Field Switching, FFS) or an In-Plane Switching mode (IPS). Of course, in other embodiments, the common electrode 141 may be disposed on the color film substrate 20 (fig. 8) instead of the common electrode 141, so that the array substrate may be suitable for a display panel of a TN mode or a VA mode, and other descriptions of the TN mode and the VA mode refer to the prior art and are not repeated here. The material of the second insulating layer 103 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both. The material of the transparent conductive layer 14 is Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), or the like.

Further, the transparent conductive layer 14 further includes a second connection part 142 insulated from the common electrode 141, and the second connection part 142 connects the two parts of the data line 111 above and below the light shielding part 112. Preferably, the second connection part 142 is located on the center line of the data line 111, i.e., the second connection part 142 has a partial overlap with the projection of the data line 111 on the substrate 10. Although the projection of the second connection portion 142 and the active layer 121 on the substrate 10 also has partial overlap, the scan line 131 is disposed between the active layer 121 and the second connection portion 142, and the scan line 131 can shield the data signal on the second connection portion 142, so as to effectively avoid the active layer 121 from being interfered by the data signal.

In this embodiment, the second insulating layer 103 is provided with a second contact hole 105 corresponding to the source electrode 122, and preferably, the second contact hole 105 is aligned vertically with the first contact hole 104, and one end of the second connection portion 142 is electrically connected to the source electrode 122 through the second contact hole 105, that is, one end of the second connection portion 142 is indirectly electrically connected to the data line 111 through the source electrode 122. The first insulating layer 101 and the second insulating layer 103 are provided with third contact holes 106 corresponding to the data lines 111, that is, the third contact holes 106 penetrate through the first insulating layer 101 and the second insulating layer 103, so that the other ends of the second connection portions 142 are electrically connected to the data lines 111 through the third contact holes 106.

As shown in fig. 4a to 5e, the present embodiment further provides a method for manufacturing an array substrate, where the method is used for manufacturing the array substrate, and the method includes:

as shown in fig. 4a and 5a, a substrate 10 is provided, the substrate 10 may be made of glass, quartz, silicon, acrylic or polycarbonate, etc., and the substrate 10 may also be a flexible substrate, suitable materials for the flexible substrate including, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinylchloride (PVC), polyethylene terephthalate (PET), or a combination thereof.

The first metal layer 11 is formed on the substrate 10, the first metal layer 11 is etched, the first metal layer 11 is patterned to form the data line 111 and the light shielding portion 112 insulated from the data line 111, the light shielding portion 112 is located on the central line of the data line 111, that is, the light shielding portion 112 is located on the same line as the data line 111, and the central line of the data line 111 is parallel to the length direction of the data line 111. The first metal layer 11 may be made of a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or the like, or a combination of the above metals such as Al/Mo, cu/Mo, or the like.

As shown in fig. 4b, a first insulating layer 101 covering the data line 111 and the light shielding portion 112 is formed on the upper surface of the first metal layer 11. The first insulating layer 101 is etched such that the first insulating layer 101 is provided with a first contact hole 104 at a position corresponding to the data line 111, and the data line 111 is exposed from the first contact hole 104. The material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

As shown in fig. 4c, 4d and 5b, the metal oxide semiconductor layer 12 is formed over the first insulating layer 101, the metal oxide semiconductor layer 12 is etched, the metal oxide semiconductor layer 12 is patterned to form the active layer 121, the source electrode 122, the drain electrode 123 and the pixel electrode 124, the source electrode 122 and the drain electrode 123 are connected through the active layer 121, the source electrode 122 is electrically connected with the data line 111 through the first contact hole 104, and the pixel electrode 124 is directly electrically connected with the drain electrode 123. Among them, the metal oxide semiconductor layer 12 is preferably made of a transparent metal oxide semiconductor material such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium Gallium Zinc Oxide (IGZO), or Indium Gallium Zinc Tin Oxide (IGZTO). By forming the active layer 121, the source electrode 122, the drain electrode 123, and the pixel electrode 124 of the metal oxide semiconductor layer 12, the fabrication process can be simplified without using an additional process to fabricate the source electrode 122, the drain electrode 123, and the pixel electrode 124. The metal oxide semiconductor layer 12 is transparent, so that the source electrode 122, the drain electrode 123 and the pixel electrode 124 are transparent, and the aperture ratio of the pixel can be increased.

Preferably, both the source electrode 122 and the drain electrode 123 are located on the center line of the data line 111, so that the lengths of the source electrode 122 and the drain electrode 123 can be reduced. Since the resistivity of the metal oxide semiconductor layer 12 is relatively large with respect to the resistivity of the metal, decreasing the lengths of the source electrode 122 and the drain electrode 123 may increase the signal conductivity.

As shown in fig. 4e and 5c, the gate insulating layer 102 and the second metal layer 13 are sequentially formed over the metal oxide semiconductor layer 12, and preferably, the gate insulating layer 102 is directly disposed on the upper surface of the metal oxide semiconductor layer 12, and the second metal layer 13 is directly disposed on the upper surface of the gate insulating layer 102. The second metal layer 13 is etched, and the second metal layer 13 is patterned to form a scan line 131 and a gate electrode 132, and preferably, the scan line 131 and the data line 111 extend in directions perpendicular to each other, and a region where the scan line 131 and the active layer 121 overlap is used as the gate electrode 132. The projection of the active layer 121 on the substrate 10 corresponds to an overlapping area of the scan line 131 and the light shielding part 112 projected on the substrate 10, and the size of the active layer 121 is smaller than or equal to the size of the overlapping area of the scan line 131 and the light shielding part 112 projected on the substrate 10. By arranging the scanning line 131 and the light shielding part 112 on the upper and lower sides of the active layer 121 respectively, the scanning line 131 and the light shielding part 112 can shield external environment light and backlight for the active layer 121 respectively, no additional light shielding layer is needed, the problem of TFT device characteristic degradation of the active layer 121 caused by illumination can be avoided, the scanning line 131 and the light shielding part 112 can also be used as shielding electrodes, no additional shielding electrode is needed, the active layer 121 can be prevented from being interfered by data signals, and the manufacturing process is greatly simplified. The material of the gate insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both. The second metal layer 13 may employ a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al/Mo, cu/Mo, etc.

In this embodiment, the second metal layer 13 is used as a mask to etch the gate insulating layer 102, and the projection of the gate insulating layer 102 and the data line 111 on the substrate 10 overlap, so that the source electrode 122, the drain electrode 123 and the pixel electrode 124 are exposed.

As shown in fig. 4f and 5d, the second metal layer 13 is used as a mask to perform a conductive treatment on the metal oxide semiconductor layer 12, the regions of the metal oxide semiconductor layer 12 corresponding to the source electrode 122, the drain electrode 123 and the pixel electrode 124 are conductive, and the region of the metal oxide semiconductor layer 12 corresponding to the active layer 121 is kept as a semiconductor. Specifically, the exposed region of the metal oxide semiconductor layer 12 may be subjected to a plasma treatment, and the exposed region of the metal oxide semiconductor layer 12 may be subjected to a plasma treatment, such as ion bombardment, hydrogen (H2) doping, helium (He) doping, or argon (Ar) doping, to thereby form a conductor, that is, to form a conductor for the source electrode 122, the drain electrode 123, and the pixel electrode 124. Of course, in other embodiments, ultraviolet light may be used to conduct the conductive treatment on the metal oxide semiconductor layer 12, so that the etching of the gate insulating layer 102 is not required, thereby reducing one etching process. By using the second metal layer 13 as a shield, the gate electrode 132 is vertically aligned with the active layer 121 and overlapped with the source electrode 122 and the drain electrode 123 by a small amount, so that parasitic capacitance is reduced.

As shown in fig. 4g, a second insulating layer 103 is formed over the second metal layer 13, the second insulating layer 103 is etched, and a second contact hole 105 is formed in a region corresponding to the source electrode 122 in the second insulating layer 103, preferably, the second contact hole 105 is aligned up and down with the first contact hole 104. In this embodiment, the first insulating layer 101 and the second insulating layer 103 are etched at the same time, so that the first insulating layer 101 and the second insulating layer 103 are formed with the third contact hole 106 corresponding to the data line 111, that is, the third contact hole 106 penetrates the first insulating layer 101 and the second insulating layer 103. The material of the second insulating layer 103 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both. Of course, in other embodiments, before the metal oxide semiconductor layer 12 is covered, when the first insulating layer 101 is etched, a lower half portion of the third contact hole 106 is formed on the first insulating layer 101, and when the second insulating layer 103 is etched, an upper half portion of the third contact hole 106 is formed on the second insulating layer 103, and the second contact hole 105 is aligned with the first contact hole 104, so that the same mask plate can be used when the first insulating layer 101 and the second insulating layer 103 are etched, so that one mask plate can be saved.

As shown in fig. 4h and 5e, a transparent conductive layer 14 is formed over the second insulating layer 103, the transparent conductive layer 14 is etched, and the transparent conductive layer 14 is patterned to form a common electrode 141 and a second connection portion 142 insulated from the common electrode 141. The common electrode 141 has slits in a region corresponding to the pixel electrode 124, and the second connection portion 142 connects the two portions of the data line 111 above and below the light shielding portion 112. Specifically, one end of the second connection part 142 is electrically connected to the data line 111 through the third contact hole 106, and the other end of the second connection part 142 is electrically connected to the source electrode 122 through the second contact hole 105, i.e., the other end of the second connection part 142 is indirectly electrically connected to the data line 111 through the source electrode 122. The material of the transparent conductive layer 14 is Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), or the like. Of course, in other embodiments, the transparent conductive layer 14 may not be formed with the common electrode 141, but the common electrode 141 is disposed on the color film substrate 20 (fig. 8), so that the array substrate may be suitable for a display panel of a TN mode or a VA mode, and for other description of the TN mode and the VA mode, please refer to the prior art, and no further description is given here.

Preferably, the second connection part 142 is located on the center line of the data line 111, i.e., the second connection part 142 has a partial overlap with the projection of the data line 111 on the substrate 10. Although the projection of the second connection portion 142 and the active layer 121 on the substrate 10 also has partial overlap, the scan line 131 is disposed between the active layer 121 and the second connection portion 142, and the scan line 131 can shield the data signal on the second connection portion 142, so as to effectively avoid the active layer 121 from being interfered by the data signal.

Example two

Fig. 6 is a schematic plan view of a substrate and a first metal layer in the second embodiment of the present application, and fig. 7 is a schematic cross-sectional view of an array substrate along the direction B-B in fig. 1 in the second embodiment of the present application. As shown in fig. 6 and 7, the array substrate and the manufacturing method according to the second embodiment of the present application are substantially the same as those of the first embodiment (fig. 1 to 5 e), and the difference is that in the present embodiment, the first metal layer 11 further includes a first connection portion 113 located at the periphery of the light shielding portion 112, and the first connection portion 113 connects two portions of the data line 111 located above and below the light shielding portion 112, that is, the first connection portion 113 replaces the second connection portion 142 in the first embodiment, so as to reduce the number of times of the hole forming process, and simplify the manufacturing process.

The present embodiment also provides a method for manufacturing an array substrate, which is substantially the same as the method in the first embodiment (fig. 1 to 5 e), and is different in that, in the present embodiment, as shown in fig. 7, when the first metal layer 11 is etched, a first connection portion 113 is further formed at the periphery of the light shielding portion 112, and the first connection portion 113 connects two portions of the data line 111 located above and below the light shielding portion 112, that is, the first connection portion 113 replaces the second connection portion 142 in the first embodiment, so as to reduce the number of times of the hole opening process, and simplify the manufacturing process.

Compared with the first embodiment, the first connection portion 113 is formed by using the first metal layer 11, and the first connection portion 113 bypasses the light shielding portion 112 and connects the two portions of the data line 111 above and below the light shielding portion 112, so that the number of times of the opening process is reduced, and the manufacturing process is simplified, but since the first connection portion 113 is of an opaque structure, the aperture ratio of the pixel is reduced.

Those skilled in the art will understand that the other structures and working principles of the present embodiment are the same as those of the first embodiment, and will not be described herein.

Fig. 8 is a schematic cross-sectional structure of a display panel according to the present application. As shown in fig. 8, the present application further provides a display panel, which includes the above-mentioned array substrate, a counter substrate 20 disposed opposite to the array substrate, and a liquid crystal layer 30 disposed between the array substrate and the counter substrate 20. An upper polaroid 41 is arranged on the opposite substrate 20, a lower polaroid 42 is arranged on the array substrate, and the transmission axis of the upper polaroid 41 is mutually perpendicular to the transmission axis of the lower polaroid 42. In the initial state, the positive liquid crystal molecules are in a lying posture, and the alignment direction of the positive liquid crystal molecules near the opposite substrate 20 is parallel to the alignment direction of the positive liquid crystal molecules 131 near the array substrate. It is understood that the array substrate and the counter substrate 20 are further provided with an alignment layer at a layer facing the liquid crystal layer 30, thereby aligning the positive liquid crystal molecules in the liquid crystal layer 30.

In this embodiment, the opposite substrate 20 is a color film substrate, and the opposite substrate 20 is provided with a black matrix 21 and a color resist layer 22, wherein the black matrix 21 corresponds to the scan lines 131, the data lines 111, the thin film transistors and the peripheral non-display area, and the black matrix 21 separates the plurality of color resist layers 22. The color resist layer 22 includes red (R), green (G), and blue (B) color resist materials, and corresponds to the sub-pixels forming the three colors red (R), green (G), and blue (B).

In this document, terms such as up, down, left, right, front, rear, etc. are defined by the positions of the structures in the drawings and the positions of the structures with respect to each other, for the sake of clarity and convenience in expressing the technical solution. It should be understood that the use of such orientation terms should not limit the scope of the claimed application. It should also be understood that the terms "first" and "second," etc., as used herein, are used merely for distinguishing between names and not for limiting the number and order.

The present application is not limited to the preferred embodiments, but is capable of modification and variation in detail, and other modifications and variations can be made by those skilled in the art without departing from the scope of the present application.

Claims (7)

1. An array substrate, characterized by comprising:

a substrate (10);

the first metal layer (11) is arranged on the upper surface of the substrate (10), the first metal layer (11) comprises a data line (111) and a shading part (112) insulated from the data line (111), and the shading part (112) is positioned on the central line of the data line (111);

a first insulating layer (101) provided on the upper surface of the first metal layer (11), the first insulating layer (101) covering the data line (111) and the light shielding portion (112);

a metal oxide semiconductor layer (12) disposed above the first insulating layer (101), the metal oxide semiconductor layer (12) including a conductor portion and a semiconductor portion, the semiconductor portion including an active layer (121), the conductor portion including a source electrode (122), a drain electrode (123), and a pixel electrode (124), the source electrode (122) and the drain electrode (123) being connected through the active layer (121), the source electrode (122) being conductively connected to the data line (111), the pixel electrode (124) being conductively connected to the drain electrode (123);

a gate insulating layer (102) disposed above the metal oxide semiconductor layer (12) and a second metal layer (13) disposed above the gate insulating layer (102), wherein the second metal layer (13) includes a scan line (131) and a gate electrode (132), a projection of the active layer (121) on the substrate (10) corresponds to an overlapping region of the scan line (131) and a projection of the light shielding portion (112) on the substrate (10), and a region of the scan line (131) overlapping with the active layer (121) serves as the gate electrode (132);

the transparent conductive layer (14) is arranged on the second insulating layer (103) above the second metal layer (13), the transparent conductive layer (14) comprises a second connecting part (142), and the second connecting part (142) connects the two parts of the data line (111) above and below the light shielding part (112).

2. The array substrate of claim 1, further comprising:

the transparent conductive layer (14) further includes a common electrode (141) insulated from the second connection portion (142), and a region of the common electrode (141) corresponding to the pixel electrode (124) has a slit.

3. The array substrate of claim 1, wherein one end of the second connection part (142) is electrically connected to the data line (111), and the other end of the second connection part (142) is electrically connected to the source electrode (122).

4. The array substrate according to claim 1, wherein the source electrode (122) and the drain electrode (123) are located on a center line of the data line (111).

5. The manufacturing method of the array substrate is characterized by comprising the following steps of:

providing a substrate (10);

forming a first metal layer (11) on the substrate (10), etching the first metal layer (11), patterning the first metal layer (11) to form a data line (111) and a light shielding part (112) insulated from the data line (111), wherein the light shielding part (112) is positioned on a central line of the data line (111);

forming a first insulating layer (101) on the upper surface of the first metal layer (11) to cover the data line (111) and the light shielding portion (112);

forming a metal oxide semiconductor layer (12) over the first insulating layer (101), etching the metal oxide semiconductor layer (12), patterning the metal oxide semiconductor layer (12) to form an active layer (121), a source electrode (122), a drain electrode (123), and a pixel electrode (124), the source electrode (122) and the drain electrode (123) being connected through the active layer (121), the source electrode (122) being conductively connected to the data line (111), the pixel electrode (124) being conductively connected to the drain electrode (123);

sequentially forming a gate insulating layer (102) and a second metal layer (13) above the metal oxide semiconductor layer (12), etching the second metal layer (13), patterning the second metal layer (13) to form a scanning line (131) and a gate (132), wherein the projection of the active layer (121) on the substrate (10) corresponds to the overlapping area of the scanning line (131) and the projection of the light shielding part (112) on the substrate (10), and the overlapping area of the scanning line (131) and the active layer (121) is used as the gate (132);

conducting the metal oxide semiconductor layer (12) with the second metal layer (13) as a shield, wherein the metal oxide semiconductor layer (12) is conducted to the areas corresponding to the source electrode (122), the drain electrode (123) and the pixel electrode (124), and the metal oxide semiconductor layer (12) is kept as a semiconductor in the areas corresponding to the active layer (121);

a second insulating layer (103) is formed above the second metal layer (13), a transparent conductive layer (14) is formed above the second insulating layer (103), the transparent conductive layer (14) is etched, the transparent conductive layer (14) is patterned to form a second connecting portion (142), and the second connecting portion (142) connects two parts of the data line (111) above and below the light shielding portion (112).

6. The method for manufacturing an array substrate according to claim 5, further comprising:

when the transparent conductive layer (14) is etched, the transparent conductive layer (14) further forms a common electrode (141) insulated from the second connection portion (142), and a region of the common electrode (141) corresponding to the pixel electrode (124) has a slit.

7. A display panel comprising an array substrate according to any one of claims 1 to 4, a counter substrate (20) arranged opposite to the array substrate, and a liquid crystal layer (30) arranged between the array substrate and the counter substrate (20).