CN113690257A - Array substrate, manufacturing method thereof and display panel - Google Patents

Array substrate, manufacturing method thereof and display panel Download PDF

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Publication number
CN113690257A
CN113690257A CN202110991228.1A CN202110991228A CN113690257A CN 113690257 A CN113690257 A CN 113690257A CN 202110991228 A CN202110991228 A CN 202110991228A CN 113690257 A CN113690257 A CN 113690257A
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layer
insulating layer
electrode
metal layer
transparent conductive
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CN113690257B (en
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杨珊珊
井晓静
王影影
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InfoVision Optoelectronics Kunshan Co Ltd
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InfoVision Optoelectronics Kunshan Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

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  • Physics & Mathematics (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Crystallography & Structural Chemistry (AREA)
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  • Optics & Photonics (AREA)
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Abstract

The invention discloses an array substrate, a manufacturing method thereof and a display panel, wherein the array substrate comprises: a substrate; a first metal layer disposed on the substrate, the first metal layer including a source electrode; the first insulating layer covers the source electrode, and a through hole is formed in the position, corresponding to the source electrode, of the first insulating layer; a first transparent conductive layer disposed on the first insulating layer, the first transparent conductive layer including a pixel electrode; a second metal layer arranged on the first insulating layer and the pixel electrode, wherein the second metal layer comprises a drain electrode; the semiconductor layer is arranged on the drain electrode and is filled in the through hole to electrically connect the source electrode and the drain electrode; a second insulating layer covering the pixel electrode and the semiconductor layer; a gate electrode disposed on the second insulating layer; a third insulating layer covering the gate electrode; and a second transparent conductive layer disposed on the third insulating layer, the second transparent conductive layer including a common electrode. The array substrate provided by the invention not only reduces the power consumption, but also avoids the influence on the conductivity of the semiconductor layer after light irradiates the semiconductor layer.

Description

Array substrate, manufacturing method thereof and display panel
Technical Field
The invention relates to the technical field of displays, in particular to an array substrate, a manufacturing method thereof and a display panel.
Background
Currently, a Thin Film Transistor (TFT) is required to be miniaturized as a component of a display panel and to provide a display device with sufficient electrical driving capability. For the conventional lateral channel structure TFT device, to reduce the size, the channel length must be reduced. However, due to the limitation of photolithography tools in the display panel fabrication process, the channel length is difficult to shrink to submicron level. Therefore, the charging capacity of the pixel is improved only by increasing the width of the channel; and the high PPI product has limited pixel size, so that the channel width cannot be increased, further the product is insufficiently charged, and various display problems occur. Also, the small-sized in-cell model is more prominent due to the presence of the touch wire (TP trace line).
Disclosure of Invention
In view of this, the present invention provides an array substrate, which not only reduces power consumption, but also prevents light from irradiating a semiconductor layer to affect conductivity of the semiconductor layer.
An array substrate, comprising:
a substrate;
a first metal layer disposed on the substrate, the first metal layer including a source electrode;
the first insulating layer covers the source electrode, and a through hole is formed in the first insulating layer at the position corresponding to the source electrode;
a first transparent conductive layer disposed on the first insulating layer, the first transparent conductive layer including a pixel electrode;
the second metal layer is arranged on the first insulating layer and the pixel electrode and comprises a drain electrode which is electrically connected with the pixel electrode;
the semiconductor layer is arranged on the drain electrode and is filled in the through hole to electrically connect the source electrode and the drain electrode;
a second insulating layer covering the pixel electrode and the semiconductor layer;
a third metal layer disposed on the second insulating layer, the third metal layer including a gate;
a third insulating layer covering the gate electrode;
and a second transparent conductive layer disposed on the third insulating layer, the second transparent conductive layer including a common electrode.
In an embodiment of the invention, the semiconductor layer includes a first connection portion, a second connection portion, and a third connection portion, the first connection portion and the drain electrode are stacked, the second connection portion is filled in the through hole and connected between the first connection portion and the third connection portion, and the third connection portion and the source electrode are stacked.
In an embodiment of the invention, the first metal layer further includes a data line, and the data line is electrically connected to the source.
In an embodiment of the invention, the second metal layer further includes a touch lead, the touch lead is located on the first insulating layer, and the touch lead and the pixel electrode are disposed at an interval.
In an embodiment of the invention, an orthographic projection of the touch lead on the substrate is at least partially overlapped with an orthographic projection of the data line on the substrate.
In an embodiment of the present invention, the semiconductor layer is made of an IGZO material.
The invention also provides a display panel comprising the array substrate.
The invention also provides a manufacturing method for manufacturing the array substrate,
providing a substrate;
forming a first metal layer on the substrate, and carrying out patterning treatment on the first metal layer to enable the first metal layer to form a source electrode;
forming a first insulating layer covering the source electrode on the substrate, and carrying out patterning treatment on the first insulating layer to enable the first insulating layer to form a through hole at a position corresponding to the source electrode;
forming a first transparent conductive layer on the first insulating layer, and performing patterning processing on the first transparent conductive layer to form a pixel electrode on the first transparent conductive layer;
forming a second metal layer covering the pixel electrode on the first insulating layer, and performing patterning treatment on the second metal layer to form a drain electrode on the second metal layer, wherein the drain electrode is electrically connected with the pixel electrode;
forming a semiconductor film covering the pixel electrode and the drain electrode on the first insulating layer, and performing patterning treatment on the semiconductor film to form a semiconductor layer on the drain electrode by the semiconductor film, wherein the semiconductor layer is filled in the through hole to electrically connect the source electrode and the drain electrode;
forming a second insulating layer covering the pixel electrode and the semiconductor layer on the first insulating layer;
forming a third metal layer on the second insulating layer, and carrying out patterning treatment on the third metal layer to enable the third metal layer to form a grid electrode;
forming a third insulating layer covering the gate electrode on the second insulating layer;
and forming a second transparent conductive layer on the third insulating layer, and carrying out patterning treatment on the second transparent conductive layer to enable the second transparent conductive layer to form a common electrode.
In an embodiment of the invention, when the first metal layer is patterned, the first metal layer is also formed with a data line, wherein the data line is electrically connected to the source.
In an embodiment of the invention, when the second metal layer is subjected to the patterning process, the second metal layer is also subjected to a touch lead, wherein the touch lead and the pixel electrode are arranged at an interval.
According to the array substrate, the horizontal channel structure of the TFT (thin Film transistor) is designed into the vertical channel, so that the occupied area of the TFT on the substrate is reduced, the improvement of the aperture ratio of a pixel unit is facilitated, the vertical channel structure of the TFT reduces the channel length, the conductivity of the TFT is improved, the charging capability of a pixel (pixel) is improved, the power consumption can be reduced, and the pixel (pixel) design of a high pixel density (PPI) product is facilitated. Meanwhile, the semiconductor layer is arranged on the upper surface of the drain electrode formed by the second metal layer, and the semiconductor layer is directly deposited on the upper surface of the source electrode formed by the first metal layer after filling the through hole. Therefore, the semiconductor layer is directly positioned on the surface of the substrate and positioned on the upper surfaces of the drain electrode and the source electrode, so that light can be prevented from irradiating the semiconductor layer, and the influence of the light on the conductivity of the semiconductor layer after the light irradiates the semiconductor layer is avoided.
Drawings
Fig. 1 is a schematic partial cross-sectional view of an array substrate according to a first embodiment of the invention.
Fig. 2 is a schematic partial cross-sectional view of a display panel according to a first embodiment of the invention.
Fig. 3 to 18 are schematic cross-sectional views illustrating a manufacturing method of an array substrate according to a first embodiment of the invention.
Fig. 19 is a schematic partial cross-sectional view of an array substrate according to a second embodiment of the invention.
Detailed Description
In order to facilitate understanding of those skilled in the art, the present application provides a specific implementation process of the technical solution provided by the present application through the following embodiments.
First embodiment
Fig. 1 is a schematic partial cross-sectional structure view of an array substrate according to a first embodiment of the present invention, fig. 2 is a schematic partial cross-sectional structure view of a display panel according to the first embodiment of the present invention, and fig. 3 to 18 are schematic cross-sectional manufacturing process views of a manufacturing method of an array substrate according to the first embodiment of the present invention, as shown in fig. 1 to 18, the first embodiment of the present invention provides an array substrate, including:
substrate 10. substrate 10 may be made of glass, quartz, acrylic, or polycarbonate, among other materials.
A first metal layer 11 disposed on the substrate 10, the first metal layer 11 including the source electrode 111, the first metal layer 11 being made of copper and molybdenum niobium (Cu/MoNb), or copper and molybdenum (Cu/Mo), or copper and aluminum (Cu/Al).
A first insulating layer 12 covering the source 111, the first insulating layer 12 having a through hole 101 formed at a position corresponding to the source 111, the first insulating layer 12 being made of silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof.
A first transparent conductive layer 13 disposed on the first insulating layer 12, wherein the first transparent conductive layer 13 includes a pixel electrode 131, and the first transparent conductive layer 13 is made of a transparent metal oxide material such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). In the present embodiment, the first transparent conductive layer 13 is Indium Tin Oxide (ITO). In addition, a groove for accommodating the pixel electrode 131 may be further disposed on the first insulating layer 12, and after the pixel electrode 131 is disposed in the groove, the thicknesses of the first insulating layer 12 and the pixel electrode 131 can be reduced, so as to reduce the total thickness of the array substrate.
And a second metal layer 14 disposed on the first insulating layer 12 and the pixel electrode 131, wherein the second metal layer 14 includes a drain electrode 141, the drain electrode 141 is electrically connected to the pixel electrode 131, and the second metal layer 14 may be made of copper and molybdenum niobium (Cu/MoNb), or copper and molybdenum (Cu/Mo), or copper and aluminum (Cu/Al). In the present embodiment, a portion of the drain electrode 141 is stacked on the pixel electrode 131 to electrically connect the drain electrode 141 and the pixel electrode 131.
The semiconductor layer 151 is disposed on the drain 141, and the semiconductor layer 151 is filled in the via hole 101 to electrically connect the source 111 and the drain 141, in the embodiment, since the via hole 101 is formed at a position of the first insulating layer 12 corresponding to the source 111, the semiconductor layer 151 is directly deposited on the upper surface of the source 111, not the substrate 10, after filling the via hole 101.
A second insulating layer 16 covering the pixel electrode 131 and the semiconductor layer 151, wherein the material of the second insulating layer 16 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof.
A third metal layer 17 disposed on the second insulating layer 16, the third metal layer 17 including a gate electrode 171; in the present embodiment, when the third metal layer 17 is formed as the gate electrode 171, a scan line (not shown) is also formed, wherein the third metal layer 17 may be formed of copper and molybdenum niobium (Cu/MoNb), or copper and molybdenum (Cu/Mo), or copper and aluminum (Cu/Al).
And a third insulating layer 18 covering the gate electrode 171, wherein the material of the third insulating layer 18 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof.
And a second transparent conductive layer 19 disposed on the third insulating layer 18, wherein the second transparent conductive layer 19 includes a common electrode 191, and the second transparent conductive layer 19 is made of a transparent metal oxide material such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). In the present embodiment, the second transparent conductive layer 19 is Indium Tin Oxide (ITO).
As shown in fig. 1, the array substrate of the present invention reduces an occupied area of a TFT on the substrate by designing a horizontal channel structure of the TFT (thin Film transistor) as a vertical channel, which is helpful for improving an aperture ratio of a pixel unit, and the vertical channel structure of the TFT reduces a channel length, increases a conductive capability of the TFT and improves a charging capability of a pixel (pixel), thereby reducing power consumption and being beneficial to a pixel (pixel) design of a high pixel density (PPI) product. Meanwhile, the semiconductor layer 151 is disposed on the upper surface of the drain electrode 141 formed using the second metal layer 14, and the semiconductor layer 151 is also deposited directly on the upper surface of the source electrode 111 formed using the first metal layer 11 after filling the via hole 101. Therefore, the semiconductor layer 151 is located on the upper surfaces of the drain electrode 141 and the source electrode 111, which is opposite to the semiconductor layer 151 located on the surface of the substrate 10, so that light can be prevented from irradiating the semiconductor layer 151, and the influence of the light on the conductivity of the semiconductor layer 151 after irradiating the semiconductor layer 151 is avoided.
Further, as shown in fig. 1, the semiconductor layer 151 includes a first connection portion 1511, a second connection portion 1512, and a third connection portion 1513, the first connection portion 1511 is stacked with the drain 141, the second connection portion 1512 is filled in the through hole 101 and connected between the first connection portion 1511 and the third connection portion 1513, and the third connection portion 1513 is stacked with the source 111. In this embodiment, an orthographic projection of the third connection portion 1513 on the substrate 10 is located within an orthographic projection of the source 111 on the substrate 10, and preferably, orthographic projections of the first connection portion 1511, the second connection portion 1512 and the third connection portion 1513 are all located within an orthographic projection of the source 111 on the substrate 10, so that light can be completely prevented from being irradiated to the semiconductor layer 151.
Further, the first metal layer 11 further includes a data line (not shown), and the data line is electrically connected to the source 111. And the first insulating layer 12 covers not only the source electrode 111 but also the data line as well as the first insulating layer 12. Therefore, the first insulating layer 12, the second insulating layer 16, and the third insulating layer 18 are interposed between the data line and the common electrode 191, and the presence of the three insulating layers enables the capacitance between the data line and the common electrode 191 to be small. In the embodiment, since the data line and the source electrode 111 are both formed by the first metal layer 11, the data line and the source electrode 111 can be directly connected without an additional mask for forming a via hole for communicating the data line and the source electrode 111, thereby saving the cost.
Further, the second metal layer 14 further includes a touch lead 142, the touch lead 142 is located on the first insulating layer 12, and the touch lead 142 and the pixel electrode 131 are disposed at an interval. The second insulating layer 16 covers not only the pixel electrode 131 and the semiconductor layer 151, but also the touch lead 142 of the second insulating layer 16. Therefore, the second insulating layer 16 and the third insulating layer 18 are spaced between the touch lead 142 and the common electrode 191, and the presence of the two insulating layers can make the capacitance between the touch lead 142 and the common electrode 191 also smaller. In the embodiment, since the touch lead 142 and the drain 141 are both formed by the second metal layer 14, the touch lead 142 and the drain 141 can be formed simultaneously by one mask, and thus, two masks are not required to be used to manufacture the touch lead 142 and the drain 141 respectively, thereby saving the cost.
Further, the orthographic projection of the touch lead 142 on the substrate 10 is not overlapped with the orthographic projection of the data line on the substrate 10. In the embodiment, since the touch lead 142 and the data line are disposed in a staggered manner, the distance between the touch lead 142 and the data line is relatively long, and the current influence between the touch lead 142 and the data line can be reduced.
Further, the semiconductor layer 151 is made of an IGZO material. In an embodiment, an IGZO (indium gallium zinc oxide) material is used as the semiconductor layer 151, which has a higher electron mobility with respect to amorphous silicon (α -Si).
As shown in fig. 2, the present invention further relates to a display panel including the array substrate as described above.
Further, the display panel further includes an opposite substrate 20 disposed opposite to the array substrate, and a liquid crystal layer 30 disposed between the array substrate and the opposite substrate 20, wherein an upper polarizer is disposed on the opposite substrate 20, a lower polarizer is disposed on the array substrate, and a transmission axis of the upper polarizer is perpendicular to a transmission axis of the lower polarizer. In the liquid crystal layer 30, positive liquid crystal molecules (liquid crystal molecules having positive dielectric anisotropy) are used, and in an initial state, the positive liquid crystal molecules are in a lying posture, and the alignment direction of the positive liquid crystal molecules close to the counter substrate 20 is parallel to the alignment direction of the positive liquid crystal molecules close to the array substrate. It is understood that the array substrate and the opposite substrate 20 are further provided with an alignment layer at a layer facing the liquid crystal layer 30, thereby aligning the positive liquid crystal molecules in the liquid crystal layer 30.
Further, the opposite substrate 20 is a color film substrate, a black matrix and a color resist layer are disposed on the opposite substrate 20, the black matrix corresponds to the scan line, the data line, the thin film transistor and the peripheral non-display region, and the black matrix separates the plurality of color resist layers. The color resistance layer comprises color resistance materials of three colors of red (R), green (G) and blue (B), and sub-pixels of the three colors of red (R), green (G) and blue (B) are correspondingly formed.
As shown in fig. 3 to 18, the present invention also relates to a method for manufacturing the array substrate,
a substrate 10 is provided, and the substrate 10 may be made of glass, quartz, acrylic, or polycarbonate, among other materials.
Forming a first metal layer 11 on the substrate 10, and patterning the first metal layer 11 to make the first metal layer 11 form the source 111, wherein the first metal layer 11 may be made of copper and molybdenum niobium (Cu/MoNb), or copper and molybdenum (Cu/Mo), or copper and aluminum (Cu/Al).
Forming a first insulating layer 12 covering the source 111 on the substrate 10, and patterning the first insulating layer 12 to form a through hole 101 in the first insulating layer 12 at a position corresponding to the source 111, wherein the material of the first insulating layer 12 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof.
A first transparent conductive layer 13 is formed on the first insulating layer 12, and patterning is performed on the first transparent conductive layer 13, so that the pixel electrode 131 is formed on the first transparent conductive layer 13, and the first transparent conductive layer 13 is made of a transparent metal oxide material such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). In the present embodiment, the first transparent conductive layer 13 is Indium Tin Oxide (ITO).
Forming a second metal layer 14 covering the pixel electrode 131 on the first insulating layer 12, and performing a patterning process on the second metal layer 14 to form a drain 141 on the second metal layer 14, wherein the drain 141 is electrically connected to the pixel electrode 131; the second metal layer 14 may be made of copper and molybdenum niobium (Cu/MoNb), or copper and molybdenum (Cu/Mo), or copper and aluminum (Cu/Al). In the present embodiment, a portion of the drain electrode 141 is stacked on the pixel electrode 131 to electrically connect the drain electrode 141 and the pixel electrode 131.
Forming a semiconductor film 15 on the first insulating layer 12 to cover the pixel electrode 131 and the drain electrode 141, and patterning the semiconductor film 15 to form a semiconductor layer 151 on the drain electrode 141 from the semiconductor film 15, wherein the semiconductor layer 151 is filled in the through hole 101 to electrically connect the source electrode 111 and the drain electrode 141; in the present embodiment, since the via hole 101 is formed in the first insulating layer 12 corresponding to the source 111, the semiconductor layer 151 is directly deposited on the upper surface of the source 111, not the substrate 10, after filling the via hole 101.
Forming a second insulating layer 16 covering the pixel electrode 131 and the semiconductor layer 151 on the first insulating layer 12; wherein the material of the second insulating layer 16 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof.
Forming a third metal layer 17 on the second insulating layer 16, and performing patterning processing on the third metal layer 17 to form a gate 171 on the third metal layer 17; in this embodiment, when the third metal layer 17 is patterned to form the gate electrode 171, a scan line (not shown) is further formed, wherein the third metal layer 17 may be made of copper and molybdenum niobium (Cu/MoNb), or copper and molybdenum (Cu/Mo), or copper and aluminum (Cu/Al).
Forming a third insulating layer 18 covering the gate electrode 171 on the second insulating layer 16; wherein the material of the third insulating layer 18 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof.
A second transparent conductive layer 19 is formed on the third insulating layer 18, and patterning is performed on the second transparent conductive layer 19, so that the second transparent conductive layer 19 forms a common electrode 191. The second transparent conductive layer 19 is made of a transparent metal oxide material such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). In the present embodiment, the second transparent conductive layer 19 is Indium Tin Oxide (ITO).
Furthermore, when the first metal layer 11 is patterned, the first metal layer 11 also forms a data line, wherein the data line is electrically connected to the source 111. The first insulating layer 12 covers not only the source electrode 111, but also the data line of the first insulating layer 12. Therefore, the first insulating layer 12, the second insulating layer 16, and the third insulating layer 18 are interposed between the data line and the common electrode 191, and the presence of the three insulating layers enables the capacitance between the data line and the common electrode 191 to be small. In the embodiment, since the data line and the source electrode 111 are both formed by the first metal layer 11, the data line and the source electrode 111 can be directly connected without an additional mask for forming a via hole for communicating the data line and the source electrode 111, thereby saving the cost. Meanwhile, since the data line and the source electrode 111 are both formed by the first metal layer 11, the data line and the source electrode 111 can be formed simultaneously by only one photomask, and one photomask is saved compared with the method of forming the data line and the source electrode 111 by two photomasks respectively.
Further, when the second metal layer 14 is patterned, the second metal layer 14 is also formed with a touch lead 142, wherein the touch lead 142 is disposed at an interval from the pixel electrode 131. The second insulating layer 16 covers not only the pixel electrode 131 and the semiconductor layer 151, but also the touch lead 142 of the second insulating layer 16. Therefore, the second insulating layer 16 and the third insulating layer 18 are spaced between the touch lead 142 and the common electrode 191, and the presence of the two insulating layers can make the capacitance between the touch lead 142 and the common electrode 191 also smaller. In the embodiment, since the touch lead 142 and the drain 141 are both formed by using the second metal layer 14, the touch lead 142 and the drain 141 can be simultaneously formed by using one mask, and thus, two masks are not required to be used to manufacture the touch lead 142 and the drain 141 respectively, thereby saving one mask.
Second embodiment
Fig. 19 is a schematic partial cross-sectional view of an array substrate according to a second embodiment of the invention. As shown in fig. 19, the array substrate provided by the second embodiment of the present invention is substantially the same as the array substrate provided by the first embodiment, except that in this embodiment, the relative positions of the touch leads and the data lines are different.
Further, the orthographic projection of the touch lead 142 on the substrate 10 is at least partially overlapped with the orthographic projection of the data line 112 on the substrate 10. In the present embodiment, the orthographic projection of the data line 112 on the substrate 10 is located within the orthographic projection of the touch lead 142 on the substrate 10, or the orthographic projection of the touch lead 142 on the substrate 10 is located within the orthographic projection of the data line 112 on the substrate 10. Therefore, the positions of the data lines 112 and the touch leads 142 are overlapped, so that the positions of the touch leads 142 are saved, and the opening area is increased.
For other structures of the array substrate, please refer to the first embodiment, which is not repeated herein.
In this document, the terms of upper, lower, left, right, front, rear and the like are used to define the positions of the structures in the drawings and the positions of the structures relative to each other, and are only used for the sake of clarity and convenience in technical solution. It is to be understood that the use of the directional terms should not be taken to limit the scope of the claims. It is also to be understood that the terms "first" and "second," etc., are used herein for descriptive purposes only and are not to be construed as limiting in number or order.
Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. An array substrate, comprising:
a substrate (10);
a first metal layer (11) disposed on the substrate (10), the first metal layer (11) including a source (111);
a first insulating layer (12) covering the source electrode (111), wherein a through hole (101) is formed in the first insulating layer (12) at a position corresponding to the source electrode (111);
a first transparent conductive layer (13) provided on the first insulating layer (12), the first transparent conductive layer (13) including a pixel electrode (131);
a second metal layer (14) disposed on the first insulating layer (12) and the pixel electrode (131), wherein the second metal layer (14) includes a drain (141), and the drain (141) is electrically connected to the pixel electrode (131);
the semiconductor layer (151) is arranged on the drain electrode (141), and the semiconductor layer (151) is filled in the through hole (101) to electrically connect the source electrode (111) and the drain electrode (141);
a second insulating layer (16) covering the pixel electrode (131) and the semiconductor layer (151);
a third metal layer (17) disposed on the second insulating layer (16), the third metal layer (17) including a gate electrode (171);
a third insulating layer (18) covering the gate electrode (171);
a second transparent conductive layer (19) disposed on the third insulating layer (18), the second transparent conductive layer (19) including a common electrode (191).
2. The array substrate according to claim 1, wherein the semiconductor layer (151) comprises a first connection portion (1511), a second connection portion (1512), and a third connection portion (1513), the first connection portion (1511) is stacked with the drain electrode (141), the second connection portion (1512) fills in the through hole (101) and is connected between the first connection portion (1511) and the third connection portion (1513), and the third connection portion (1513) is stacked with the source electrode (111).
3. The array substrate of claim 1, wherein the first metal layer (11) further comprises a data line (112), and the data line (112) is electrically connected to the source electrode (111).
4. The array substrate according to claim 3, wherein the second metal layer (14) further comprises a touch lead (142), the touch lead (142) is located on the first insulating layer (12), and the touch lead (142) is spaced apart from the pixel electrode (131).
5. The array substrate of claim 4, wherein an orthographic projection of the touch lead (142) on the substrate (10) is at least partially coincident with an orthographic projection of the data line (112) on the substrate (10).
6. The array substrate according to any one of claims 1 to 5, wherein the semiconductor layer (151) is made of IGZO material.
7. A display panel comprising the array substrate according to any one of claims 1 to 6.
8. A manufacturing method of an array substrate is characterized by comprising the following steps:
providing a substrate (10);
forming a first metal layer (11) on the substrate (10), and carrying out patterning treatment on the first metal layer (11) to enable the first metal layer (11) to form a source electrode (111);
forming a first insulating layer (12) covering the source electrode (111) on the substrate (10), and carrying out patterning treatment on the first insulating layer (12) to enable the first insulating layer (12) to form a through hole (101) at a position corresponding to the source electrode (111);
forming a first transparent conductive layer (13) on the first insulating layer (12), and performing patterning processing on the first transparent conductive layer (13) to form a pixel electrode (131) on the first transparent conductive layer (13);
forming a second metal layer (14) covering the pixel electrode (131) on the first insulating layer (12), and performing a patterning process on the second metal layer (14) to form a drain electrode (141) on the second metal layer (14), wherein the drain electrode (141) is electrically connected with the pixel electrode (131);
forming a semiconductor film (15) covering the pixel electrode (131) and the drain electrode (141) on the first insulating layer (12), and performing patterning processing on the semiconductor film (15) to enable the semiconductor film (15) to form a semiconductor layer (151) on the drain electrode (141), wherein the semiconductor layer (151) is filled in the through hole (101) to electrically connect the source electrode (111) and the drain electrode (141);
forming a second insulating layer (16) covering the pixel electrode (131) and the semiconductor layer (151) on the first insulating layer (12);
forming a third metal layer (17) on the second insulating layer (16), and performing patterning processing on the third metal layer (17) to enable the third metal layer (17) to form a grid electrode (171);
forming a third insulating layer (18) covering the gate electrode (171) on the second insulating layer (16);
and forming a second transparent conductive layer (19) on the third insulating layer (18), and performing patterning treatment on the second transparent conductive layer (19) to form a common electrode (191) on the second transparent conductive layer (19).
9. The method for manufacturing the array substrate according to claim 8, wherein when the patterning process is performed on the first metal layer (11), a data line (112) is simultaneously formed on the first metal layer (11), wherein the data line (112) is electrically connected to the source electrode (111).
10. The method for manufacturing the array substrate according to claim 8, wherein when the second metal layer (14) is patterned, the second metal layer (14) is formed with a touch lead (142), wherein the touch lead (142) is spaced from the pixel electrode (131).
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