KR101496204B1 - Method of manufacturing liquid crystal display - Google Patents

Abstract

A method of manufacturing a liquid crystal display device capable of realizing high transmittance and high-speed driving is provided. A method of manufacturing a liquid crystal display device includes: forming a gate electrode on an insulating substrate; Forming a gate insulating film on the gate electrode; Forming an oxide semiconductor layer on the gate insulating layer; Forming an etch stop layer on the channel region of the oxide semiconductor layer; Forming a lower wiring layer and an upper wiring layer on the gate insulating film, the oxide semiconductor layer, and the etching stopper film; Etching the lower wiring layer and the upper wiring layer to form a source electrode and a drain electrode including the lower wiring layer and the upper wiring layer; Forming a protective film on the etch stop layer, the common electrode, the source electrode, and the drain electrode; And forming a pixel electrode connected to the drain electrode on the passivation layer, wherein the source electrode and the drain electrode are spaced apart from each other on the etch stop layer and extend to the top of the oxide semiconductor layer.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display

The present invention relates to a liquid crystal display device and a method of manufacturing the same, and more particularly, to a liquid crystal display device in which a common electrode and a pixel electrode are formed on one substrate and a method of manufacturing the same.

2. Description of the Related Art A liquid crystal display (LCD) is one of the most widely used flat panel displays, and is composed of two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween. And rearranges the liquid crystal molecules in the liquid crystal layer to adjust the amount of light transmitted.

The liquid crystal display device is advantageous in that the liquid crystal display device is thin, has a relatively low power consumption, and generates little harmful electromagnetic waves. However, the liquid crystal display device has various drawbacks A liquid crystal array and a driving method are being developed. As a method for realizing such a wide viewing angle, a PVA (Patterned Vertical Aligned) mode in which a cut-out portion for domain division is applied and an in-plane switching (IPS) mode in which a horizontal electric field method is adopted are presented in a liquid crystal display device of a vertical alignment mode .

However, the PVA mode often has texture or afterimage, and there is still a limit to realize a perfect wide viewing angle. In addition, IPS has a burden of adopting a high-brightness backlight because the common electrode has a low aperture ratio and a relatively low brightness.

A planar to line switching (PLS) mode in which a transverse electric field system such as an IPS mode is adopted is attracting attention as a system for simultaneously realizing such a wide viewing angle and a high luminance. However, in the case of a large area high resolution liquid crystal display device driven at a high speed of 120 Hz or more, development of a thin film transistor having high mobility characteristics in a channel region is required.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal display device capable of realizing high transmittance and high-speed driving.

Another object of the present invention is to provide a method of manufacturing such a liquid crystal display device.

The problems of the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to another aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, including: forming a gate electrode on an insulating substrate; forming an oxide semiconductor layer on the gate electrode; Forming a lower interconnection layer and an upper interconnection layer on the resultant structure; etching the lower interconnection layer and the upper interconnection layer to form a lower electrode; Forming a source electrode and a drain electrode including the lower wiring layer and the upper wiring layer; forming a protective film on the etch stop film, the common electrode, the source electrode, and the drain electrode; And forming a pixel electrode connected to the drain electrode. Here, the source electrode and the drain electrode may be spaced apart from each other on the etch stop layer and extend to the top of the oxide semiconductor layer.

The details of other embodiments are included in the detailed description and drawings.

 According to the present invention, it is possible to provide a method of manufacturing a liquid crystal display device capable of realizing high transmittance and high speed driving.

1 is a layout view of a lower panel of a liquid crystal display according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view of the lower panel of FIG. 1 taken along line II-II '. FIG.
FIGS. 3 to 9 are process sectional views sequentially showing the manufacturing method of the lower panel of FIG.
10 is a layout view of a lower panel of a liquid crystal display according to a second embodiment of the present invention.
11 is a layout view of a lower panel of a liquid crystal display according to a third embodiment of the present invention.
12 is a cross-sectional view of the lower panel of FIG. 11 taken along line XII-XII '.
13 is a sectional view of a lower panel of a liquid crystal display according to a fourth embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The dimensions and relative sizes of layers and regions in the figures may be exaggerated for clarity of illustration.

It is to be understood that when an element or layer is referred to as being "on" or " on "of another element or layer, All included. On the other hand, a device being referred to as "directly on" or "directly above " indicates that no other device or layer is interposed in between. "And / or" include each and every combination of one or more of the mentioned items.

The terms spatially relative, "below", "beneath", "lower", "above", "upper" May be used to readily describe a device or a relationship of components to other devices or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. Like reference numerals refer to like elements throughout the specification.

Embodiments described herein will be described with reference to plan views and cross-sectional views, which are ideal schematics of the present invention. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are generated according to the manufacturing process. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

First, a liquid crystal display according to embodiments of the present invention will be described. The liquid crystal display according to embodiments of the present invention includes a lower display panel including a thin film transistor array, an upper display panel facing the lower display panel and spaced apart from the lower display panel, and a liquid crystal layer interposed between the lower display panel and the upper display panel .

1 is a layout view of a lower panel of a liquid crystal display according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view of the lower panel of FIG. 1 taken along line II-II '. FIG.

Referring to FIGS. 1 and 2, the lower panel will be described. Gate wirings 22 and 26 for transmitting gate signals are formed on an insulating substrate 10 made of transparent glass or plastic. The gate wirings 22 and 26 include a gate line 22 extending in the transverse direction and a gate electrode 24 of the thin film transistor formed in a protrusion shape connected to the gate line 22.

On the insulating substrate 10, a common electrode line 25 for transmitting a common voltage is formed. The common electrode line 25 is formed in a lateral direction substantially parallel to the gate line 22. [

The gate wirings 22 and 26 and the common electrode line 25 may be formed of any one of aluminum based metals such as aluminum (Al) and an aluminum alloy, a copper based alloy such as silver (Ag) A metal of molybdenum series such as molybdenum (Mo) and molybdenum alloy, chromium (Cr), titanium (Ti), tantalum (Ta) and the like. Further, the gate wirings 22 and 26 and the common electrode line 25 may have a multi-film structure including two conductive films (not shown) having different physical properties. One of the conductive films is formed of a metal having a low resistivity such as an aluminum-based metal, a silver-based metal, a copper-based metal, or the like, so as to reduce signal delay or voltage drop of the gate wirings 22, 26 and the common electrode line 25. [ . Alternatively, the other conductive film may be made of a material having excellent contact properties with other materials, particularly zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO), such as molybdenum metal, chromium, titanium, tantalum and the like. A good example of such a combination is a chromium bottom film, an aluminum top film, an aluminum bottom film and a molybdenum top film. However, the present invention is not limited thereto, and the gate wirings 22 and 26 and the common electrode line 25 may be made of various metals and conductors.

A gate insulating film 30 made of silicon oxide (SiOx) or silicon nitride (SiNx) is formed on the insulating substrate 10, the gate wirings 22, 26, and the common electrode line 25. [

On the gate insulating film 30, an oxide semiconductor layer 40 made of an oxide of a material selected from Zn, In, Ga, Sn, and combinations thereof is formed. For example, as the oxide semiconductor layer 40, a mixed oxide such as ZnO, InZnO, InGaO, InSnO, ZnSnO, GaSnO, GaZnO, GaZnSnO or GaInZnO may be used. The oxide semiconductor layer 40 has an effective mobility of about 2 to 100 times higher than that of hydrogenated amorphous silicon and has an on / off current ratio of 10 ⁵ to 10 ⁸ , have. In addition, in the case of the oxide semiconductor layer 40, since the band gap is about 3.0 to 3.5 eV, no leakage photocurrent is generated with respect to visible light. Accordingly, instantaneous afterglow of the oxide thin film transistor can be prevented, and it is not necessary to form a light shielding film under the oxide thin film transistor, so that the aperture ratio of the liquid crystal display device can be increased. Group 3, Group 4, Group 5 or transition elements on the periodic table may be further included to improve the characteristics of the oxide semiconductor. Also, the oxide semiconductor layer 40 is in an amorphous state, but has a high charge mobility and can be applied to a conventional amorphous silicon manufacturing process, so that the oxide semiconductor layer 40 can be applied to a large area display device.

An etch stopper 50 is formed on the oxide semiconductor layer 40 in a position overlapping the gate electrode 24. The etch stop layer 50 prevents the channel region of the oxide semiconductor layer 40 from being damaged by etching in the process of forming the subsequent data lines 55, 56, 62, 65, and 66. As the etching stopper film 50, an inorganic material such as an oxide, a nitride, or an oxynitride may be used. For example, as the etching stopper film 50, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (AlOx), hafnium oxide (HfOx), or the like can be used.

Data wirings 55, 56, 62, 65, and 66 are formed on the oxide semiconductor layer 40, the etching stopper film 50, and the gate insulating film 30. The data lines 55, 56, 62, 65 and 66 are formed in the vertical direction and intersect the gate line 22 to define a pixel, a data line 62 extending from the data line 62 in a branch form Source electrodes 55 and 65 which are branched and extended to the upper portion of the oxide semiconductor layer 40 and source electrodes 55 and 65 which are separated from the source electrodes 55 and 65 and which are separated from each other by a channel portion of the gate electrode 24 or the oxide thin film transistor, And drain electrodes 56 and 66 formed on the oxide semiconductor layer 40 so as to face the gate electrodes 55 and 65, respectively.

The source electrodes 55 and 65 are composed of a source lower film 55 in contact with the oxide semiconductor layer 40 and a source upper film 65 formed on the source lower film 55. The drain electrodes 56 and 66 Includes a drain lower film 56 connected to the oxide semiconductor layer 40 and a drain upper film 66 formed on the drain lower film 56. [ The source lower film 55 and the source upper film 65 have substantially the same pattern shape and the drain lower film 56 and the drain upper film 66 have substantially the same pattern shape.

In addition, a common electrode 52 is formed in the pixel region on the gate insulating film 30. The common electrode 52 is connected to the common electrode line 25 through the contact hole 32 formed in the gate insulating film 30 and receives a common voltage. The common electrode 52 is arranged in a matrix form as a substantially rectangular plane electrode and has a region defined by the gate line 22 and the data line 62 It is filling. The common electrode 52 is formed in the same layer as the source lower film 55 and the drain lower film 56, and may be made of the same material.

The source lower film 55 and drain lower film 56 are preferably made of a material having good contact properties with the oxide semiconductor layer 40 and the common electrode 52 is preferably made of a transparent conductor. For example, the source lower film 55, the drain lower film 56, and the common electrode 52 may be made of an oxide including indium (In), zinc (Zn), tin (Sn) Specifically, it may be made of a transparent conductor such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The source lower film 55, the drain lower film 56, and the common electrode 52 can be made of aluminum (Al) (Al), copper (Cu), silver (Ag), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), nickel (Ni), cobalt have. Here, molybdenum (Mo), tungsten (W), niobium (Nb), zirconium (Zr), vanadium (V), oxygen (O), nitrogen (N) and the like may be added to form an alloy.

The source upper film 65 and the drain upper film 66 may be formed of a material selected from the group consisting of Al, Cu, Ag, Mo, Cr, Ti, (Ni), cobalt (Co), or an alloy thereof. Preferably, the source top film 65 and the drain top film 66 are formed of a metal material having a low specific resistance, for example, an aluminum-based metal such as aluminum (Al) and an aluminum alloy, And may be made of a copper-based metal such as copper (Cu) and a copper alloy.

The source electrodes 55 and 65 overlap at least a part of the oxide semiconductor layer 40 and the etching stopper film 50 and the drain electrodes 56 and 66 are connected to the source electrodes 55 and 65 And at least a part of the oxide semiconductor layer 40 and the etching stopper film 50 are overlapped with each other. The portion of the oxide semiconductor layer 40 that does not overlap with the source electrodes 55 and 65 and the drain electrodes 56 and 66 is overlapped with the etching stopper film 50.

A protective film 70 is formed on the data lines 55, 56, 62, 65, and 66. For example, the protective film 70 may be formed of an inorganic material such as silicon nitride or silicon oxide, an organic material having excellent planarization characteristics and photosensitivity, or an organic material formed by plasma enhanced chemical vapor deposition (PECVD) -Si: C: O, a-Si: O: F, or the like. Further, the protective film 70 may have a bilayer structure of a lower inorganic film and an upper organic film.

The protective film 70 is provided with a contact hole 77 for exposing the drain electrodes 56 and 66. A pixel electrode 82 electrically connected to the drain electrodes 56 and 66 through the contact hole 77 is formed on the passivation layer 70. The pixel electrode 82 may be formed of a transparent conductor such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide) or a reflective conductor such as aluminum. The pixel electrode 82 to which the data voltage is applied generates an electric field together with the common electrode 52 to rotate the liquid crystal molecules of the liquid crystal layer interposed between the lower display panel and the upper display panel.

The pixel electrode 80 includes a plurality of main field generating portions 80a in a stripe pattern and a connecting portion 80b for connecting the main electric field generating portion 80a. Between the neighboring main field generating portions 80a, cutouts 81 are formed in the shape of a quadrangle or other closed curve.

The main electric field generating portion 80a occupies most of the pixel electrodes 80, has a rod shape, and extends in a substantially horizontal direction. The main electric field generating portion 80a is inclined at a predetermined angle (referred to as a 'pre-scan square') with respect to the gate line 22 in order to facilitate the smooth behavior of the liquid crystal molecules according to the horizontal electric field. In other words, the main electric field generating portion 80a is inclined at a predetermined angle with respect to the alignment direction of the alignment film located above the pixel electrode 80. [ Hereinafter, the case where the alignment film is oriented in the lateral direction along the gate line 22 will be described as an example.

When an electric field is formed between the main electric field generating portion 80a and the common electrode 26, this electric field includes a horizontal electric field component parallel to the lower panel. When viewed from the top of the lower panel, the horizontal electric field component is directed vertically from the side of the main electric field generating portion 80a. Therefore, when the liquid crystal molecules having positive dielectric anisotropy are initially aligned with the main electric field generating portion 80a at a predetermined angle (pre-scan square), the liquid crystal molecules are aligned in the horizontal electric field It is possible to perform the rotational motion easily. When the main electric field generating portion 80a is inclined with respect to the initial alignment direction of the liquid crystal molecules, the rotational motion of the liquid crystal molecules becomes more desirable and the reaction rate increases.

The square of the angle between the main electric field generating portion 80a and the gate line 22 (or the alignment layer formed on the lower panel) may have a value between 0 and 45 degrees. Preferably, it may be in the range of 5 to 15 degrees, more preferably in the range of 9 to 11 degrees in consideration of the change in brightness and the reaction rate of the liquid crystal molecules.

1, the main electric field generating portion 80a is formed as a whole in the lateral direction, but it may be formed in the longitudinal direction.

Hereinafter, a method of manufacturing the lower panel according to the first embodiment of the present invention will be described in detail with reference to FIGS. 1 to 9. FIG. FIGS. 3 to 9 are process sectional views sequentially showing the manufacturing method of the lower panel of FIG.

First, referring to FIGS. 1 and 3, a gate line 22, a gate electrode 24, and a common electrode line 25 are formed on an insulating substrate 10.

The insulating substrate 10 may be made of, for example, glass or plastic such as soda lime glass or borosilicate glass. A sputtering method may be used to form the gate wirings 22 and 26 and the common electrode line 25. [ Wet etching or dry etching may be used for patterning the gate wirings 22 and 26 and the common electrode line 25. [ In the case of wet etching, an etchant such as phosphoric acid, nitric acid or acetic acid can be used. In case of dry etching, chlorine-based etching gas such as Cl ₂ , BCl ₃ and the like can be used.

Subsequently, a gate insulating film (not shown) is formed on the insulating substrate 10, the gate wirings 22 and 26, and the common electrode line 25 by plasma enhanced chemical vapor deposition (PECVD), reactive sputtering, 30).

Referring to FIGS. 1 and 4, an oxide semiconductor layer 40 is formed on the gate insulating layer 30. For example, as the oxide semiconductor layer 40, a mixed oxide such as ZnO, InZnO, InGaO, InSnO, ZnSnO, GaSnO, GaZnO, GaZnSnO or GaInZnO may be used.

Referring to FIGS. 1 and 5, an etch stop layer 50 is formed on the oxide semiconductor layer 40. Silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (AlOx), hafnium oxide (HfOx), or the like can be used as the etching stopper film (50).

1 and 6, a lower wiring layer 51 and an upper wiring layer 60 are formed on the etching stopper film 50, the oxide semiconductor layer 40, and the gate insulating film 30 by, for example, sputtering. Sequentially. Here, the lower wiring layer 51 may be made of an oxide including indium (In), zinc (Zn), tin (Sn) or the like. Specifically, ITO (Indium Tin Oxide) And may be made of a transparent conductor. The lower wiring layer 51 may be formed of a material selected from the group consisting of Al, Cu, Ag, Mo, Cr, Ti, Ta, Ni, Co) or an alloy thereof. Here, molybdenum (Mo), tungsten (W), niobium (Nb), zirconium (Zr), vanadium (V), oxygen (O), nitrogen (N) and the like may be added to form an alloy. The upper wiring layer 60 is formed of a material selected from the group consisting of Al, Cu, Ag, Mo, Cr, Ti, Ta, Ni, Co) or an alloy thereof.

Next, a photoresist layer is coated on the upper wiring layer 60, and then light is irradiated to the photoresist layer through a mask and developed to form photoresist patterns 112 and 114. Here, the photoresist patterns 112 and 114 are composed of two regions having different thicknesses, and the second region 112 having a relatively large thickness is located at a portion where the data wiring portion A, that is, the data wiring is formed, The relatively thin first region 114 is located at the portion where the common electrode portion B, i.e., the common electrode is to be formed. Then, the photoresist film of the other portion (B) except the data wiring portion (A) and the common electrode portion (B) is removed. In particular, the photoresist layer on the etch stop layer 50 corresponding to the channel region is also removed.

As described above, there are various methods of varying the thickness of the photoresist layer depending on the position, and a slit, a lattice pattern, or a mask using a semitransparent film can be used to adjust the light transmittance. In addition, by using a photoresist film made of a material capable of reflowing, the photoresist film is exposed by a conventional mask, which is divided into a portion where light can be completely transmitted and a portion where light can not be completely transmitted, A part of the photoresist film may be caused to flow down to the portion where the photoresist film 114 is not formed.

6 and 7, the upper wiring layer 60 and the lower wiring layer 51 are etched using the photoresist pattern 112 and 114 as an etching mask to form the source lower film 55 and the source upper film 65, Drain electrodes 56 and 66 composed of a drain lower film 56 and a drain upper film 66 and source and drain electrodes 55 and 65 formed on the upper and lower surfaces of the common electrode 52 and common electrode 52, (60). The etch can be wet etch or dry etch, wet etch etch can be used such as phosphoric acid, nitric acid, acetic acid etch, and dry etch can etch chlorine etch gases such as Cl ₂ and BCl ₃ . Can be used.

Next, the first photoresist pattern 112 and the first photoresist pattern 114 are etched to expose the upper wiring layer 60 above the common electrode 52. In this case, the thickness of the second region 112 is also reduced. Such front etching can be performed by, for example, an ashing process using an oxygen plasma or the like.

Referring to FIGS. 7 and 8, the exposed upper wiring layer 60 is etched using the photoresist pattern 112 as an etching mask. The common electrode 52 is exposed to the outside. The etch can be wet etch or dry etch, wet etch etch can be used such as phosphoric acid, nitric acid, acetic acid etch, and dry etch can etch chlorine etch gases such as Cl ₂ and BCl ₃ . Can be used.

Then, the photoresist pattern 112 is removed by an ashing process using an oxygen plasma or the like.

Referring to FIG. 9, a protective film 70 is formed on the source electrodes 55 and 65, the drain electrodes 56 and 66, and the common electrode 52. For example, the protective film 70 may be formed of an inorganic material such as silicon nitride or silicon oxide, an organic material having excellent planarization characteristics and photosensitivity, or an organic material formed by plasma enhanced chemical vapor deposition (PECVD) -Si: C: O, a-Si: O: F, or the like. Further, the protective film 70 may have a bilayer structure of a lower inorganic film and an upper organic film. Then, the protective film 70 is patterned by a photolithography process to form a contact hole 77 for exposing the drain electrodes 56 and 66.

Referring again to FIG. 2, a conductive film for a pixel electrode is formed on the passivation layer 70 and is patterned to form a pixel electrode 82 connected to the drain electrodes 56 and 66.

Hereinafter, a liquid crystal display according to a second embodiment of the present invention will be described with reference to FIG. 10 is a layout view of a lower panel of a liquid crystal display according to a second embodiment of the present invention. For convenience of explanation, the members having the same functions as those of the members shown in the drawings of the first embodiment are denoted by the same reference numerals and the description thereof will be omitted, and the differences will be mainly described below.

In this embodiment, a separate common electrode line is not provided for connecting the common electrode 52 formed in the neighboring pixels. That is, the common electrodes 52 formed on the neighboring pixels, that is, the pixels disposed on the upper and lower sides, are connected to each other by the common electrode connection portion 53 made of the same material in the same layer as the common electrode 52. Since the common electrode connecting portion 53 is formed on the gate insulating film 30, the common electrode connecting portion 53 is insulated from the gate line 22.

Hereinafter, a liquid crystal display according to a third embodiment of the present invention will be described with reference to FIGS. 11 and 12. FIG. 11 is a layout view of a lower panel of a liquid crystal display according to a third embodiment of the present invention, and FIG. 12 is a cross-sectional view of a lower panel of FIG. 11 taken along line XII-XII '. For convenience of explanation, the members having the same functions as the members shown in the drawings of the second embodiment are denoted by the same reference numerals, and a description thereof will be omitted, and the differences will be mainly described below.

A gate electrode 24 and an additional gate electrode 24 overlapping the oxide semiconductor layer 40 are formed on the protective film 70. The additional gate electrode 24 may be formed of the same material as the pixel electrode 82 in the same layer. The additional gate electrode 24 is connected to the gate electrode 24 through the protective film 70 and the contact hole 75 formed in the gate insulating film 30. [ Therefore, when a gate-on voltage is applied through the gate line 22, the gate electrode 24 disposed under the oxide semiconductor layer 40 and the additional gate electrode 24 disposed over the oxide semiconductor layer 40 Since the channel region is formed in the oxide semiconductor layer 40, signals can be smoothly transmitted between the source electrodes 55 and 65 and the drain electrodes 56 and 66.

In this embodiment, the common electrode connection portion 53 is used to connect the common electrode 52 formed in the neighboring pixels, but the present invention is not limited thereto. That is, a common electrode line made of the same material may be provided in the same layer as the gate line 22 without using the common electrode connecting portion 53. The common electrode line may be electrically connected to the common electrode 52 through the contact hole.

Hereinafter, a liquid crystal display according to a fourth embodiment of the present invention will be described with reference to FIG. 13 is a cross-sectional view of a lower panel of a liquid crystal display according to a fourth embodiment of the present invention. For convenience of explanation, the members having the same functions as those of the members shown in the drawings of the first embodiment are denoted by the same reference numerals and the description thereof will be omitted, and the differences will be mainly described below.

As shown in FIG. 13, the oxide semiconductor layer 40 may not be provided with a separate etching stopper film for protecting the oxide semiconductor layer 40. In this case, the oxide semiconductor layer 40 is preferably made of a material having a high etch selectivity ratio as compared with the common electrode 52. For example, when a transparent conductor such as ITO or IZO is used as the common electrode 52, the oxide semiconductor layer 40 may be made of an oxide containing no indium (In). If there is no etching stopper film, the oxide semiconductor layer 40 may be etched together when the common electrode 52 is patterned. The indium-containing oxide is used as the common electrode 52 and the indium-free oxide is used as the oxide semiconductor layer 40. In the case where the common electrode 52 and the oxide semiconductor layer 40 are formed using indium- The etch selectivity ratio can be increased.

Furthermore, in order to prevent the oxide semiconductor layer 40 from being etched while patterning the common electrode 52, the oxide semiconductor layer 40 preferably includes tin (Sn). Since the etching rate is low in the case of tin, the etch selectivity between the common electrode 52 and the oxide semiconductor layer 40 can be further increased. As the oxide semiconductor layer 40, for example, ZnSnO, GaSnO, or GaZnSnO may be used.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is to be understood that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

10: insulating substrate 22: gate line
24: gate electrode 25: common electrode line
30: gate insulating film 32: contact hole
40: oxide semiconductor layer 50: etch stop film
52: common electrode 55, 65: source electrode
56, 66: drain electrode 62: data line
70: protective film 75, 77: contact hole
82: pixel electrode

Claims (4)

Forming a gate electrode on an insulating substrate;
Forming a gate insulating film on the gate electrode;
Forming an oxide semiconductor layer on the gate insulating layer;
Forming an etch stop layer on the channel region of the oxide semiconductor layer;
Forming a lower wiring layer and an upper wiring layer on the gate insulating film, the oxide semiconductor layer, and the etching stopper film;
Etching the lower wiring layer and the upper wiring layer to form a source electrode and a drain electrode including the lower wiring layer and the upper wiring layer;
Forming a protective film on the etch stop layer, the common electrode, the source electrode, and the drain electrode; And
And forming a pixel electrode connected to the drain electrode on the protective film,
Wherein the source electrode and the drain electrode are spaced apart from each other above the etch stop layer and extend to the top of the oxide semiconductor layer. The method of claim 1, wherein forming the common electrode, the source electrode,
Forming a photoresist layer on the upper wiring layer, the photoresist layer having two regions having different thicknesses and exposing the etching stopper film and the upper portion of the drain electrode;
Etching the upper wiring layer and the lower wiring layer using the photoresist film as an etching mask;
Removing the photoresist layer on the common electrode; And
And removing the upper wiring layer on the common electrode. The liquid crystal display device according to claim 1, wherein, during formation of the pixel electrode,
And forming an additional gate electrode overlapping the gate electrode on the protective film. The method according to claim 1,
Wherein the pixel electrode includes a plurality of main electric field generating portions spaced apart by a cutout portion and a connecting portion connecting the main electric field generating portions.

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