KR20050118537A - Substrate for liquid crystal display device and manufacturing method thereof - Google Patents

Abstract

An object of the present invention is to provide an IPS type liquid crystal display device having a high opening ratio and a manufacturing method thereof.

The present invention provides a semiconductor device comprising: a gate wiring and a data wiring crossing each other on a substrate; Common wiring spaced apart in parallel with the gate wiring; A common electrode connected to the common wiring; A gate electrode connected to the gate wiring; A source electrode connected to the data line, a drain electrode spaced apart from the source electrode; A pixel electrode spaced apart from the common electrode and connected to the drain electrode; A substrate for a liquid crystal display device includes a first auxiliary electrode connected to the drain electrode and formed on the common electrode adjacent to the data line to form a first storage capacitor.

According to the present invention, the aperture ratio of the IPS type liquid crystal display device can be increased by forming the pixel electrode and the common electrode using a transparent conductive metal material and configuring the storage capacitor in a portion where the common electrode adjacent to the data line is formed.

Description

Substrate for liquid crystal display device and manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to an in-plane switching mode liquid crystal display device.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the arrangement of molecules can be controlled by artificially applying an electric field to the liquid crystal. Therefore, by adjusting the molecular arrangement of the liquid crystal, light can be refracted to express image information.

The liquid crystal display is driven by applying an electric field to the liquid crystal by using a voltage difference between the common electrode and the pixel electrode to express image information. The common electrode and the pixel electrode are formed on the same substrate to form a horizontal electric field in the liquid crystal layer. In-plane switching mode (hereinafter referred to as IPS type) liquid crystal display devices are widely used because of their excellent viewing angle characteristics.

1A and 1B are cross-sectional views showing the arrangement of liquid crystal molecules in a voltage off / on state in an IPS type liquid crystal display device, respectively.

In the voltage-off state, as shown in FIG. 1A, since no electric field is formed in the liquid crystal molecules 50, the liquid crystal molecules 50 are maintained in the initial arrangement state.

In the voltage-on state, as shown in FIG. 1B, since a vertical electric field is formed on the common electrode 38 and the pixel electrode 40, the liquid crystal molecules 50a positioned therein have no change in the arrangement direction, but the common electrode ( The liquid crystal molecules 50b positioned between the 38 and the pixel electrode 40 have an operating characteristic arranged in parallel with the substrate by a horizontal electric field generated between the common electrode 38 and the pixel electrode 40.

The IPS type liquid crystal display device has a wide viewing angle characteristic and a good color reproducibility by driving liquid crystal molecules by a horizontal electric field.

2 is a plan view of a conventional IPS type liquid crystal display substrate.

As shown in the drawing, gate and data lines 111 and 141 orthogonal to each other are formed, and these two lines 111 and 141 are orthogonal to each other to define the pixel region P. The thin film transistor T is formed at the intersection of the gate and the data lines 111 and 141. Gate and data pads GP and DP are formed at one end of the gate and data lines 111 and 141.

The thin film transistor T includes a gate electrode 113 positioned in the gate wiring, a semiconductor layer pattern 131 on the gate electrode 113, a source electrode 143 connected to the data wiring 141, and a source electrode ( 143 and a drain electrode 145 spaced apart from each other. The semiconductor layer pattern 131 includes a pure amorphous silicon layer (a-Si) and an impurity amorphous silicon layer (n + a-Si).

The common wiring 116 is formed in the pixel region P in parallel with the gate wiring 111, and the common electrode 117 is branched from the common wiring 116. The common electrode 117 is formed of the same material and the same process as the gate wiring 113. The common electrodes 117 branched from the common wiring 116 are connected to each other through the connection wiring 118 at the top.

The pixel electrode 161 is connected to the drain electrode 145. The pixel electrode 161 is made of a transparent conductive metal material including indium-tin-oxide (ITO) and indium-zinc-oxide (IZO).

The pixel electrode 161 is connected to the metal pattern 149 formed on the connection line 118. The metal pattern 149 is made of the same material and the same process as the data line 141.

The drain electrode 145 and the common wiring 116 overlap each other to form a first storage capacitor C _ST1 . The metal pattern 149 overlaps the connection wiring 118 to form a second storage capacitor C _ST2 .

Therefore, when the thin film transistor T is in the off state, the charges charged in the pixel electrode 161 and the common electrode 117 are maintained until the next on state by the first and second storage capacitors C _ST1 and C _ST2 . .

However, the conventional IPS type liquid crystal display having the above configuration has a problem that the aperture ratio is reduced.

First, in order to form the second storage capacitor C _ST2 , separate connection lines and metal patterns 118 and 149 are formed to decrease the aperture ratio of the liquid crystal display.

Then, the common electrode 117 and the common wiring 116 are made of the same opaque metal material as that of the gate wiring, and the portion where the common electrode 117 and the common wiring 116 are formed becomes a portion which cannot display an image and thus liquid crystals. The aperture ratio of the display device is lowered.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is to provide an IPS type liquid crystal display device having a high opening ratio and a manufacturing method thereof.

In order to achieve the object as described above, the present invention, the gate wiring and data wiring crossing each other on the substrate; Common wiring spaced apart in parallel with the gate wiring; A common electrode connected to the common wiring; A gate electrode connected to the gate wiring; A source electrode connected to the data line, a drain electrode spaced apart from the source electrode; A pixel electrode spaced apart from the common electrode and connected to the drain electrode; A substrate for a liquid crystal display device includes a first auxiliary electrode connected to the drain electrode and formed on the common electrode adjacent to the data line to form a first storage capacitor.

The pixel electrode, the common electrode, and the first auxiliary electrode may be made of a transparent conductive metal material. The pixel electrode and the common electrode may be formed on the same layer as the gate line.

The display device may further include a second auxiliary electrode connecting the drain electrode and the first auxiliary electrode, and the second auxiliary electrode, the drain electrode, and the common wiring may form a second storage capacitor.

In addition, the first auxiliary electrode may have a narrower width than the common electrode.

In another aspect, the present invention, forming a gate wiring, a gate electrode connected to the gate wiring, a common wiring, a common electrode connected to the common wiring, and a pixel electrode spaced apart from the common electrode on a substrate Wow; A gate insulating layer, a semiconductor layer pattern, a data line crossing the gate line, a source electrode connected to the data line, a drain electrode spaced apart from the source electrode, and connected to the pixel electrode on the substrate on which the gate electrode is formed. Forming a; Forming a protective film on the substrate on which the drain electrode is formed; And forming a first auxiliary electrode connected to the drain electrode and above the common electrode adjacent to the data line.

The pixel electrode, the common electrode, and the first auxiliary electrode may be made of a transparent conductive metal material.

The drain electrode may further include forming a second auxiliary electrode formed on the common wiring and connecting the drain electrode and the first auxiliary electrode. Forming first and second contact holes exposing the drain electrode and a third contact hole exposing the pixel electrode in the passivation layer, and connecting the drain electrode and the pixel electrode through the first and third contact holes; The method may further include forming a pixel connection pattern, wherein the second auxiliary electrode may contact the drain electrode through the second contact hole.

In addition, the first auxiliary electrode may have a narrower width than the common electrode.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

3A, 4A, 5A, 6A, and 7A are plan views illustrating a method of manufacturing a substrate for an IPS type liquid crystal display device according to an exemplary embodiment of the present invention. 3B, 4B, 5B, 6B, and 7B are cross-sectional views taken along cut lines IIIb-IIIb, IVb-IVb, Vb-Vb, VIb-VIb, and VI-Bb of FIGS. 3A, 4A, 5A, 6A, and 7A, respectively. . 3C, 4C, 5C, 6C, and 7C are shown along the cut lines IIIc-IIIc, IVc-IVc, Vc-Vc, VIc-VIc, and Vc-VIIc of FIGS. 3A, 4A, 5A, 6A, and 7A, respectively. It is a cross section. 3D, 4D, 5D, 6D, and 7D are shown along the cut lines IIId-IIId, IVd-IVd, Vd-Vd, VId-VId, and Vd-Vd of FIGS. 3A, 4A, 5A, 6A, and 7A, respectively. It is a cross section. 3e, 4e, 5e, 6e, and 7e are shown along cut lines IIIe-IIIe, IVe-IVe, Ve-Ve, VIe-VIe, and VIIe-VIIe of FIGS. 3a, 4a, 5a, 6a, and 7a, respectively. It is a cross section.

First, as shown in FIGS. 3A, 3B, 3C, 3D, and 3E, first and second metal films are sequentially formed on the substrate 200. The first metal layer, which is a lower layer, uses a transparent conductive metal material including indium-tin-oxide (ITO) and indium-zinc-oxide (IZO). The second metal film includes copper (Cu), copper alloy (Cu alloy), aluminum (Al), aluminum alloy (Al alloy), chromium (Cr), molybdenum (Mo), tungsten (W), tantalum (Ta) Use metal materials. Meanwhile, a plurality of metal films may be further deposited on the first and second metal films.

Next, the first and second metal films are patterned in a first mask process to form a gate wiring 211, a gate electrode 213, a gate pad electrode 215, a common wiring 216, a common electrode 217, and a pixel electrode ( 219).

Next, the second metal film of the common electrode 217 and the pixel electrode 219 is removed. In this way, the common electrode 217 and the pixel electrode 219 are made of one film made of a transparent conductive metal material.

The common electrode 217 and the pixel electrode 219 have a zig-zag shape that is bent once and are spaced apart from each other in parallel. Meanwhile, the common electrode 217 and the pixel electrode 219 may have a zigzag shape bent a plurality of times.

Next, as shown in FIGS. 4A, 4B, 4C, 4D, and 4E, the gate insulating film 220, the semiconductor layer 230, and the third metal film 240 are formed on the substrate on which the gate wiring 211 or the like is formed. Form.

The gate insulating layer 220 is an inorganic insulating material including silicon oxide (SiO ₂ ) and silicon nitride (SiN _X ), or an organic insulating material including benzocyclobutene (BCB) and acrylic resin. Is done.

The semiconductor layer 230 includes a lower pure amorphous silicon layer 230a (a-Si) and an upper impurity amorphous silicon layer 230b (n + a-Si).

The third metal layer 240 may be formed of copper (Cu), copper alloy (Cu alloy), aluminum (Al), aluminum alloy (Al alloy), chromium (Cr), molybdenum (Mo), tungsten (W), and tantalum (Ta). It is made of a metal material containing.

Next, the photoresist is applied and patterned on the third metal film 240 to form the photoresist pattern 300. The photoresist may use a positive type in which a portion of light is developed and a negative type in which a portion of light is not developed. The photoresist pattern 300 is formed at a portion where the data line, the source and drain electrodes, and the data pad electrode are to be formed.

In particular, the photoresist pattern 300 formed on the portion where the source and drain electrodes are to be formed is formed to have a thickness of the center portion smaller than that of the peripheral portion. When the semi-transmissive film of a mask (not shown) is corresponded to the center portion and exposed, a photoresist pattern 300 having different thicknesses is formed on the gate electrode 213 as shown in the figure.

Next, the third metal layer 240 and the semiconductor layer 230 are etched along the photoresist pattern 300. The third metal layer 240 is etched by a wet etch method, and the semiconductor layer 230 is etched by a dry etch method. Accordingly, a source / drain metal pattern (not shown) and a semiconductor layer pattern (not shown) are formed on the gate electrode 213.

Next, by removing the photoresist pattern 300 to a predetermined thickness from the surface by an ashing process, all of the center portion of the photoresist pattern 300 positioned on the gate electrode 213 is removed. The source / drain metal pattern is exposed and the peripheral portion remains to a certain thickness.

Next, the exposed source / drain metal pattern is removed by a dry etching method, and an upper impurity amorphous silicon layer 230b of the semiconductor layer pattern is removed by a dry etching method.

By the second mask process as described above, as shown in FIGS. 5A, 5B, 5C, 5D, and 5E, a channel CH is formed in the semiconductor layer, and the source and drain electrodes 243 and 245 spaced apart from each other. Is formed. The data line 241, the data pad electrode 247, and the semiconductor layer pattern 231 are formed.

The semiconductor layer pattern 231 is also disposed under the data line 241 and the data pad electrode 247. The drain electrode 245 is positioned above the common wiring 216.

The gate electrode 213, the semiconductor layer pattern 231 formed on the gate electrode 213, and the source and drain electrodes 243 and 245 form a thin film transistor T.

The gate wiring 211 and the data wiring 241 which cross each other define the pixel region P. As shown in FIG.

In addition, the data line 241 has a bent shape like the common electrode and the pixel electrodes 217 and 219. Since the data line 241 has the same shape as the common electrode 217, the space between the data line 241 and the common electrode 217 is minimized.

Next, as shown in FIGS. 6A, 6B, 6C, 6D, and 6E, the protective film 250 is coated on the substrate on which the data line 241 and the like are formed, and patterned through a third mask process. Three, four, five contact holes 251, 252, 253, 254, and 255 are formed. The passivation layer 250 is made of an inorganic insulating material including silicon oxide (SiO ₂ ) and silicon nitride (SiN _X ), or an organic insulating material including benzocyclobutene (BCB) and acrylic resin. .

The first and second contact holes 251 and 252 may expose the drain electrode 245, the third contact hole 253 may expose the pixel electrode 219, and the fourth contact hole 254 may be a gate pad. The electrode 215 is exposed, and the fifth contact hole 255 exposes the data pad electrode 247. In particular, the third and fourth contact holes 253 and 254 are formed by etching the passivation layer 250 and the gate insulating layer 220.

Next, as shown in FIGS. 7A, 7B, 7C, 7D, and 7E, indium-tin-oxide (ITO) and indium-zinc-oxide on the protective film 250 are shown. oxide (IZO) is deposited and patterned through a fourth mask process to form the first and second auxiliary electrodes 261 and 262, the pixel connection pattern 265, the gate pad electrode terminals 267 and data. The pad electrode terminal 268 is formed.

The first auxiliary electrode 261 is disposed on the drain electrode 245 and is connected to the drain electrode 245 through the first contact hole 251.

The first auxiliary electrode and the drain electrodes 261 and 245, the common wiring 216, and the gate insulating layer 220 and the semiconductor layer pattern 231, which serve as dielectrics therebetween, form the first storage capacitor C _ST1 . Configure.

The second auxiliary electrode 262 is positioned above the common electrode 217 adjacent to the data line 241. The second auxiliary electrode 262 is formed along the shape of the common electrode 217 adjacent to the data line 241. The second auxiliary electrode 262, the common electrode 217 adjacent to the data line 241, and the gate insulating layer 220 and the protective layer 250 serving as a dielectric between the second storage capacitor C _{ST2 are} formed. Will be constructed.

The width of the second auxiliary electrode 262 may be smaller than that of the common electrode 217 adjacent to the data line 241. Since the second auxiliary electrode 262 is applied with the same signal as that applied to the data line and the pixel electrodes 241 and 219, the width of the second auxiliary electrode 262 is equal to the width of the data line 241 to prevent signal distortion. It may be formed smaller than the width of the common electrode 217 adjacent to the.

The pixel connection pattern 265 contacts the drain electrode 245 through the second contact hole 252 and the pixel electrode 219 through the third contact hole 253 to contact the drain electrode 245 and the pixel. The electrode 219 is electrically connected.

The gate pad electrode terminal 267 and the data pad electrode terminal 268 are in contact with the gate pad electrode 215 and the data pad electrode 247 through fourth and fifth contact holes, respectively. The gate pad electrode terminal 267 and the data pad electrode terminal 268 receive a gate signal and a data signal from the outside, respectively. The applied gate signal and data signal are transferred to the gate line 211 and the data line 241 through the gate pad electrode 215 and the data pad electrode 247, respectively.

The gate pad electrode terminal 267 and the gate pad electrode 215 constitute a gate pad GP, and the data pad electrode terminal 268 and the data pad electrode 247 constitute a data pad DP.

Through the process as described above to produce a substrate for the IPS type liquid crystal display device according to an embodiment of the present invention.

As shown in FIG. 8, the opening between the pixel electrode 219 and the common electrode 217 is divided into two domains D1 and D2 having different directions of an electric field formed between the two electrodes 217 and 219. You lose. Since the two domains D1 and D2 have different directions of electric fields, the arrangement of liquid crystals located in the two domains D1 and D2 also varies when an electric field is applied. The two domains D1 and D2 are bent portions. Since the structures are symmetrical with each other, the optical characteristics through the two domains D1 and D2 are compensated for each other, thereby improving the viewing angle characteristic of the liquid crystal display.

In addition, since a second storage capacitor (see C _ST2 of FIG. 2) is positioned above the conventional IPS type liquid crystal display substrate, an image cannot be displayed, thereby reducing the aperture ratio. Since the storage capacitor C _ST2 is not positioned at the upper portion as in the related art, the storage capacitor C _ST2 is positioned at the portion where the common electrode 217 adjacent to the data line 241 is formed so that the upper portion can be used as a portion capable of displaying an image. The aperture ratio is improved.

Further, the pixel electrode 219 and the common electrode 217 are formed by forming the common electrode, the pixel electrodes 217 and 219, and the second auxiliary electrode 262 constituting the second storage capacitor C _ST2 with a transparent conductive metal material. Can be used as a portion capable of displaying an image, thereby improving the aperture ratio.

In addition, since the second storage capacitor C _ST2 is formed along the common electrode 217 adjacent to the data line 241, the charging capacity is increased. Therefore, since the first storage capacitor C _ST1 can be made small, the portion capable of displaying an image can be increased such that the width of the common wiring 216 can be reduced, and the aperture ratio can be improved.

In addition, since the data line 241 has the same shape as the common electrode 217, the space between the data line 241 and the common electrode 217 adjacent to the data line 241 may be minimized to improve the aperture ratio.

Embodiment of the present invention as described above is an example of the present invention, various modifications are possible. When such modifications are included in the spirit of the present invention, it is obvious to those skilled in the art that they fall within the scope of the present invention. The scope of the invention will be apparent from the claims.

According to the present invention, the aperture ratio of the IPS type liquid crystal display device can be increased by forming the pixel electrode and the common electrode using a transparent conductive metal material and configuring the storage capacitor in a portion where the common electrode adjacent to the data line is formed.

1A and 1B are cross-sectional views showing the arrangement of liquid crystal molecules in a voltage off / on state in an IPS type liquid crystal display device, respectively.

2 is a plan view showing a conventional substrate for an IPS type liquid crystal display device.

2A and 2B are schematic cross-sectional views showing arrangement states of liquid crystal molecules with voltages off and on in an IPS type liquid crystal display device, respectively.

3A, 4A, 5A, 6A, and 7A are plan views illustrating a method of manufacturing a substrate for an IPS type liquid crystal display device according to an embodiment of the present invention.

3B, 4B, 5B, 6B, and 7B are cross-sectional views taken along cut lines IIIb-IIIb, IVb-IVb, Vb-Vb, VIb-VIb, and VI-Bb of FIGS. 3A, 4A, 5A, 6A, and 7A, respectively.

3C, 4C, 5C, 6C, and 7C are cross-sectional views taken along cut lines IIIc-IIIc, IVc-IVc, Vc-Vc, VIc-VIc, and VIIc-VIIc of FIGS. 3A, 4A, 5A, 6A, and 7A, respectively.

3D, 4D, 5D, 6D, and 7D are cross-sectional views taken along cut lines IIId-IIId, IVd-IVd, Vd-Vd, VId-VId, and Vd-Vd of FIGS. 3A, 4A, 5A, 6A, and 7A, respectively.

3E, 4E, 5E, 6E, and 7E are cross-sectional views taken along cut lines IIIe-IIIe, IVe-IVe, Ve-Ve, VIe-VIe, VIe-VIIe of FIGS. 3A, 4A, 5A, 6A, and 7A, respectively.

8 is a plan view showing a substrate for a liquid crystal display device manufactured according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

200: substrate 211: gate wiring

213: gate electrode 216: common wiring

217: common electrode 219: pixel electrode

241: data wiring C _ST1 , C _ST2 : first and second storage capacitor

Claims (10)

Gate wiring and data wiring crossing each other on the substrate; Common wiring spaced apart in parallel with the gate wiring; A common electrode connected to the common wiring; A gate electrode connected to the gate wiring; A source electrode connected to the data line, a drain electrode spaced apart from the source electrode; A pixel electrode spaced apart from the common electrode and connected to the drain electrode; A first auxiliary electrode connected to the drain electrode and formed on the common electrode adjacent to the data line to form a first storage capacitor; Liquid crystal display substrate comprising a. The method of claim 1, The pixel electrode, the common electrode, and the first auxiliary electrode are made of a transparent conductive metal material. The method of claim 2, And the pixel electrode and the common electrode are formed on the same layer as the gate line. The method of claim 1, And a second auxiliary electrode connecting the drain electrode and the first auxiliary electrode, wherein the second auxiliary electrode and the drain electrode and the common wiring form a second storage capacitor. The method of claim 1, The first auxiliary electrode has a narrower width than the common electrode. Forming a gate wiring, a gate electrode connected to the gate wiring, a common wiring, a common electrode connected to the common wiring, and a pixel electrode spaced apart from the common electrode on a substrate; A gate insulating layer, a semiconductor layer pattern, a data line crossing the gate line, a source electrode connected to the data line, a drain electrode spaced apart from the source electrode, and connected to the pixel electrode on the substrate on which the gate electrode is formed. Forming a; Forming a protective film on the substrate on which the drain electrode is formed; Forming a first auxiliary electrode on the common electrode connected to the drain electrode and adjacent to the data line; Substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 6, The pixel electrode, the common electrode, and the first auxiliary electrode are made of a transparent conductive metal material. The method of claim 6, The drain electrode is formed on the common wiring, and further comprising the step of forming a second auxiliary electrode connecting the drain electrode and the first auxiliary electrode. The method of claim 8, Forming first and second contact holes exposing the drain electrode and a third contact hole exposing the pixel electrode in the passivation layer, and connecting the drain electrode and the pixel electrode through the first and third contact holes; The method may further include forming a pixel connection pattern. The second auxiliary electrode is in contact with the drain electrode through the second contact hole. The method of claim 6, The first auxiliary electrode has a narrower width than the common electrode.