KR101785914B1 - In-Plane Switching Mode - Google Patents

Abstract

The present invention provides a liquid crystal display comprising: a gate wiring and a data wiring crossing each other on a substrate to define a pixel in a matrix form; A common wiring line including a vertical portion parallel to the data line and formed in the pixel, a jumping portion connecting the vertical portion of the adjacent pixel, and an extending portion extending from the vertical portion to the adjacent pixel; A thin film transistor connected to the gate wiring and the data wiring; A pixel electrode connected to the thin film transistor; And a common electrode formed to be offset from the pixel electrode.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display (LCD)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a common wiring of a liquid crystal display device of a lateral electric field type.

2. Description of the Related Art [0002] With the development of an information society, demands for a display device for displaying images have been increasing in various forms. Recently, a liquid crystal display (LCD), a plasma display panel (PDP) Various flat display devices such as an organic light emitting diode (OLED) have been utilized.

Of these flat panel display devices, liquid crystal display devices are widely used today because they have advantages of miniaturization, weight reduction, thinness, and low power driving. On the other hand, an active matrix type liquid crystal display device in which a large number of pixels are arranged in a matrix and a switching transistor is formed in each of these pixels is widely used today.

In general, TN (Twisted Nematic) liquid crystal has been mainly applied to such a liquid crystal display device. However, in the TN liquid crystal display device, since the liquid crystal is driven by the vertical electric field between the common electrode and the pixel electrode, the light transmissivity varies depending on the viewing angle of up, down, left, and right.

In order to solve the above problems, an in-plane switching (IPS) liquid crystal display device has been proposed in which a liquid crystal is driven by a transverse electric field.

Fig. 1 is a schematic view of a liquid crystal panel of a general transverse electric field type liquid crystal display device, Fig. 2 is a diagram showing the pixel structure of a general transverse electric field type liquid crystal display device, and Fig. 3 is a cross- Circuit diagram.

The liquid crystal panel is provided with a plurality of gate lines GL1, GL2, ... extending along the row line direction and a plurality of data lines DL extending along the column line direction, And a plurality of common wirings CL arranged in parallel with the gate wirings GL1, GL2, ... in the row direction on the liquid crystal panel. The pixel P is defined by the intersection of the gate lines GL1, GL2, ... and the data line DL. In the pixel P, a thin film transistor T connected to the gate lines GL1, GL2, ... and the data line DL is formed. The thin film transistor T is connected to the pixel electrode 2. In each pixel P, a common electrode 1 forming a transverse electric field with the pixel electrode 2 is formed. The common electrode 1 is extended from the common wiring CL and receives a common voltage transmitted through the common wiring CL. At this time, one side formed corresponding to each pixel P is connected to the common wire extension CL0 and the same common voltage is applied. A transverse electric field is formed between the pixel electrode 2 and the common electrode 1 to drive the liquid crystal.

The liquid crystal located between the pixel electrode 2 and the common electrode 1 and between these electrodes constitutes a liquid crystal capacitor Clc. Each pixel P further includes a storage capacitor Cst which serves to store the data voltage applied to the pixel electrode 2 until the next frame.

However, in a general transverse electric-field liquid crystal display device, the light transmittance is low due to the common wiring formed at the lower end of each pixel. Specifically, although a storage capacitor for storing a data voltage until the next frame is unnecessary by a high-speed driving of a liquid crystal display in recent years, there is a problem that the aperture ratio of a pixel is further reduced by further constituting a storage capacitor.

In addition, in order to minimize the voltage drop and supply the common voltage, the common wiring extension part CL0 is formed to have a relatively large thickness as compared with other wiring lines. Since the common wiring extension part CL0 is formed in the gate pad part, In the narrow bezel model in which the display area of the panel is maximized, space for image display is insufficient.

The present invention has a problem of providing a transverse electric field type liquid crystal display device capable of increasing transmittance and further securing a display region of a liquid crystal panel.

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In order to achieve the above-mentioned object, the present invention provides a liquid crystal display device comprising: a gate wiring and a data wiring crossing each other on a substrate to define a pixel in a matrix form; A common wiring including a jumping portion that is parallel to the data wiring and connects a vertical portion formed in the pixel and a vertical portion of the pixel vertically adjacent to the data wiring and an extension portion extending from the vertical portion to the horizontally adjacent pixel; A thin film transistor connected to the gate wiring and the data wiring; A pixel electrode connected to the thin film transistor; And a common electrode formed to be offset from the pixel electrode.

A gate insulating layer deposited on the upper surface of the common wiring and the gate wiring, and a protective layer applied to the upper surface of the data wiring and the thin film transistor.

The gate line, the vertical portion and the extension portion are formed of the same layer and the same material, and the pixel electrode, the common electrode, and the jumping portion are formed of the same layer and the same material.

The gate insulation layer and the protection layer may include a first contact hole for electrically connecting the connection portion and the common electrode to each other and a first jumping hole and a second jumping hole for connecting the vertical portion and the jumping portion to each other, And a second contact hole for electrically connecting the pixel electrode and the drain electrode to each other is formed in the protective layer.

Forming a gate wiring on the substrate on which the pixel is defined, an extension portion extending from the vertical portion of the common wiring parallel to the data wiring and formed in the pixel and horizontally adjacent to the vertical portion; Forming a gate insulating film on the entire surface of the gate wiring and the common wiring; Forming a data line crossing the gate line over the gate insulating layer; Forming a thin film transistor connected to the gate wiring and the data wiring; Forming a protective layer on the data wiring and on the entire surface of the thin film transistor; Forming a pixel electrode connected to the thin film transistor on the protection layer, a common electrode connected to the vertical portion and the extending portion, and a jumping portion connecting the vertical portion, the method comprising: to provide.

The gate line, the vertical portion and the extension portion are formed of the same layer and the same material, and the pixel electrode, the common electrode, and the jumping portion are formed of the same layer and the same material.

The gate insulation layer and the protection layer may include a first contact hole for electrically connecting the connection portion and the common electrode to each other and a first jumping hole and a second jumping hole for connecting the vertical portion and the jumping portion to each other, And a second contact hole for electrically connecting the pixel electrode and the drain electrode to each other is formed in the protective layer.

The transverse electric field type liquid crystal display device according to the present invention eliminates the common wiring formed at the lower end of the pixel, thereby eliminating unnecessary storage capacitors and enhancing the light transmittance of the pixel.

Further, by removing the common wiring extension portion and using the gate pad portion of the liquid crystal panel for image display, it is possible to maximize the display region and secure a liquid crystal display device of a narrow-bezel model.

1 is a schematic sectional view showing a conventional transverse electric field type liquid crystal display device.
BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display device.
3 is a pixel equivalent circuit diagram of a conventional transverse electric field type liquid crystal display device.
4 is a sectional view of a transverse electric field type liquid crystal display device according to an embodiment of the present invention.
5A and 5B are diagrams schematically showing the arrangement of liquid crystal layers when the liquid crystal display device is turned on and off.
6 is a schematic cross-sectional view of a transverse electric field type liquid crystal display device according to an embodiment of the present invention.
7 is a pixel equivalent circuit diagram of a transverse electric field type liquid crystal display device according to an embodiment of the present invention.
8 is a schematic view showing a pixel structure of a transverse electric field type liquid crystal display device according to an embodiment of the present invention.
9 is a cross-sectional view of a lower substrate according to an embodiment of the present invention.

Hereinafter, a transverse electric field type liquid crystal display device according to an embodiment of the present invention will be described with reference to the drawings.

4 is a schematic cross-sectional view of a transverse electric field type liquid crystal display device according to an embodiment of the present invention.

A transverse electric field type liquid crystal display 100 according to an embodiment of the present invention includes an upper substrate 200 as a color filter substrate and a lower substrate 300 as an array substrate, And a liquid crystal layer 400 is interposed between the upper and lower substrates 200 and 300.

The common electrode 310 and the pixel electrode 320 are formed on the same plane on the lower substrate 300. The liquid crystal layer 400 is formed on the common electrode 310 and the pixel electrode 320, (L).

5A and 5B are cross-sectional views illustrating the on and off states of the transverse electric field type liquid crystal display device according to the embodiment of the present invention, respectively.

FIG. 5A is a cross-sectional view showing a liquid crystal alignment state in an ON state in which a voltage is applied, and FIG. 5B is a cross-sectional view illustrating a liquid crystal alignment state in an OFF state in which no voltage is applied.

5A, there is no phase change of the liquid crystal molecules 400a at the positions corresponding to the common electrode 310 and the pixel electrode 320 in the ON state. On the other hand, the liquid crystal molecules 400b located between the common electrode 310 and the pixel electrode 320 have a horizontal electric field L formed by applying a voltage between the common electrode 310 and the pixel electrode 320, In the same direction as the horizontal electric field (L).

That is, since the liquid crystal is rotated by the horizontal electric field L in the transverse electric field type liquid crystal display device 100, the viewing angle becomes wide. Accordingly, when the transverse electric-field-type liquid-crystal display device 100 is viewed from the front, it can be seen in the direction of about 80 to 85 degrees in the up / down / left / right directions without reversal.

5B, since the horizontal electric field L is not formed between the common electrode 310 and the pixel electrode 320 in the OFF state, the alignment state of the liquid crystal layer 400 does not change.

Hereinafter, a transverse electric field type liquid crystal display device according to an embodiment of the present invention will be described in more detail with reference to FIGS. 6 to 8. FIG.

6 is a schematic view of a lower substrate 300 of a transverse electric field type liquid crystal display device 100 according to an embodiment of the present invention. FIG. 7 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention, Is a plan view showing a pixel region in a lower substrate 300 of a transverse electric field type liquid crystal display device 100 according to an embodiment of the present invention.

6, a plurality of gate lines GL1, GL2, ... extending in a row line direction and spaced apart from each other by a predetermined distance are formed on the lower substrate 300, A plurality of data lines DL1, DL2, ... extending in the Y-direction are arranged. The gate lines GL1, GL2, ... and the data lines DL1, DL2, ... intersect each other to define a pixel P in the form of a matrix.

Further, on the lower substrate 300, a plurality of common wirings CL1, CL2, ... are located. More specifically, each of the common lines CL1, CL2, ... includes a plurality of vertical portions VP formed in the pixel P region in parallel with the data lines DL1, DL2, A jumping part JP connected to the pixel P and extending between the pixel P and the pixel P horizontally adjacent to the vertical part VP. This will be described later in more detail.

7, each pixel P may include a thin film transistor T, a pixel electrode 320, a common electrode 310, and a liquid crystal capacitor Clc.

The thin film transistor T is formed at the intersection of the gate lines GL1, GL2, ... and the data lines DL1, DL2, .... The pixel electrode 320 of FIG. 8 is connected to the thin film transistor T and the common electrode 310 of FIG. 8 is connected to the corresponding common wiring CL1, CL2,... As described above, the pixel electrode 320 and the common electrode 310 are formed on the lower substrate 300 to form a transverse electric field L to drive the liquid crystal layer located therebetween. The liquid crystal capacitor Clc includes a pixel electrode 320, a common electrode 310, and a liquid crystal layer disposed between the pixel electrode 320 and the common electrode 310.

Hereinafter, the structure of the pixel P according to the embodiment of the present invention will be described in more detail with reference to FIG.

The first and second gate lines GL1 and GL2 arranged in the row direction and the first and second data lines DL1 and DL2 arranged in the column direction are vertically crossed and arranged in the unit pixel P).

Also, first and second common lines CL1 and CL2 parallel to the first and second data lines DL1 and DL2 are located. Here, the first and second common wirings CL1 and CL2 are composed of a vertical portion VP, a jumping portion JP and an extended portion EP.

First, the vertical portion VP is formed in the pixel P region in parallel with the data lines DL1 and DL2. Also, for example, the data lines DL1 and DL2 are formed on the left side.

Concretely, for example, the vertical portion VP of the first common wiring CL1 is parallel to the first data line DL1 and is located on the left side of the first data line DL1 to be formed in the pixel P region do. That is, the vertical portion VP of the first common wiring CL1 is formed in the pixel P defined by the first data wiring DL1 and the first gate wiring and the second gate wiring GL1 and GL2.

Likewise, the vertical portion VP of the second common line CL2 is formed in the pixel P region in parallel with the second data line DL2 and on the left side of the second data line DL2. That is, the vertical portion VP of the second common wiring CL2 is formed in the pixel P defined by the second data wiring DL2 and the first gate wiring and the second gate wiring GL1 and GL2.

The jumping portion JP is formed between the pixel P regions connected to the vertical portion VP. That is, a plurality of vertical portions VP constituting corresponding common lines CL1 and CL2 are connected so as not to overlap with the gate lines GL1 and GL2.

More specifically, for example, the jumping portion JP of the first common line CL1 corresponding to the first data line DL1 is connected to the first data line DL1 and the first gate line GL1 Is connected to a vertical portion VP formed in each pixel P region between the pixel P region and the pixel P region defined by the first data line DL1 and the second gate line GL2. More specifically, the upper end of the jumping portion JP of the first common wiring CL1 is connected to the lower end of the vertical portion VP formed in the pixel P region defined by the first gate wiring GL1. On the other hand, the lower end of the jumping portion JP of the first common wiring CL1 is connected to the upper end of the vertical portion VP formed in the pixel P region defined by the second gate wiring GL2. Thus, the jumping portion JP connects the vertical portion VP of the first common wiring CL1 without overlapping with the first and second gate wirings GL1 and GL2.

Likewise, the jumping portion JP of the second common line CL2 corresponding to the second data line DL2 is connected to the second data line DL2 and the pixel P region defined by the first gate line GL1 And the pixel P region defined by the second data line DL2 and the second gate line GL2 are connected to the vertical portion VP formed in the pixel P region. More specifically, the upper end of the jumping portion JP of the second common line CL2 is connected to the lower end of the vertical portion VP formed in the pixel P region defined by the first gate line GL1. On the other hand, the lower end of the jumping portion JP of the second common wiring CL2 is connected to the upper end of the vertical portion VP formed in the pixel P region defined by the second gate wiring GL2. Thus, the jumping portion JP connects the vertical portion VP of the second common wiring CL2 without overlapping with the first and second gate wirings GL1 and GL2.

The extension part EP extends from the vertical part VP to the pixel P horizontally adjacent thereto. Accordingly, the extended portion EP is connected to the common electrode 310 formed in the adjacent pixel P region across the data lines DL1 and DL2.

Specifically, for example, the extended portion EP of the second common line CL2 is connected to the vertical portion VP formed in the pixel P region defined by the first data line DL1 and the first gate line GL1 And is connected to the common electrode 310 formed in the pixel P region defined by the second data line DL2 and the first gate line GL1. Thus, the extended portion EP of the second common line CL2 intersects with the second data line DL2. At this time, the extension part EP can extend from the upper end of the vertical part VP, for example.

Further, the extending portion EP can further extend vertically at the end of the extending portion EP, that is, at the adjacent pixel P. Thus, the end of the extended portion EP becomes parallel to the data lines DL1 and DL2. At this time, the portion further connected vertically in the adjacent pixel (P) region may be, for example, a dummy wiring.

Specifically, for example, the extended portion EP of the second common wiring CL2 extends vertically further in the adjacent pixel P region defined by the second data wiring DL2 and the first gate wiring GL1 do. Accordingly, the extended portion EP can be formed in, for example, a shape of ".".

A gate electrode 10, a semiconductor layer (not shown), a source and a drain (not shown) are formed at intersections of the first and second gate lines GL1 and GL2 and the first and second data lines DL1 and DL2. a drain electrode 20 and a drain electrode 30 are formed. At this time, the gate electrode 10 is formed as a part of the first and second gate lines GL1 and GL2, and the source electrode 20 is formed by branching from the first and second data lines DL1 and DL2.

The pixel P includes a plurality of pixel electrodes 320 electrically connected to the drain electrode 30 through a first contact hole 40 and a plurality of pixel electrodes 320 arranged in parallel with the pixel electrode 320, And a plurality of common electrodes 310 electrically connected to the first and second common lines CL1 and CL2 through the second contact holes 50 are formed. The first and second common wirings CL1 and CL2 electrically connected to each other through the common electrode 310 and the second contact hole 50 may be extended portions EP, for example.

The common lines CL1 and CL2 and the common electrode 310 may be formed in various layers and various shapes. In the embodiment of the present invention, the common lines CL1 and CL2 and the common electrode 310 are formed on the same plane And the common electrode 310 is formed on the common wiring CL1 and CL2.

The outermost common electrode 310 closest to the data lines DL1 and DL2 and disposed at the outermost periphery of the pixel P is connected to the lower common wiring line CL1, CL2. ≪ / RTI >

The width of the outermost common electrode 310 may be wider than the width of the central common electrode 310 formed at the center of the pixel P apart from the data lines DL1 and DL2. The reason why the width of the outermost common electrode 310 is made larger than the width of the central common electrode 310 is to minimize defects such as crosstalk.

That is, the data lines DL1 and DL2 affect an electric field generated between the outermost common electrode 310 and the adjacent pixel electrode 320, thereby causing crosstalk. At this time, if the width of the outermost common electrode 310 is formed to be wider than the width of the central common electrode 310 and disposed between the data lines DL1 and DL2 and the pixel electrode 320, the occurrence of crosstalk can be minimized .

The spacing between the data lines DL1 and DL2 and the outermost common electrode 310 on both sides of the data lines DL1 and DL2 in the structure of the lower substrate 300 corresponds to a light leakage region in which the liquid crystal is abnormally oriented when a voltage is applied.

For example, the black matrix may be formed on the color filter substrate 200 or the first and second common wirings CL1 and CL2 may be formed on the data lines DL1 and DL2 and the pixel electrode 320, May be formed so as to overlap with each other.

In addition, the vertical portions VP of the first common wiring CL1 of the pixels P corresponding to one column line are connected to each other. The vertical part VP may be connected by the jumping part JP and the jumping part JP may be formed of the same layer and the same material as the pixel electrode 320. [ For this, first and second jumping holes 60 and 70 are formed on the upper and lower sides of the vertical part VP and the jumping part JP is provided with first and second jumping holes 60, 70 to the vertical portion VP.

At this time, the vertical portion VP can be formed of the same layer and the same material as the gate lines GL1 and GL2.

Specifically, for example, a first jumping hole 60 is formed on the upper side of the vertical portion VP of the first common wiring CL1, and the vertical portion VP included in the pixel P of the previous row line in the same column line (VP). A second jumping hole 70 is formed below the vertical portion VP of the first common wiring CL1 and is connected to the vertical portion VP included in the pixel P of the next row line.

That is, the vertical part VP is connected to the gate lines GL1 and GL2 so as not to overlap with the gate lines GL1 and GL2 using the jumping parts JP formed in different layers.

Here, although not shown in the drawing, the outermost common electrode 310 adjacent to the data lines DL1 and DL2 may be connected to neighboring pixels P for a more stable structure.

Hereinafter, the cross section of the lower substrate 300 of the transverse electric field type liquid crystal display device according to the embodiment of the present invention will be described in more detail with reference to FIG.

9 is a cross-sectional view of a lower substrate 300 according to an embodiment of the present invention.

(Al), aluminum (AlNd), chromium (Cr), molybdenum (Mo), molybdenum alloy, copper (Cu) or the like is formed on the entire surface of the transparent insulating substrate (s) , A copper alloy is deposited to form a gate metal film, a photoresistor is coated on the gate metal film, exposure is performed using a mask having a transmission region and a blocking region, the exposed photoresist is developed, A mask process such as etching the exposed metal material is performed.

Then, the gate metal film is etched using the patterned photoresist as a mask to form the gate electrode 10 and the vertical portion VP. At this time, although not shown, gate wirings GL1, GL2, ... and extension parts EP are integrally formed in the gate electrode 10.

The gate insulating film 11 is formed by depositing an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx) on the entire upper surfaces of the gate wirings GL1, GL2, ...,

Next, pure amorphous silicon and impurity amorphous silicon are sequentially deposited on the gate insulating film 11 and the diffraction exposure or halftone exposure process is performed to form the channel layer 12, the ohmic contact layer 13, a source electrode 20 and a drain electrode 30 are formed at the same time to form a thin film transistor T.

At this time, data lines DL1, DL2, ... electrically connected to the source electrode 20 are formed. The data lines DL1, DL2, ... are connected to the source electrode 20 of the thin film transistor T so that the source electrode 20 is branched from the data lines DL1, DL2, ....

Next, an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx) is deposited on the entire upper surfaces of the data lines DL1, DL2, ... and the source and drain electrodes 20, 30, or benzocyclobutene BCB) or photo acryl is applied to form the protective layer 14. The protective layer 14 is formed by applying a photosensitive organic insulating material, such as BCB or photo acryl.

Here, a contact hole process is performed to open the drain electrode 30 and the gate pad and the data pad (not shown).

Also, in the contact hole process, it is preferable to form the jumping holes 70 to connect the vertical portions VP located in one column line, for example. This is because the connection of the vertical part VP uses the jumping part JP as described above. That is, in order to connect the vertical part VP and the jumping part JP, the gate insulating film 11 and the protective layer 14 are etched so that the vertical part VP can be opened.

The etching of the protective layer 14 and the gate insulating film 11 is an example and it is possible to expose the vertical portion VP by etching the gate insulating film 11 and the protective layer 14, To be clear to.

After the contact holes 40 and the jumping holes 70 are formed, a transparent conductive material such as indium tin oxide (ITO) or indium tin oxide (ITO) is deposited on the entire upper surface of the protective layer 14 on which the contact holes 40 are formed. - Zinc-oxide (IZO) is deposited and the mask process is performed to degum. A pixel electrode 320 connected to the drain electrode 30, and a common electrode 310 are formed.

At this time, the jumping part JP for connecting the vertical part VP located on one column line may be formed of a transparent conductive material such as aluminum (Al), an aluminum alloy (AlNd), chromium (Cr) (Mo), molybdenum alloy, copper (Cu), copper alloy, and the like.

The present invention has the following effects.

First, as the liquid crystal display device is driven at a high speed (for example, driving at 240 Hz), the liquid crystal display device does not need a separate storage capacitor configuration. That is, by the high-speed driving, the function of storing the data voltage applied to the pixel electrode until the next frame becomes unnecessary. Thus, by eliminating the common wiring at the lower end of the pixel located in the row line, the unnecessary structure of the storage capacitor can be omitted. As a result, by removing the common wiring at the lower end of the pixel, the light transmittance of each pixel of the liquid crystal panel can be increased.

Further, by removing the vertical common wiring extension portion for applying the common voltage to the liquid crystal panel, the gate pad portion can be utilized as the display region to the maximum extent. That is, conventionally, since the common wire extension portion is located in the gate pad portion, there is a problem that the gate pad portion is designed to be unnecessarily wide. As a result, there has been a limitation in shrinking the gate pad portion of the narrow bezel model. However, in the case of the present invention, it is possible to further secure the space required for the inner low-bezel model by deleting the common wiring extension portion.

The embodiment of the present invention described above is an example of the present invention, and variations are possible within the spirit of the present invention. Accordingly, the invention includes modifications of the invention within the scope of the appended claims and equivalents thereof.

310: common electrode 320: pixel electrode
VP: vertical part JP: jumping part EP: extension part
60: first jumping hole 70: second jumping hole

Claims (7)

A gate wiring and a data wiring crossing each other on the substrate to define a pixel in the form of a matrix;
A common wiring including a jumping portion connecting a vertical portion formed in the pixel and a vertical portion of the pixel vertically adjacent to the pixel, and an extension extending to the horizontally adjacent pixel;
A thin film transistor connected to the gate wiring and the data wiring;
A pixel electrode connected to the thin film transistor;
And a common electrode formed to be offset from the pixel electrode,
Wherein the extension extends to pixels horizontally adjacent to the data line in the same layer as the gate line and is connected to a common electrode of horizontally adjacent pixels through a first jumping hole,
Wherein the vertical portion extends parallel to the data line from one end of the extending portion and is located on the same layer as the gate line between the data line and the common electrode,
Wherein the jumping portion extends from the common electrode in the same layer as the common electrode and is connected through the vertical portion and the second jumping hole and is located between the data line and the common electrode,
And a common voltage applied to the common wiring is applied in a vertical direction like the data wiring.
The method according to claim 1,
A gate insulating film formed on the upper surface of the vertical portion and the gate wiring,
And a protective layer applied to the upper surface of the data line and the thin film transistor.
3. The method of claim 2,
Wherein the pixel electrode and the common electrode are formed of the same layer and the same material.
The method of claim 3,
A first contact hole for electrically connecting the pixel electrode and the drain electrode to each other is formed in the passivation layer, and a first contact hole for electrically connecting the extension and the common electrode to the gate insulating layer and the passivation layer, And the first jumping hole and the second jumping hole for connecting the vertical portion and the jumping portion are located.
The method according to claim 1,
Wherein the vertical portion is located apart from the data line and the common electrode.
The method according to claim 1,
And the jumping portion extends from the vertical portion, and is located between the data line and the pixel electrode.
The method according to claim 1,
And a dummy wiring parallel to the vertical part further extends at the other end of the extended part.

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