KR101201329B1 - Thin Film Transistor Array Substrate And Method For Fabricating The Same - Google Patents

Abstract

The present invention provides a TFT array substrate which is intended to simplify the process by forming a black matrix on a TFT array substrate without an additional mask process and simultaneously form the black matrix on the semiconductor layer of the thin film transistor so that no external light is incident on the channel layer. In the manufacturing method of the present invention, the TFT array substrate of the present invention is formed at the intersection of the gate wiring and data wiring vertically crossed to define a unit pixel, and the intersection of the gate wiring and the data wiring, the gate electrode, semiconductor layer, source / drain A thin film transistor comprising an electrode, a protective film formed on the front surface including the data line and the thin film transistor, a black matrix formed on the protective film so as to cover the semiconductor layer of the thin film transistor, and a drain of the thin film transistor on the protective film. Pixel field contacted with electrode , And a shield layer formed in a region between the data line and the pixel electrode.

Light leakage current, channel layer, diffraction exposure, black matrix

Description

TFT Film Substrate and Method for Manufacturing the Same {Thin Film Transistor Array Substrate And Method For Fabricating The Same}

1 is a cross-sectional view of a TFT array substrate according to the prior art.

2 is a cross-sectional view of a TFT array substrate having a BOA structure according to the prior art.

3 is a cross-sectional view of a TFT array substrate according to the present invention.

4A to 4G are process cross-sectional views of a TFT array substrate according to the present invention.

* Explanation of symbols on the main parts of the drawings

111: TFT array substrate 112a: gate electrode

113: gate insulating film 114: semiconductor layer

115: data wiring 115a: source electrode

115b: data electrode 116: protective film

117: pixel electrode 122: gate pad

125: data pad 132: storage electrode

135 photoresist 150 shield layer

152 black matrix 500 half-tone mask

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device (LCD), and more particularly, to a TFT array substrate having a black on array (BOA) structure having a black matrix on a substrate having a TFT array and a method of manufacturing the same. .

BACKGROUND ART Liquid crystal display devices, which have recently been spotlighted as flat panel display devices, have been actively researched due to their high contrast ratio, suitable for gray scale display or moving picture display, and low power consumption.

In particular, it can be manufactured with a thin thickness so that it can be used as an ultra-thin display device such as a wall-mounted TV in the future, and is light in weight and consumes significantly less power than a CRT CRT. It is being used as a next generation display device. In addition, since it is manufactured as a small panel and used as a mobile phone display, its use is various.

The liquid crystal display device includes a color filter layer array substrate as a first substrate and a thin film transistor array substrate as a second substrate, and a liquid crystal having dielectric anisotropy therebetween. With the structure formed, it is driven by displaying an image using the difference of the transmittance | permeability of the light which arises from the arrangement change of a liquid crystal.

Hereinafter, a manufacturing method of a TFT array substrate according to the prior art will be described with reference to the accompanying drawings.

1 is a cross-sectional view of a TFT array substrate according to the prior art, and FIG. 2 is a cross-sectional view of a TFT array substrate having a BOA structure according to the prior art.

In a typical liquid crystal display device, as shown in FIG. 1, a color filter layer array substrate 12 as an upper substrate and a TFT (Thin Film Transistor) array substrate 11 as a lower substrate are disposed to face each other, and a dielectric is disposed therebetween. The liquid crystal layer 50 having anisotropy is formed, and a thin film transistor (TFT) added to each pixel is switched through a pixel selection address line to apply a voltage to the pixel. To drive.

At this time, the color filter layer array substrate 12 is arranged in a predetermined order to implement a color (Red), green (Green), blue (Blue) color filter layer 32 and between the R, G, B cells It is composed of a black matrix 31 which serves to distinguish and block light, and a common electrode 33 for applying a voltage to the liquid crystal cell. The three colors constituting the color filter layer 32 are driven independently, and a color of one pixel is displayed by a combination thereof.

The TFT array substrate 11 includes a plurality of gate wirings (not shown) and data wirings 17, which are vertically intersected with the gate insulating film 15 serving as an insulating film therebetween to define a unit pixel, and the gate wirings. And a thin film transistor (TFT) disposed at an intersection point of the data line to control turn-on or turn-off of a voltage, and a thin film transistor (TFT) interposed between the thin film transistor (TFT) and an insulating film. The pixel electrode 19 for applying a voltage is provided.

In this case, the black matrix of the color filter layer array substrate 12 is formed at a position corresponding to the gate wiring, the data wiring, and the thin film transistor T where light leakage occurs, in consideration of the bonding margin between the color filter array substrate and the TFT array substrate. Widely formed with a certain margin on both sides at the position corresponding to the thin film transistor (T).

However, there is a problem in that light leakage phenomenon is not completely blocked because light passing in an oblique direction is leaked between the black matrices among the light supplied from the TFT array substrate. In addition, when the size of the black matrix becomes larger, the opening area of the device becomes smaller, so that there is a limit in reducing the size of the black matrix.

Accordingly, in order to improve the above problems, a black matrix on array (BOA) structure is proposed in which a black matrix is formed on a TFT array substrate.

In the case of the BOA structure liquid crystal display, as the overlap gap between the thin film transistor and the black matrix is narrowed, the light leakage phenomenon due to the light leakage current and the light source traveling in the diagonal direction from the backlight can be effectively blocked.

The liquid crystal display of the BOA structure includes a color filter layer array substrate having a color filter layer, a TFT array substrate having a black matrix and a thin film transistor simultaneously, and a liquid crystal layer interposed between the two substrates.

Specifically, on the TFT array substrate 91 of the BOA structure, as shown in FIG. 2, a black matrix 92 for preventing light leakage, a buffer layer 93 formed on the entire surface including the black matrix, and A thin film transistor (TFT), a storage capacitor (Cst) and a pixel electrode 94 formed on the buffer layer. The buffer layer is formed to insulate the black matrix and the thin film transistor from each other and to prevent a coupling phenomenon between the black matrix and the gate wiring.

As described above, the conventional BOA structure liquid crystal display device directly overlaps the black matrix 92 under the TFT to reduce the gap between the TFT and the black matrix, thereby completely eliminating light leakage without forming a large size of the black matrix. It is possible to block and at the same time prevent narrowing of the opening area by the black matrix.

However, the TFT array substrate for a liquid crystal display device according to the prior art has the following problems.

First, when a black matrix is formed on a TFT array substrate and a thin film transistor is formed thereon, the channel layer of the thin film transistor is exposed to external light (95 in FIG. 2) to excite electrons in the semiconductor layer 99, thereby causing light leakage current. (photo induced leakage current) has a problem that occurs.

Second, since the black matrix must be additionally formed on the TFT array substrate, the number of mask processes in the TFT array process is added once, and a buffer layer must be additionally formed therebetween to insulate the black matrix and the thin film transistor from each other. .

In order to solve the above problems, a black matrix is formed on a TFT array substrate without an additional mask process, thereby simplifying the process and improving the aperture ratio, and simultaneously forming a black matrix on the thin film transistor so that the channel layer is exposed to external light. It is an object of the present invention to provide a TFT array substrate and a method of manufacturing the same, which are intended to prevent photo leakage current from being exposed.

In order to achieve the above object, the TFT array substrate of the present invention has a gate wiring and a data wiring vertically intersecting to define a unit pixel, and are formed at the intersection of the two wirings to form a gate electrode, a semiconductor layer, and a source / drain electrode. A thin film transistor, a protective film formed on the front surface including the data line and the thin film transistor, a black matrix formed on the protective film to cover the semiconductor layer of the thin film transistor, and a drain electrode of the thin film transistor on the protective film. And a pixel electrode to be contacted.

On the other hand, a method of manufacturing a TFT array substrate for achieving another object of the present invention comprises the steps of forming a gate wiring, a gate electrode and a gate pad on the substrate, forming a gate insulating film on the entire surface including the gate wiring; Forming a semiconductor layer on the gate insulating film above the gate electrode, forming a data wiring, a source / drain electrode and a data pad on the gate insulating film on which the semiconductor layer is formed, and a front surface including the data wiring Forming a passivation layer and a light shielding material on the substrate; patterning the passivation layer and the light blocking material in a batch; a contact hole exposing the drain electrode; a pad open region exposing the gate pad and the data pad; and a black matrix covering the semiconductor layer. Simultaneously forming a contact with the drain electrode on the passivation layer; Including the step of forming the pixel electrode is characterized in that formed.

As such, a black matrix is formed on the semiconductor layer to cover the channel layer from external light, thereby preventing light leakage current that may occur in the channel layer.

On the other hand, an electric field is not formed between the data line and the pixel electrode, so that the liquid crystal is not controlled in the desired direction. As a result, light leakage occurs in the region. Therefore, a shield layer is further provided to block light leakage between the data line and the pixel electrode, which may be formed on the same layer as the gate line or on the same layer as the black matrix.

Hereinafter, a TFT array substrate and a method of manufacturing the same according to an embodiment of the present invention will be described with reference to the accompanying drawings.

3 is a cross-sectional view of a TFT array substrate according to the present invention, and FIGS. 4A to 4G are process cross-sectional views of the TFT array substrate according to the present invention.

As illustrated in FIG. 3, a TFT array substrate for a liquid crystal display device according to the present invention includes a pixel region including a black matrix on a thin film transistor (TFT), a gate pad 122, and a data pad 125. It is divided into pad area | regions which are formed, respectively.

A gate wiring 112 and a data wiring 115 that vertically intersect the pixel region to define a unit pixel, and a gate electrode 112a, a gate insulating film 113, a semiconductor layer 114, A thin film transistor (TFT) in which source / drain electrodes 115a and 115b are sequentially stacked, a protective film 116 formed on the front surface including the thin film transistor, and the protective film to cover the semiconductor layer of the thin film transistor from external natural light. A black matrix 152 formed on the substrate, a pixel electrode 117 contacted to the drain electrode 115b through a contact hole 118 and formed on the entire surface of the unit pixel, and storage parallel to the gate wiring 112. The electrode 132 is formed.

In this case, the black matrix 152 is characterized in that the external light is not incident on the semiconductor layer (hereinafter, referred to as a 'channel layer') between the source electrode 115a and the drain electrode 115b. The light leakage current formed in the channel layer can be prevented by this. Since the gate electrode and the source / drain electrode of the thin film transistor are formed of a metal material and thus shield light, the entire thin film transistor may not be covered with the black matrix.

When the black matrix is limitedly formed on the thin film transistor or the semiconductor layer, the shield layer 150 is further provided to shield light leakage generated between the data line and the pixel electrode.

The shield layer may be provided on the same layer as the gate wiring or on the same layer as the black matrix, but it is more preferable to form the shield layer at the same time as the gate wiring. When the shield layer is formed simultaneously with the black matrix, the pixel layer and the data line may be shorted by the shield layer. Also, if the dielectric constant or thickness of the passivation layer is larger than that of the gate insulating layer, parasitics may occur between the shield layer and the data line. This is because the capacitance may be larger.

The pixel electrode 117 overlaps the gate insulating layer 113 and the passivation layer 116 on the storage electrode 132 to form a storage capacitor.

In addition, a gate pad 122 extending from the gate line 112 to transmit a scan signal from the outside and a data pad 125 extending from the data line 115 to a video signal are formed in the pad area. The gate pad 122 and the data pad 125 are in contact with the antioxidant layer 127 through the pad open region 119 formed by removing the gate insulating layer 113 or the protective layer 116.

Although not shown, the TFT array substrate on which the thin film transistor and the black matrix are formed as described above is opposed to the opposite substrate on which the common electrode and the color filter layer are formed, and then the liquid crystal is filled between the two substrates to complete the liquid crystal display device. .

As described above, the liquid crystal display device according to the present invention can reduce the area of the black matrix due to the bonding margin by forming the black matrix on the TFT array substrate without forming the black matrix on the counter substrate.

In order to form the TFT array substrate of the liquid crystal display device, first, as shown in FIG. 4A, copper (Cu), copper alloy (Cu Alloy), aluminum (Al) on a transparent and heat resistant TFT array substrate 111 is shown. ), Aluminum alloy (AlNd: Aluminum Neodymium), molybdenum (Mo), molybdenum alloy, chromium (Cr), chromium alloy, titanium (Ti), titanium alloys, silver (Ag), a metal selected from a silver alloy by depositing the first The gate wiring (not shown), the shield layer 150, the gate electrode 112a, and the storage electrode 132 are formed in the pixel region by patterning the photoetch process using an exposure mask, and the gate pad 122 is formed in the pad region. To form.

In this case, the shield layer 150 is formed on both edges of the data line formed in a later process to shield light leakage generated between the data line and the pixel electrode, and is formed so as not to be shorted with another pattern of the gate line layer. do.

The gate electrode and the gate pad are integrally formed with the gate wiring, and the storage electrode is formed in parallel with the gate wiring to receive the Vcom signal in the pad portion region.

4B, an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx) is deposited on the entire surface including the gate electrode 112a to form a gate insulating layer 113.

Subsequently, an amorphous silicon (a-Si: H) is deposited on the gate insulating layer 113, and then patterned by a photoetch process using a second exposure mask to form a semiconductor layer 114.

Next, copper (Cu), copper alloy (Cu Alloy), aluminum (Al), aluminum alloy (AlNd: Aluminum Neodymium), molybdenum (Mo), molybdenum alloy, chromium (Cr) on the front surface including the semiconductor layer 114 , A metal selected from chromium alloy, titanium (Ti), titanium alloy, silver (Ag), and silver alloy, and patterned by a photolithography process using a third exposure mask, thereby forming data lines 115 and source / drain electrodes in the pixel region. 115a and 115b are formed, and a data pad 125 is formed in the pad portion region.

The data line 115 vertically crosses the gate line to define a pixel region, and the source / drain electrodes 115a and 115b overlap the gate electrode 112a and the semiconductor layer 114 to form a thin film transistor. . In this case, both edges of the data line 115 overlap with edges of the shield layer 150.

For reference, forming the semiconductor layer and forming the data line, the source / drain electrode, and the data pad may be performed in the same mask process in order to reduce the number of times of mask use.

That is, after the gate insulating film is formed, amorphous silicon, a metal material, and a photoresist are deposited thereon, a diffraction exposure mask such as a slit mask or a halftone mask is covered, and the photoresist is formed in a double step. In addition, the amorphous silicon and the metal material exposed between the double-stage photoresist are collectively patterned to form a semiconductor layer, a data line, a source / drain electrode, and a data pad. Subsequently, the photoresist is etched until the low stepped photoresist is removed, and then the metal material is etched using the remaining photoresist as a mask to separate the source electrode and the drain electrode from each other, and at the same time, the channel between the source electrode and the drain electrode. Define the layer.

Subsequently, as shown in FIG. 4C, an organic insulating material such as benzocyclobutene (BCB) and an acrylic material or an inorganic insulating material such as silicon nitride or silicon oxide is deposited on the front surface including the source / drain electrodes 115a and 115b. As a result, the protective film 116 is formed, and the light blocking material 152a and the photoresist 135 are sequentially formed thereon.

The light-shielding material is at least one of a metal material, a metal oxide, and a metal nitride, but is preferably selected from a combination of these materials. Particularly, the light blocking material is selected from chromium (Cr), chromium oxide film (CrOX), and chromium nitride film (CrNx). It is preferable. Of course, you can use black resin.

Thereafter, the photoresist 135 is patterned by diffraction exposure and development using a fourth exposure mask. The fourth exposure mask uses a half-tone mask or a slit mask for diffraction exposure.

Specifically, the half-tone mask 500 positioned on the photoresist 135 has a patterned light shielding layer 502 of a metal material on the transparent substrate 501, and the light shielding layer 502 is optionally Covered by a translucent layer 503, these components divide the half-tone mask 500 into three regions: a transparent region, a translucent region, and a light shielding region.

The light transmittance is 100% in the transparent region, the light shielding region is formed with the light shielding layer 502, the light transmittance is 0%, and the translucent region is formed with the translucent layer 503, so the light transmittance is 0% or more and 100% or less. to be.

Therefore, when the photoresist 135 subjected to the diffraction exposure is developed, as shown in FIG. 4D, the photoresist 135 is divided into three regions of the fully exposed portion I, the completely non-exposed portion II, and the diffracted exposure portion III, It is completely removed only in the exposed part, formed thinner than other parts in the diffractive exposure part, and remains intact only in the completely non-exposed part.

The full exposure portion I corresponds to the transparent region of the half-tone mask 500, the full non-exposure portion II corresponds to the light shielding region, and the diffraction exposure portion III is formed at a position corresponding to the translucent region. do. In this case, the fully exposed portion is a region where a contact hole, through which a drain electrode is exposed, and a pad open region, through which a gate pad and a data pad are exposed, is formed. The completely non-exposed portion is a region where a black matrix is to be formed. The rest of the area.

Next, the light blocking material 152a, the passivation layer 116, or the gate insulating layer 113 may be selectively etched using the photoresist 135 as a mask to expose the drain electrode 115b and the gate pad ( 122 and a pad open area 119 to which the data pad 125 is exposed.

Thereafter, as shown in FIG. 4E, the photoresist 135 is ashed until the photoresist of the diffractive exposure portion is completely removed to expose the light blocking material 152a.

Subsequently, as shown in FIG. 4F, the black matrix 152 is formed by etching the light blocking material using the ashed photoresist 135 as a mask. The black matrix is formed on the thin film transistor and is formed at least on the semiconductor layer of the thin film transistor so that external light does not enter the channel layer of the semiconductor layer.

Finally, as shown in FIG. 4G, after the photoresist is stripped, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the entire surface of the substrate, and then a photo using a fifth exposure mask. Patterning is performed by an etching process to form a pixel electrode 117 contacting the drain electrode through the contact hole 118, and an anti-oxidation layer 127 contacting the gate pad and the data pad through the pad open region 119. .

The pixel electrode overlaps the storage electrode 132 to form a storage capacitor, and overlaps an edge of the shield layer 150 to shield light leakage generated between the pixel electrode and the data line. The anti-oxidation layer prevents the gate pad and the data pad exposed through the pad open region from being oxidized and improves contact characteristics with an external driving circuit.

The TFT array substrate of the BOA structure according to the present invention formed as described above is completed using a total of five exposure masks.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

In the above embodiment, the present invention has been described with reference to a twisted nematic (TN) mode TFT array substrate. The technical idea according to the invention may be applied.

The TFT array substrate of the present invention as described above and a manufacturing method thereof have the following effects.

First, when the black matrix and the thin film transistor are simultaneously formed on the TFT array substrate, the photo induced leakage current flows in the channel layer exposed to the external light by forming the black matrix on the semiconductor layer of the thin film transistor. Can be prevented.

Second, by simultaneously patterning the black matrix in the process of patterning the protective layer to form the contact hole and the pad open region, the BOA structure can be realized without additional process.

Third, since the black matrix is formed on the passivation layer on the top of the thin film transistor, it is not necessary to further form a buffer layer to insulate the black matrix and the thin film transistor, thereby reducing the process cost and simplifying the procedure.

Fourth, as the black matrix is formed on the TFT array substrate, the bonding margin can be excluded, thereby reducing the area of the black matrix. Therefore, the aperture ratio of the device can be improved.

Claims (10)

A gate wiring and a data wiring vertically intersecting to define a unit pixel; A thin film transistor formed at the intersection of the gate wiring and the data wiring and composed of a gate electrode, a semiconductor layer, and a source / drain electrode; A protective film formed on the entire surface including the data line and the thin film transistor; A black matrix formed on the passivation layer to cover the semiconductor layer of the thin film transistor; A pixel electrode contacting the drain electrode of the thin film transistor on the passivation layer; And a shield layer formed in a region between the data line and the pixel electrode. delete The method of claim 1, And the shield layer is provided on the same layer as the gate wiring. The method of claim 1, And the shield layer is provided on the same layer as the black matrix. Forming a gate wiring, a gate electrode and a gate pad on the substrate; Forming a gate insulating film on the entire surface including the gate wiring; Forming a semiconductor layer on the gate insulating film on the gate electrode; Forming a data line, a source / drain electrode, and a data pad on the gate insulating layer on which the semiconductor layer is formed; Forming a protective film and a light shielding material on the entire surface including the data line; Simultaneously patterning the passivation layer and the light blocking material to form a contact hole through which the drain electrode is exposed, a pad open region through which the gate pad and the data pad are exposed, and a black matrix covering the semiconductor layer; Forming a pixel electrode contacting the drain electrode on the passivation layer. 6. The method of claim 5, And forming a shield layer between the data line and the pixel electrode. The method of claim 6, And said shield layer is formed simultaneously with said gate wiring or said black matrix. 6. The method of claim 5, In the step of patterning the protective film and the light shielding material, a method of manufacturing a TFT array substrate, characterized in that for performing a photo-etching process using a diffraction exposure mask. 9. The method of claim 8, The patterning of the passivation layer and the light blocking material to form a contact hole, a pad open area, and a black matrix may include: Forming a double-stage photoresist on the light blocking material using the diffraction exposure mask; Selectively etching the light blocking material, the passivation layer, or the gate insulating layer using the photoresist as a mask to form a contact hole and a pad open region; Ashing the photoresist to remove the low step photoresist; Etching the light blocking material using the photoresist as a mask to form a black matrix; And removing the photoresist. 6. The method of claim 5, Forming a semiconductor layer, And forming the data wirings, the source / drain electrodes and the data pads in a same mask process.

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