KR101942982B1 - Array substrate for liquid crystal display device and method of fabricating the same - Google Patents

Abstract

The present invention provides a liquid crystal display device including gate lines extending in one direction in a display region on a substrate on which a gate pad portion and a data pad portion are defined in a display region having a plurality of pixel regions and a non-display region outside the display region, Forming a gate electrode connected to the gate wiring, forming a gate pad electrode connected to the gate wiring on the gate pad portion and a first auxiliary data pad electrode on the data pad portion; Forming a gate insulating film over the gate wiring; A first gate pad contact hole formed on the gate insulating layer in an island shape corresponding to each of the gate electrodes and simultaneously exposing the gate pad electrode to the gate insulating layer; Forming a first data pad contact hole; Forming an etch stopper at the center of the oxide semiconductor layer; A source electrode and a drain electrode which are spaced apart from each other on the upper portion of the etch stopper; a data line connected to the source electrode and intersecting the gate line to define the pixel region, 1 auxiliary gate pad electrode and a data pad electrode in contact with the first auxiliary data pad electrode; Forming an organic film over the data line on the entire surface of the display region; Forming a common electrode on the organic film having a first opening in each of the source and drain electrodes in the display region; Forming a first passivation layer over the common electrode; And forming a plate-shaped pixel electrode having a plurality of bar-shaped second openings on each of the pixel regions on the first protective layer, and a liquid crystal display device manufactured by the method And an array substrate.

Description

[0001] The present invention relates to an array substrate for a liquid crystal display device,

The present invention relates to an array substrate, and more particularly, to an array substrate for a liquid crystal display device having an oxide semiconductor layer excellent in stability of device characteristics and capable of reducing the number of mask processes, and a method of manufacturing the same.

Recently, the display field for processing and displaying a large amount of information has been rapidly developed as society has entered into a full-fledged information age. Recently, flat panel display devices having excellent performance such as thinning, light weight, and low power consumption have been developed A liquid crystal display or an organic electroluminescent device has been developed to replace a conventional cathode ray tube (CRT).

An active matrix liquid crystal display device including an array substrate including a thin film transistor Tr which is a switching element capable of controlling voltage on and off for each pixel in a liquid crystal display device has a resolution And the ability to implement video is the most attention.

In such a liquid crystal display device, an array substrate provided with a thin film transistor (Tr), which is a switching element, is essential in order to turn on / off each pixel region.

1 is a cross-sectional view of a portion of a conventional array substrate constituting a liquid crystal display device in which one pixel region is cut including a thin film transistor Tr.

As shown in the figure, in the switching region TrA in a plurality of pixel regions P in which a plurality of gate lines (not shown) and a plurality of data lines 33 are defined in the array substrate 11, gate electrodes 15 are formed.

A gate insulating layer 18 is formed on the entire surface of the gate electrode 15 and sequentially formed thereon an active layer 22 of pure amorphous silicon and an ohmic contact layer 26 of impurity amorphous silicon. (28) are formed.

A source electrode 36 and a drain electrode 38 are formed on the ohmic contact layer 26 to correspond to the gate electrode 15. At this time, the gate electrode 15, the gate insulating film 18, the semiconductor layer 28, and the source and drain electrodes 36 and 38, which are sequentially stacked in the switching region TrA, constitute the thin film transistor Tr.

A protective layer 42 is formed on the entire surface of the source and drain electrodes 36 and 38 and the exposed active layer 22 and includes a drain contact hole 45 exposing the drain electrode 38 And a pixel electrode 50 is formed on the passivation layer 42 and is independent of each pixel region P and is in contact with the drain electrode 38 through the drain contact hole 45.

At this time, a semiconductor pattern 29 having a double layer structure of a first pattern 27 and a second pattern 23 is formed under the data line 33 with the same material forming the ohmic contact layer 26 and the active layer 22 Is formed.

The active layer 22 of pure amorphous silicon is formed on the upper side of the semiconductor layer 28 of the thin film transistor Tr constituting the switching region TrA in the conventional array substrate 11 having the above- The first thickness t1 of the portion where the ohmic contact layer 26 is formed and the second thickness t2 of the exposed portion where the ohmic contact layer 26 is removed are differently formed. The difference in thickness (t1? T2) of the active layer 22 is due to the manufacturing method, and the difference in thickness (t1? T2) of the active layer 22, more precisely the source and drain And the thickness of the exposed portion between the electrodes is reduced, thereby deteriorating the characteristics of the thin film transistor Tr.

Therefore, recently, as shown in Fig. 2 (cross-sectional view for one pixel region of the array substrate provided with the thin film transistor Tr having the conventional oxide semiconductor layer), the oxide semiconductor material A thin film transistor Tr having an oxide semiconductor layer 61 of a single layer structure has been developed.

Since the oxide semiconductor layer 61 does not need to form an ohmic contact layer, the oxide semiconductor layer 61 may be formed of a material similar to that of an array substrate having a semiconductor layer made of a conventional amorphous silicon to form a spaced apart ohmic contact layer made of impurity amorphous silicon It is not necessary to be exposed to the progressive dry etching, so that deterioration of the characteristics of the thin film transistor Tr can be prevented.

On the other hand, the liquid crystal display device includes an array substrate on which a plurality of wirings, switching elements, and pixel electrodes are formed, and a color filter substrate on which color filters and common electrodes are formed. The liquid crystal molecules between the two substrates are induced That is, a vertical electric field in a direction perpendicular to the substrate.

However, there is a problem that the method of driving the liquid crystal by the vertical electric field is not excellent in the viewing angle characteristic.

In order to overcome such a problem, a transverse electric field type liquid crystal display device has been proposed. In the transverse electric field type liquid crystal display device, the pixel electrode and the common electrode are staggered on the same substrate, and a horizontal electric field in a direction parallel to the substrate is induced between the two electrodes. Therefore, the liquid crystal molecules are driven by a horizontal electric field and move in a direction parallel to the substrate, and such a lateral electric field liquid crystal display device has an improved viewing angle.

However, such a transverse electric field type liquid crystal display device has a disadvantage of low aperture ratio and low transmittance.

A fringe field switching mode LCD that drives a liquid crystal by a fringe field has been proposed in order to overcome the shortcomings of such a transverse electric field liquid crystal display device. An oxide semiconductor layer is applied to a thin film transistor provided in an array substrate for an apparatus.

However, a total of nine mask processes are being performed to fabricate an array substrate for a fringe field switching mode liquid crystal display including such an oxide semiconductor layer.

More specifically, an array substrate for a fringe field switching mode liquid crystal display including a conventional oxide semiconductor layer includes a gate forming step, an oxide semiconductor layer forming step, an esstopper forming step, a hole forming step in the gate insulating film, Forming step, an organic film forming step, a first protective layer forming step, a common electrode forming step, and a pixel electrode forming step.

Since the mask process is performed including the application of the photoresist, the exposure using the exposure mask, the development of the exposed photoresist, and the etching and the strip, a total of five unit processes are performed. The manufacturing time is prolonged, the chargeability per unit time is charged, the frequency of occurrence of defects increases, and the manufacturing cost increases.

Accordingly, in the case of a conventional array substrate for a fringe field switching mode liquid crystal display device including an oxide semiconductor layer, it is required to reduce the masking process and reduce the manufacturing cost.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide an array substrate for a fringe field switching mode liquid crystal display device having an oxide semiconductor layer capable of reducing the number of mask processes, do.

According to another aspect of the present invention, there is provided a method of fabricating an array substrate for a fringe field switching mode liquid crystal display, including: forming a display region having a plurality of pixel regions and a non- A gate electrode extending in one direction in the display region on the substrate on which the pad portion is defined; a gate electrode connected to the gate wiring in each pixel region; a gate pad electrode connected to the gate wiring in the gate pad portion; Forming a first auxiliary data pad electrode in the data pad portion; Forming a gate insulating film over the gate wiring; A first gate pad contact hole formed on the gate insulating layer in an island shape corresponding to each of the gate electrodes and simultaneously exposing the gate pad electrode to the gate insulating layer; Forming a first data pad contact hole; Forming an etch stopper at the center of the oxide semiconductor layer; A source electrode and a drain electrode which are spaced apart from each other on the upper portion of the etch stopper; a data line connected to the source electrode and intersecting the gate line to define the pixel region, 1 auxiliary gate pad electrode and a data pad electrode in contact with the first auxiliary data pad electrode; Forming an organic film over the data line on the entire surface of the display region; Forming a common electrode on the organic film having a first opening in each of the source and drain electrodes in the display region; Forming a first passivation layer over the common electrode; And forming a plate-shaped pixel electrode having a plurality of bar-shaped second openings on each of the pixel regions on the first protective layer.

The first gate pad contact hole exposes the gate pad electrode to the gate insulating layer and the oxide semiconductor layer is formed in an island shape corresponding to each gate electrode on the gate insulating layer. Forming the first data pad contact hole exposing the electrode comprises: forming a layer of an oxide semiconductor material over the entire surface of the substrate over the gate insulating layer; Forming a first photoresist pattern having a first thickness over the oxide semiconductor material layer and a second photoresist pattern having a second thickness less than the first thickness; The first gate pad contact hole and the first auxiliary data pad electrode exposing the gate pad electrode by removing the oxide semiconductor material layer and the gate insulating film below the oxide semiconductor material layer exposed between the first and second photoresist patterns, Forming the first data pad contact hole to expose the first data pad contact hole; Performing ashing to remove the second photoresist pattern having the second thickness; Forming the oxide semiconductor layer over the gate insulating film in correspondence to the gate electrode of each pixel region by removing the oxide semiconductor material layer exposed by removing the second photoresist pattern; And removing the first photoresist pattern.

A method of fabricating an array substrate for a fringe field switching mode liquid crystal display according to another embodiment of the present invention includes the steps of forming a gate pad portion and a data pad portion on a display region having a plurality of pixel regions and non- A gate electrode connected to the gate wiring, a gate pad electrode connected to the gate wiring, and a gate electrode connected to the data line, Forming a first auxiliary data pad electrode; Forming a gate insulating film over the gate wiring; Forming an oxide semiconductor layer on the gate insulating film in an island shape corresponding to each of the gate electrodes; A first gate pad contact hole for forming an etch stopper at a central portion of the oxide semiconductor layer and exposing the gate pad electrode to the gate insulating layer, a first gate pad contact hole for exposing the first auxiliary data pad electrode, ; ≪ / RTI > A source electrode and a drain electrode which are spaced apart from each other on the upper portion of the etch stopper; a data line connected to the source electrode and intersecting the gate line to define the pixel region, 1 auxiliary gate pad electrode and a data pad electrode in contact with the first auxiliary data pad electrode; Forming an organic film over the data line on the entire surface of the display region; Forming a common electrode on the organic film having a first opening in each of the source and drain electrodes in the display region; Forming a first passivation layer over the common electrode; And forming a plate-shaped pixel electrode having a plurality of second openings in a bar shape for each pixel region on the first passivation layer.

The first gate pad contact hole exposes the gate pad electrode to the gate insulating layer. The first gate pad contact hole exposes the first auxiliary data pad electrode. Forming the one data pad contact hole includes: forming an inorganic insulating layer on the entire surface of the substrate over the oxide semiconductor layer; Forming a second photoresist pattern having a first thickness above the inorganic insulating layer and a second thickness smaller than the first thickness; The first gate pad contact hole and the first auxiliary data pad electrode exposing the gate pad electrode are exposed by removing the inorganic insulating layer exposed between the first and second photoresist patterns and the gate insulating film below the inorganic insulating layer, Forming a first data pad contact hole to contact the first data pad; Performing ashing to remove the second photoresist pattern having the second thickness; Forming an etch stopper at an upper portion of the oxide semiconductor layer in each pixel region by removing the inorganic insulating layer exposed by removing the second photoresist pattern; And removing the first photoresist pattern.

A second protective layer is formed on the entire surface of the substrate over the data line before the organic film is formed.

The forming of the organic layer may include forming a hole exposing the first passivation layer corresponding to the drain electrode.

The forming of the first passivation layer may include forming a drain contact hole exposing the drain electrode by removing the second passivation layer through the hole provided in the organic layer, And forming a second gate pad contact hole and a second data pad contact hole for exposing the gate pad electrode and the data pad electrode, respectively.

The pixel electrode may be formed in contact with the drain electrode through the drain contact hole. The step of forming the pixel electrode may include the step of forming the pixel electrode through the second gate pad contact hole, 2 auxiliary gate pad electrode and a second auxiliary data pad electrode contacting the data pad electrode through the second data pad contact hole.

The plurality of bar-shaped second openings are symmetrically bent with respect to the center of each pixel region in each pixel region.

The fringe field switching mode liquid crystal display device according to an embodiment of the present invention includes a plurality of pixel regions and a non-display region outside the display region, the gate pad portion and the data pad portion being defined on the substrate, A gate and a data line formed to define the pixel region in an intersecting manner; A thin film transistor formed in each of the pixel regions and including a gate electrode, a gate insulating film, an oxide semiconductor layer, and source and drain electrodes spaced apart from the etch stopper; An organic layer formed on the entire surface of the display region above the thin film transistor; A common electrode formed on the organic layer with a first opening corresponding to each of the thin film transistors on the entire surface of the display region; and a first passivation layer formed on the entire surface of the substrate over the common electrode; A pixel electrode formed on the first passivation layer and having a plurality of second openings in a bar shape in each pixel region; A gate pad electrode connected to the gate wiring formed on the gate pad portion and the data pad portion, a first auxiliary data pad electrode in the form of an island, a first gate exposing the gate pad electrode and the first auxiliary data pad electrode, A data pad electrode in contact with the first auxiliary gate pad electrode and the first auxiliary gate pad electrode in contact with the gate pad electrode formed on the gate insulating layer; And a second gate and a data pad contact hole exposing the pad electrode and the data pad electrode, respectively.

In this case, a second passivation layer is formed on the entire surface of the substrate between the thin film transistor and the organic film, and holes for exposing the second passivation layer corresponding to the respective drain electrodes are formed in the organic film, The passivation layer and the second passivation layer are provided with a drain contact hole exposing the drain electrode through the hole, and the pixel electrode is in contact with the drain electrode through the drain contact hole.

The second passivation layer is provided with the second gate and the data pad contact hole in addition to the first passivation layer.

In addition, the plurality of bar-shaped second openings are symmetrically bent with respect to the center of each pixel region in each pixel region.

The present invention has the effect of simplifying the process by improving the productivity per unit time and further reducing the manufacturing cost by manufacturing the array substrate for the fringe field switching mode liquid crystal display device having the oxide semiconductor layer by performing the masking process for a total of eight times .

In the gate and data pad portions, a patterning process is separately performed on the gate insulating layer to form a first gate and a data pad contact hole, and a second gate and a data pad contact hole are formed for the first and second protective layers The size of the gate and data pad contact holes can be reduced, thereby contributing to realization of a narrow bezel which reduces the area of the non-display area.

In addition, the multi-domain structure is formed by symmetrically folding the data line and the bar-shaped openings in the pixel electrode with respect to the center of each pixel region, thereby reducing the color deviation according to the azimuth angle.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a conventional array substrate constituting a liquid crystal display device, in which one pixel region is cut including a thin film transistor; Fig.
2 is a cross-sectional view of one pixel region of an array substrate having a thin film transistor (Tr) having a conventional oxide semiconductor layer.
FIGS. 3A to 3K are cross-sectional views illustrating a pixel region, a gate pad portion, and a data pad portion of an array substrate for a fringe field switching mode liquid crystal display according to a first embodiment of the present invention, respectively.
4A to 4M are cross-sectional views illustrating a pixel region, a gate pad portion, and a data pad portion of an array substrate for a fringe field switching mode liquid crystal display according to a second embodiment of the present invention.

Hereinafter, preferred embodiments according to the present invention will be described with reference to the drawings.

FIGS. 3A to 3M are cross-sectional views illustrating one pixel region, a gate pad portion, and a data pad portion of an array substrate for a fringe field switching mode liquid crystal display according to a first embodiment of the present invention. Here, for convenience of description, a portion where the thin film transistor Tr as a switching element is formed in each pixel region P is defined as a switching region TrA.

3A, a transparent insulating substrate 101 is formed on a substrate made of glass or plastic, for example, a metal material such as aluminum (Al), an aluminum alloy (AlNd), copper (Cu) , Molybdenum (Mo), and molybdenum alloy (MoTi) are deposited on the entire surface to form a first metal layer (not shown).

Thereafter, the first metal layer (not shown) is exposed to a series of photoresist coating, exposure using a photomask, development of exposed photoresist, etching of the first metal layer (not shown), and strips of photoresist A plurality of gate wirings (not shown) having a single layer or a multilayer structure and extending in a first direction are formed, and at the same time, the gate wiring (not shown) is formed in the switching region TrA, And a gate electrode 105 connected to the gate electrode (not shown).

A gate pad electrode 106 connected to the gate wiring (not shown) is formed in the gate pad portion GPA as one of the characteristic structures in the first embodiment of the present invention, and the data pad portion DPA The first auxiliary data pad electrode 107 is formed in an island shape.

Thereafter, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN x) is formed on the gate wiring (not shown), the gate electrode 105, the gate pad electrode 106 and the first auxiliary data pad electrode 107. And a gate insulating layer 115 is formed on the entire surface of the substrate 101.

3B, an oxide semiconductor such as IGZO (Indium Gallium Zinc Oxide), ZTO (Zinc Tin Oxide), ZIO (Zinc Oxide), or the like is formed as an oxide semiconductor material on the gate insulating film 115. Then, Zinc Indium Oxide) is deposited or applied to form an oxide semiconductor material layer (not shown).

Thereafter, the oxide semiconductor material layer (not shown) is patterned by performing a mask process to form an island-shaped oxide semiconductor layer 120 corresponding to each switching region TrA.

Next, by depositing the oxide semiconductor layer 120 over the inorganic insulating material in the front, for example silicon oxide (SiO ₂₎ or silicon nitride (SiNx), as shown in Figure 3c to form the inorganic insulating layer 124 .

Thereafter, a photoresist is coated on the inorganic insulating layer 124 to form a first photoresist layer 190, and a light transmitting region, a blocking region, and a semi-transmitting region having a light transmission amount smaller than the transmitting region, And then exposure is performed through the exposure mask.

At this time, when the first photoresist layer 190 is of a negative type, a portion receiving a light is left at the time of development, and in a case of a positive type, a portion receiving a light is removed at the time of development.

In the drawing, for example, the first photoresist layer 190 is of a negative type. The transmissive region TA corresponds to the switching region TrA in each pixel region P and the blocking region BA corresponds to the gate pad unit GPA and the data pad unit DPA, In the other regions, the exposure mask is positioned above the first photoresist layer 190 so as to correspond to the transflective region HTA, and then exposure is performed.

At this time, diffraction exposure or halftone exposure proceeds due to the characteristics of the exposure mask having the transflective region HTA.

3D, a first photoresist pattern 191a having a first thickness corresponding to each of the switching regions TrA is formed by developing the first photoresist layer 190 having undergone the exposure, The inorganic insulating layer 124 is exposed in correspondence to the gate pad electrode 106 and the first data pad electrode 107 in the gate and data pad portions GPA and DPA, A second photoresist pattern 191b having a second thickness that is smaller than the first thickness is formed corresponding to regions other than the gate and data pad portions GPA and DPA.

Next, as shown in FIG. 3E, the inorganic insulating layer 124 exposed to the outside of the first and second photoresist patterns 191a and 191b and the gate insulating film 115 located under the inorganic insulating layer 124 are etched and removed A first gate pad contact hole 126 exposing the gate pad electrode 106 is formed in the gate pad portion GPA and the first auxiliary data pad electrode 107 is formed in the data pad portion DPA, A first data pad contact hole 127 is formed.

At this time, a first gate and data pad contact holes 126 and 127 are formed to expose the gate pad electrode 106 and the first auxiliary data pad electrode 107 in the step of patterning the inorganic insulating layer 124 Is to finally minimize the area of the gate and data pad contact holes in the gate and data pad portions (GPA, DPA).

In recent years, a narrow bezel that reduces the width of a non-display region to the maximum is a trend. In order to realize this trend, the sizes of gate and data pad contact holes in the gate and data pad portions (GPA, DPA) The gate insulating layer, the inorganic insulating layer, and the first and second passivation layers are formed together with the gate insulating layer, the inorganic insulating layer, and the second passivation layer in the same manner as in the method of manufacturing the array substrate of FIG. The etch time is prolonged due to an increase in the thickness thereof, so that the area of the gate and data pad contact holes naturally increases.

For this reason, the size of the gate and data pad contact holes is increased. To prevent this, the gate insulating film 115 is formed, and then the inorganic insulating layer 124 is directly patterned to form an etch stopper 125 The first gate and data pad contact holes 126 and 127 are formed.

Then, as shown in FIG. 3F, ashing is performed to remove the second photoresist pattern 191b having the second thickness, thereby exposing the inorganic insulating layer 124. Next, as shown in FIG.

Next, as shown in FIG. 3G, the second photoresist pattern 191b is removed, and the newly exposed inorganic insulating layer 124 is etched and removed to expose the gate insulating film 115. Next, as shown in FIG.

At this time, since the first photoresist pattern 191a remains in the switching region TrA, the inorganic insulating layer 124 remaining unetched by the first photoresist pattern 191a has an island shape, And an etch stopper 125 is formed on each oxide semiconductor layer 120. In this case, each of the oxide semiconductor layers 120 is exposed by the etch stopper 125 so that the upper surfaces of both ends thereof are exposed.

Next, as shown in FIG. 3H, the first photoresist pattern 191a remaining on the etch stopper 125 is removed by exposing a strip, thereby exposing the etch stopper 125.

Thereafter, a low resistance metal material such as aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo), molybdenum alloy (MoTi) The above material is deposited on the entire surface of the substrate 101 to form a second metal layer (not shown) having a single layer or a double layer structure.

Thereafter, the second metal layer (not shown) is patterned by a mask process to form a data line 135 crossing the gate line (not shown) on the gate insulating layer 115 and defining the pixel region P, And a source electrode 133 and a drain electrode 136 which are spaced apart from each other on the etch stopper 125 and are in contact with the upper surface of the end of the oxide semiconductor layer 120 are formed in the switching region TrA, do.

At the same time, in the gate pad portion GPA, a first assist gate pad electrode 131 is formed to contact the gate pad electrode 106 through the first gate pad contact hole 126, A data pad electrode 132 connected to the data line (not shown) and contacting the first auxiliary data pad electrode 107 through the first data pad contact hole 127 is formed in the first data pad electrode DPA .

The first auxiliary gate pad electrode 131 is formed on the gate pad portion GPA in the process of forming the first and second protective layers 140 and 160 in FIG. The first gate pad contact hole 126 is further exposed to an etchant or a reactive gas so that the area of the first gate pad contact hole 126 is not expanded.

Since the first gate pad electrode 131 and the data pad electrode 132 are provided in the gate pad unit GPA and the data pad unit DPA in the present state, Since the gate insulating layer 115 is covered with the first assist gate pad electrode 131 and the data pad electrode 132 even when the layer (140,160 in FIG. 3L) is patterned, exposure to the etchant or reactive gas The first gate and data pad contact holes 126 and 127 are not enlarged in size.

 The source electrode 133 is connected to the data line (not shown), and the gate electrode 105, the gate insulating layer 115 and the oxide semiconductor layer 120 And the source electrode 133 and the drain electrode 136 which are spaced apart from the etch stopper 125 constitute a thin film transistor Tr which is a switching element.

3I, an inorganic insulating material (not shown) is formed on the data line (not shown), the source electrode 133 and the drain electrode 136, the first assist gate pad electrode 131 and the data pad electrode 132, A first passivation layer 140 is formed on the entire surface of the substrate 101 by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiNx), for example.

The first passivation layer 140 is formed by directly contacting the organic layer 144 (see FIG. 3J) where the oxide semiconductor layer 120 exposed between the source electrode 133 and the drain electrode 136 is formed later May be omitted in order to prevent degradation of the characteristics of the thin film transistor Tr due to channel contamination.

Next, as shown in FIG. 3J, an organic insulating material having a low dielectric constant property and a photosensitive property, for example, photo acryl is formed on the entire surface of the substrate 101 on the first passivation layer 140 The gate and data pad portions GPA and DPA formed with the gate and data pad electrodes 106 and 132 are removed and the organic film 144 is formed only in the display region.

At this time, the organic layer is patterned to form a hole hl for exposing the first passivation layer 140 in a part of the drain electrode 136 in the switching region TrA in each pixel region P Feature.

Next, as shown in FIG. 3K, a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) is deposited on the entire surface of the substrate 101, A transparent conductive material layer (not shown) is formed, and a mask process is performed to form a common electrode 150 having a state connected to the display region.

At this time, the common electrode 150 is formed corresponding to the switching region TrA in each pixel region P, thereby forming the first opening op1. The provision of the first opening op1 corresponding to the common electrode 150 is advantageous in that the parasitic capacitance is increased by overlapping the common electrode 150 and the gate electrode 105, the source electrode 133 and the drain electrode 136 To prevent a short circuit with the pixel electrode (170 in FIG. 3M) formed in contact with the drain electrode 136 in a later process (see FIG. 3C) .

Next, as shown in FIG. 31, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiO ₂ ) is formed on the common electrode 150 having the first opening op 1 corresponding to the switching region TrA The second protective layer 160 is formed on the entire surface of the substrate 101 by depositing SiNx.

The first passivation layer 140 exposed through the holes provided in the organic layer 144 corresponding to the second passivation layer 160 and the respective switching regions TrA is then subjected to a mask process, And the second passivation layer 160 and the first passivation layer 140 are formed in the gate and data pad portions GPA and DPA at the same time as the drain contact hole 163 exposing the drain electrode 136. [ A second gate pad contact hole 164 and a second data pad contact hole 165 are formed to expose the first and second gate pad electrodes 131 and 132, respectively.

Although the first and second passivation layers 140 and 160 are patterned together, the second gate and data pad contact holes 164 and 165 may be formed by patterning the inorganic insulating layer 124 and the gate insulating layer 115, The size of the gate insulating film 115 is significantly reduced compared with the conventional case where the gate insulating film 115 is patterned together.

Next, as shown in FIG. 3M, a transparent conductive material, for example, indium-tin oxide (ITO) is deposited on the second passivation layer 160 having the drain contact hole 163 and the second gate and data pad contact holes 164 and 165, A second transparent conductive material layer (not shown) is formed by depositing tin-oxide (ITO) or indium-zinc-oxide (IZO) on the entire surface of the substrate 101, The pixel electrode 170 is separated from the drain electrode 136 by the drain contact hole 163 and is in contact with the drain electrode 136.

The pixel electrode 170 having the plate shape formed in each pixel region P is provided with a plurality of second openings op2 having a bar shape in each pixel region P to be.

At the same time, in the gate pad portion GPA, a second assist gate pad electrode 172 is formed to contact the first assist gate pad electrode 131 through the second gate pad contact hole 164, The second auxiliary data pad electrode 174 which contacts the data pad electrode 132 through the second data pad contact hole 165 is formed in the pad portion DPA according to the first embodiment of the present invention, The fringe field switching mode liquid crystal display array substrate 101 is completed.

At this time, the plurality of second openings op2 provided in each pixel region P form a rectilinear bar in each pixel region P or a central portion of each pixel region P The bar can be formed symmetrically with respect to the reference.

When a plurality of second openings op2 are formed in a bar shape in each pixel region P, a data line (not shown) is also formed by being bent with respect to the central portion of each pixel region P The array substrate 101 having such a configuration has a dual domain in each pixel region P, so that it has an effect of suppressing a color deviation generated when a user views the display region at a specific azimuth angle.

Hereinafter, a method of fabricating an array substrate for a fringe field switching mode liquid crystal display according to a second embodiment of the present invention will be described. At this time, in the case of the second embodiment of the present invention, since most processes are the same as those of the first embodiment described above, the processes having differentiation will be mainly described.

4A to 4H are cross-sectional views illustrating a method of manufacturing a pixel region P, a gate pad portion GPA, and a data pad portion DPA of an array substrate for a fringe field switching mode liquid crystal display according to a second embodiment of the present invention. Fig. For convenience of description, a portion where the thin film transistor Tr is formed as a switching element in each pixel region P is defined as a switching region TrA, and the same constituent elements as those of the first embodiment are denoted by the same reference numerals Respectively.

4A, a metal material such as aluminum (Al), an aluminum alloy (AlNd), copper (Cu), or the like is coated on a transparent insulating substrate 101, , A copper alloy, molybdenum (Mo), and molybdenum alloy (MoTi) is deposited on the entire surface to form a first metal layer (not shown).

Thereafter, the first metal layer (not shown) is exposed to a series of photoresist coating, exposure using a photomask, development of exposed photoresist, etching of the first metal layer (not shown), and strips of photoresist A plurality of gate wirings (not shown) having a single layer or a multilayer structure and extending in a first direction are formed, and at the same time, the gate wiring (not shown) is formed in the switching region TrA, And a gate electrode 105 connected to the gate electrode (not shown).

A gate pad electrode 106 connected to the gate wiring (not shown) is formed in the gate pad portion GPA as one of the characteristic structures in the first embodiment of the present invention, and the data pad portion DPA The first auxiliary data pad electrode 107 is formed in an island shape.

Thereafter, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN x) is formed on the gate wiring (not shown), the gate electrode 105, the gate pad electrode 106 and the first auxiliary data pad electrode 107. And a gate insulating layer 115 is formed on the entire surface of the substrate 101.

Next, as shown in FIG. 4B, an oxide semiconductor material such as IGZO (Indium Gallium Zinc Oxide), ZTO (Zinc Tin Oxide), ZIO (ZIO) Zinc Indium Oxide) is deposited or applied to form an oxide semiconductor material layer 119.

Next, as shown in FIG. 4C, a photoresist is coated on the oxide semiconductor material layer 119 to form a first photoresist layer 190, and a light transmission area TA and a blocking area BA and the transflective region HTA in which the light transmission amount is smaller than the transmissive area TA is placed and exposure is performed through the exposure mask 195. [

At this time, in the drawing, for example, the first photoresist layer 190 is a negative type.

The transmissive region TA corresponds to the switching region TrA in each pixel region P and the blocking region BA corresponds to the gate pad unit GPA and the data pad unit DPA, In the other regions, the exposure mask 195 is positioned above the first photoresist layer 190 so as to correspond to the transflective region HTA, and exposure is then performed. At this time, diffraction exposure or halftone exposure progresses due to the characteristics of the exposure mask 195 having the transflective region HTA.

Next, as shown in FIG. 4D, when the first photoresist layer 190 having undergone the exposure is developed, a first photoresist pattern 191a having a first thickness corresponding to each of the switching regions TrA, The oxide semiconductor material layer 119 is exposed in correspondence to the gate pad electrode 106 and the first auxiliary data pad electrode 107 in the gate and data pad portions GPA and DPA, A second photoresist pattern 191b having a second thickness thinner than the first thickness is formed corresponding to the switching region TrA and regions other than the gate and data pad portions GPA and DPA.

Next, as shown in FIG. 4F, the oxide semiconductor material layer 119 exposed to the outside of the first and second photoresist patterns 191a and 191b and the gate insulating film 115 located under the oxide semiconductor material layer 119 are etched A first gate pad contact hole 126 for exposing the gate pad electrode 106 to the gate pad portion GPA is formed and the first auxiliary data pad electrode 107 is formed in the data pad portion DPA, The first data pad contact hole 127 exposing the first data pad contact hole 127 is formed.

The first gate and data pad contact holes 126 and 127 exposing the gate pad electrode 106 and the first auxiliary data pad electrode 107 in the step of patterning the oxide semiconductor material layer 119, Is to minimize the width (or area) of the gate and data pad contact holes.

Then, as shown in FIG. 4F, ashing is performed to expose the oxide semiconductor material layer 119 by removing the second photoresist pattern 191b having the second thickness. The first photoresist pattern 191a is also reduced in thickness by the ashing but still remains on the oxide semiconductor material layer 119. [

Next, as shown in FIG. 4G, the second photoresist pattern 191b is removed to expose the gate insulating layer 115 by etching and removing the newly exposed oxide semiconductor material layer 119 (FIG. 4F) .

At this time, in the switching region TrA, since the first photoresist pattern 191a remains on the oxide semiconductor layer 120, the oxide semiconductor material 120 remains unetched by the first photoresist pattern 191a, The layer (119 in FIG. 4F) has an island shape and corresponds to the gate electrode 105 to form the oxide semiconductor layer 120.

Next, as shown in FIG. 4H, a strip is removed to expose the oxide semiconductor layer 120 by removing the first photoresist pattern 191a.

An inorganic insulating layer (not shown) is formed on the entire surface of the substrate 101 by depositing an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN x) on the entire surface of the oxide semiconductor layer 120 , And the etching stopper 125 is formed corresponding to the central portion of the upper portion of the oxide semiconductor layer 120 provided in each switching region TrA by patterning the masking process.

At this time, the upper surface of the oxide semiconductor layer 120 is exposed by the etch stopper 125.

The subsequent steps of forming the etch stopper 125 are the same as the manufacturing method of the array substrate 101 for a fringe field switching mode liquid crystal display according to the first embodiment described with reference to Figs. 3H to 3M The description thereof will be omitted.

The array substrate 101 for the fringe field switching mode liquid crystal display according to the first and second embodiments of the present invention is formed by performing a total of eight mask processes, There is an effect of reducing the number of the masking processes and improving the productivity per unit time and reducing the manufacturing cost.

In the gate and data pad portions GPA and DPA, a patterning process is separately performed on the gate insulating film 115 to form the first gate and data pad contact holes 126 and 127, and the first and second protection The gate and data pad contact holes 126, 164, 127, and 165 are finally reduced in size by forming second gate and data pad contact holes 164 and 165 for the layers 140 and 160 So that it has an effect of contributing to the implementation of narrow bezel which reduces the area of the non-display area.

101: (array) substrate 105: gate electrode
106: gate pad electrode 107: first auxiliary data pad electrode
115: gate insulating film 120: oxide semiconductor layer
125: etch stopper 131: first auxiliary gate electrode
132: Data pad electrode 133: Source electrode
136: drain electrode 140: first protective layer
144: organic film 150: common electrode
160: second protection layer 163: drain contact hole
164: second gate pad contact hole 165: second data pad contact hole
170: pixel electrode 172: second auxiliary gate pad electrode
174: Second auxiliary data pad electrode DPA: Data pad part
GPA: gate pad portion op1: first opening
op2: second aperture P: pixel area
Tr: thin film transistor TrA: switching region

Claims (13)

A gate wiring extending in one direction in the display region on the substrate on which the gate pad portion and the data pad portion are defined in the display region having a plurality of pixel regions and the non-display region outside the display region; Forming a gate electrode, a gate pad electrode connected to the gate wiring on the gate pad portion, and a first auxiliary data pad electrode on the data pad portion;
Forming a gate insulating film over the gate wiring;
A first gate pad contact hole formed on the gate insulating layer in an island shape corresponding to each of the gate electrodes and simultaneously exposing the gate pad electrode to the gate insulating layer; Forming a first data pad contact hole;
Forming an etch stopper at the center of the oxide semiconductor layer;
A source electrode and a drain electrode which are spaced apart from each other on the upper portion of the etch stopper; a data line connected to the source electrode and intersecting the gate line to define the pixel region, 1 auxiliary gate pad electrode and a data pad electrode in contact with the first auxiliary data pad electrode;
Forming an organic film over the data line on the entire surface of the display region;
Forming a common electrode on the organic film having a first opening in each of the source and drain electrodes in the display region;
Forming a first passivation layer over the common electrode;
Forming a plate-shaped pixel electrode having a plurality of bar-shaped second openings on each of the pixel regions on the first protective layer,
And a plurality of pixel electrodes formed on the substrate.
The method according to claim 1,
The first gate pad contact hole forming the oxide semiconductor layer in an island shape corresponding to each gate electrode on the gate insulating film and exposing the gate pad electrode to the gate insulating film, The step of forming the first data pad contact hole to expose comprises:
Forming an oxide semiconductor material layer on the entire surface of the substrate over the gate insulating film;
Forming a first photoresist pattern having a first thickness over the oxide semiconductor material layer and a second photoresist pattern having a second thickness less than the first thickness;
The first gate pad contact hole and the first auxiliary data pad electrode exposing the gate pad electrode by removing the oxide semiconductor material layer and the gate insulating film below the oxide semiconductor material layer exposed between the first and second photoresist patterns, Forming the first data pad contact hole to expose the first data pad contact hole;
Performing ashing to remove the second photoresist pattern having the second thickness;
Forming the oxide semiconductor layer over the gate insulating film in correspondence to the gate electrode of each pixel region by removing the oxide semiconductor material layer exposed by removing the second photoresist pattern;
Removing the first photoresist pattern
And a plurality of pixel electrodes formed on the substrate.
A gate wiring extending in one direction in the display region on the substrate on which the gate pad portion and the data pad portion are defined in the display region having a plurality of pixel regions and the non-display region outside the display region; Forming a gate electrode, a gate pad electrode connected to the gate wiring on the gate pad portion, and a first auxiliary data pad electrode on the data pad portion;
Forming a gate insulating film over the gate wiring;
Forming an oxide semiconductor layer on the gate insulating film in an island shape corresponding to each of the gate electrodes;
A first gate pad contact hole for forming an etch stopper at a central portion of the oxide semiconductor layer and exposing the gate pad electrode to the gate insulating layer, a first gate pad contact hole for exposing the first auxiliary data pad electrode, ; ≪ / RTI >
A source electrode and a drain electrode which are spaced apart from each other on the upper portion of the etch stopper; a data line connected to the source electrode and intersecting the gate line to define the pixel region, 1 auxiliary gate pad electrode and a data pad electrode in contact with the first auxiliary data pad electrode;
Forming an organic film over the data line on the entire surface of the display region;
Forming a common electrode on the organic film having a first opening in each of the source and drain electrodes in the display region;
Forming a first passivation layer over the common electrode;
Forming a plate-shaped pixel electrode having a plurality of bar-shaped second openings on the first protective layer,
And a plurality of pixel electrodes formed on the substrate.
The method of claim 3,
The first gate pad contact hole for exposing the gate pad electrode to the gate insulating film and the first gate pad contact hole for exposing the first auxiliary data pad electrode; Forming a pad contact hole,
Forming an inorganic insulating layer on the entire surface of the substrate over the oxide semiconductor layer;
Forming a second photoresist pattern having a first thickness above the inorganic insulating layer and a second thickness smaller than the first thickness;
The first gate pad contact hole and the first auxiliary data pad electrode exposing the gate pad electrode are exposed by removing the inorganic insulating layer exposed between the first and second photoresist patterns and the gate insulating film below the inorganic insulating layer, Forming a first data pad contact hole to contact the first data pad;
Performing ashing to remove the second photoresist pattern having the second thickness;
Forming an etch stopper at an upper portion of the oxide semiconductor layer in each pixel region by removing the inorganic insulating layer exposed by removing the second photoresist pattern;
Removing the first photoresist pattern
And a plurality of pixel electrodes formed on the substrate.
The method according to claim 1 or 3,
Wherein a second protective layer is formed on the entire surface of the substrate over the data line before forming the organic film.
6. The method of claim 5,
Wherein the forming of the organic layer includes forming a hole exposing the first passivation layer corresponding to the drain electrode.
The method according to claim 6,
Wherein forming the first passivation layer comprises:
A drain contact hole exposing the drain electrode by removing the second passivation layer through the hole provided in the organic film, and forming a drain contact hole exposing the first auxiliary gate pad electrode and the data pad electrode, And forming a second gate pad contact hole and a second data pad contact hole.
8. The method of claim 7,
The pixel electrode is formed to be in contact with the drain electrode through the drain contact hole,
Wherein forming the pixel electrode includes:
A second auxiliary gate pad electrode contacting the first auxiliary gate pad electrode through the second gate pad contact hole and a second auxiliary data pad electrode contacting the data pad electrode through the second data pad contact hole, Wherein the step of forming the array substrate comprises the steps of:
The method according to claim 1 or 3,
Wherein the plurality of bar-shaped second openings are symmetrically bent with respect to a central portion of each of the pixel regions within each pixel region.
A gate and a data line formed on the substrate defined by the gate pad portion and the data pad portion and defining the pixel region so as to intersect with each other via a gate insulating film in a display region having a plurality of pixel regions and a non-display region outside the display region;
A thin film transistor formed in each of the pixel regions and including a gate electrode, a gate insulating film, an oxide semiconductor layer, and source and drain electrodes spaced apart from the etch stopper;
An organic layer formed on the entire surface of the display region above the thin film transistor;
A common electrode formed on the organic layer and having a first opening corresponding to each of the thin film transistors on the entire surface of the display region;
A first protective layer formed on the entire surface of the substrate over the common electrode;
A pixel electrode formed on the first passivation layer and having a plurality of second openings in a bar shape in each pixel region;
A gate pad electrode connected to the gate wiring formed on the gate pad portion and the data pad portion, a first auxiliary data pad electrode in the form of an island, a first gate exposing the gate pad electrode and the first auxiliary data pad electrode, A data pad electrode in contact with the first auxiliary gate pad electrode and the first auxiliary gate pad electrode in contact with the gate pad electrode formed on the gate insulating layer; And a second gate and a data pad contact hole exposing the pad electrode and the data pad electrode, respectively,
And a plurality of pixel electrodes.
11. The method of claim 10,
A second passivation layer is formed on the entire surface of the substrate between the thin film transistor and the organic film,
Wherein the organic layer includes a hole for exposing the second passivation layer corresponding to each drain electrode,
And a drain contact hole exposing the drain electrode through the hole is formed in the first passivation layer and the second passivation layer,
And the pixel electrode is in contact with the drain electrode through the drain contact hole.
12. The method of claim 11,
And the second protective layer is provided with the second gate and the data pad contact hole in addition to the first protective layer.
12. The method of claim 11,
Wherein the plurality of bar-shaped second openings are symmetrically bent with respect to a central portion of each of the pixel regions within each pixel region.

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