KR101777628B1 - Array substrate and method of fabricating the same - Google Patents

Abstract

The present invention relates to an array substrate and a method of manufacturing the same, and more particularly, to an array substrate including a thin film transistor having an oxide semiconductor layer which originally suppresses the surface damage of the semiconductor layer by dry etching progress, And a method for producing the same.
The present invention has the effect of simplifying the manufacturing process and reducing the manufacturing cost by reducing the number of mask processes by completing the thin film transistor by the mask process four times in total including the oxide semiconductor layer and the etch stopper on the oxide semiconductor layer.
Further, since the oxide semiconductor layer is not exposed to the dry etching and the etching solution of the metal material, the surface damage does not occur and the characteristics of the thin film transistor are prevented from deteriorating.

Description

[0001] The present invention relates to an array substrate and a manufacturing method thereof,

The present invention relates to an array substrate, and more particularly, to an array substrate including a thin film transistor having an oxide semiconductor layer which suppresses the surface damage of a semiconductor layer from occurring by dry etching progress and which is excellent in device characteristic stability, and a manufacturing method thereof will be.

Recently, the display field for processing and displaying a large amount of information has been rapidly developed as society has entered into a full-fledged information age. Recently, flat panel display devices having excellent performance such as thinning, light weight, and low power consumption have been developed A liquid crystal display or an organic electroluminescent device has been developed to replace a conventional cathode ray tube (CRT).

Among liquid crystal display devices, an active matrix liquid crystal display device including an array substrate having a thin film transistor, which is a switching device capable of controlling voltage on and off for each pixel, The ability is excellent and is getting the most attention.

In addition, since the organic electroluminescent device has a high luminance and a low operating voltage characteristic and is a self-luminous type that emits light by itself, it has a large contrast ratio, can realize an ultra-thin display, has a response time of several microseconds Mu s), has no limitation of viewing angles, is stable at low temperatures, and is driven at a low voltage of 5 to 15 V DC, making it easy to manufacture and design a driving circuit, and has recently attracted attention as a flat panel display device.

In this liquid crystal display device and the organic electroluminescent device, an array substrate including a thin film transistor, which is a switching element, is constituted in order to commonly turn on / off each pixel region.

1 is a cross-sectional view of a portion of a conventional array substrate constituting a liquid crystal display device in which one pixel region is cut including a thin film transistor.

As shown in the figure, in the switching region TrA in a plurality of pixel regions P in which a plurality of gate lines (not shown) and a plurality of data lines 33 are defined in the array substrate 11, gate electrodes 15 are formed. A gate insulating layer 18 is formed on the entire surface of the gate electrode 15 and sequentially formed thereon an active layer 22 of pure amorphous silicon and an ohmic contact layer 26 of impurity amorphous silicon. (28) are formed. A source electrode 36 and a drain electrode 38 are formed on the ohmic contact layer 26 to correspond to the gate electrode 15. The gate electrode 15, the gate insulating film 18, the semiconductor layer 28, and the source and drain electrodes 36 and 38, which are sequentially stacked in the switching region TrA, constitute a thin film transistor Tr.

A protective layer 42 is formed on the entire surface of the source and drain electrodes 36 and 38 and the exposed active layer 22 and includes a drain contact hole 45 exposing the drain electrode 38 And a pixel electrode 50 is formed on the passivation layer 42 and is independent of each pixel region P and is in contact with the drain electrode 38 through the drain contact hole 45. At this time, a semiconductor pattern 29 having a double layer structure of a first pattern 27 and a second pattern 23 is formed under the data line 33 with the same material forming the ohmic contact layer 26 and the active layer 22 Is formed.

The active layer 22 of pure amorphous silicon is formed on the upper side of the semiconductor layer 28 of the thin film transistor Tr constituting the switching region TrA in the conventional array substrate 11 having the above- The first thickness t1 of the portion where the ohmic contact layer 26 is formed and the second thickness t2 of the exposed portion where the ohmic contact layer 26 is removed are differently formed. The difference in thickness (t1? T2) of the active layer 22 is due to the manufacturing method, and the difference in thickness (t1? T2) of the active layer 22, more precisely the source and drain And the thickness of the exposed portion between the electrodes is reduced, thereby deteriorating the characteristics of the thin film transistor Tr.

Therefore, in recent years, a thin film transistor having a semiconductor layer of a single layer structure using an oxide semiconductor material without requiring an ohmic contact layer has been developed. Since the oxide semiconductor layer does not need to form the ohmic contact layer, the oxide semiconductor layer is not exposed to the dry etching, so that deterioration of the characteristics of the thin film transistor can be prevented.

However, since the oxide semiconductor layer may affect not only the dry etching but also the characteristics of the thin film transistor even when exposed to the etching solution of the metal material, an etch stopper made of an inorganic insulating material is formed on the center portion of the oxide semiconductor layer.

A total of five or more mask processes have been carried out in the fabrication of the array substrate including the oxide semiconductor layer and the thin film transistor having the etch stopper on the oxide semiconductor layer.

A method of manufacturing an array substrate including a conventional thin film transistor having an oxide semiconductor layer and an etch stopper will be described.

FIGS. 2A to 2F are cross-sectional views illustrating steps of manufacturing a portion of one pixel region of an array substrate including a conventional thin film transistor having an oxide semiconductor layer and an etch stopper.

First, as shown in FIG. 2A, a first metal material is deposited on a substrate 51, and a mask process is performed and patterned to form a gate electrode 55 and a gate wiring (not shown).

2B, a gate insulating film 58 is formed on the gate electrode 55 and the gate wiring (not shown), and the oxide semiconductor material is deposited on the gate insulating film 58 over the entire surface And the oxide semiconductor layer 61 is formed corresponding to the gate electrode by patterning the mask layer through a mask process.

Next, as shown in FIG. 2C, an inorganic insulating material is deposited on the oxide semiconductor layer 61, and the mask process is performed to pattern the oxide semiconductor layer 61, thereby forming an etch stopper 64 (corresponding to the center portion of the oxide semiconductor layer 61) ).

Next, as shown in FIG. 2D, a second metal material is deposited on the entire surface of the etch stopper 64 and is patterned by a mask process to form a data line 67 crossing the gate line (not shown) And source and drain electrodes 70 and 73 spaced apart from each other are formed on the etch stopper 64.

2E, a protective layer 76 is formed on the entire surface of the source and drain electrodes 70 and 73 and is patterned by a mask process to expose the drain electrode 73, Thereby forming a hole 77.

Next, as shown in FIG. 2F, a transparent conductive material is deposited on the entire surface of the passivation layer 76 and is patterned by a mask process to contact the drain electrode 73 through the drain contact hole 77 And the pixel electrodes 79 are formed to complete the array substrate 51.

In this case, it can be seen that a total of six mask processes are in progress. Since the mask process is performed including the application of the photoresist, the exposure using the exposure mask, the development of the exposed photoresist, and the etching and the strip, a total of five unit processes are performed. The manufacturing time is prolonged, the chargeability per unit time is charged, the frequency of occurrence of defects increases, and the manufacturing cost increases.

Therefore, in the case of an array substrate having a conventional oxide semiconductor layer and an etch stopper, it is required to reduce the manufacturing cost by reducing the mask process.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a fabrication method capable of manufacturing an array substrate through an oxide semiconductor layer and an etch stopper on the oxide semiconductor layer and performing a mask process four times in total.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a gate wiring on a substrate in which a pixel region and a switching region are defined in the pixel region; forming a gate electrode corresponding to the switching region; Forming an oxide semiconductor layer and an inorganic insulating pattern on the gate insulating film in correspondence to the gate electrode and removing the rim of the inorganic insulating pattern, Forming a transparent conductive material layer on the etch stopper; forming a metal layer on the transparent conductive material layer; patterning the metal layer and the transparent conductive material layer to form a gate electrode on the gate insulating layer A data wiring of a bilayer structure is formed, and at the same time, Layer structure of source and drain electrodes spaced apart from each other on the stopper and in contact with both side edges of the oxide semiconductor layer and a pixel pattern of a bilayer structure of the metal layer and the transparent conductive material layer extending from the drain electrode, Forming a protective layer on the data line, the source electrode, the drain electrode and the pixel pattern; and removing the protective layer and the metal layer in a region other than the switching region of the pixel region, And forming a pixel electrode made of a transparent conductive film.

The step of forming the gate wiring and the gate electrode may include forming a gate pad electrode connected to an end of the gate wiring, the step of forming the data wiring is connected to the data wiring end, And forming the auxiliary gate pad electrode having a double layer structure in contact with the gate pad electrode, wherein the forming of the pixel electrode comprises: forming the auxiliary gate pad electrode and the data pad electrode So as to form a single layer of only the transparent conductive material layer.

The step of forming the oxide semiconductor layer and the etch stopper may include the steps of forming an oxide semiconductor material layer and an inorganic insulating layer on the gate insulating film and forming an oxide semiconductor layer and an inorganic insulating layer on the inorganic insulating layer, Forming a first photoresist pattern on the gate pad electrode, exposing the inorganic insulating layer in correspondence with the gate pad electrode, and forming a second thickness smaller than the first thickness corresponding to a region other than the region where the gate electrode and the gate pad electrode are formed Forming a second photoresist pattern on the first photoresist pattern by removing the inorganic insulating layer, the oxide semiconductor material layer, and the gate insulating layer exposed to the outside of the first and second photoresist patterns, Forming a gate pad contact hole; and performing a first ashing to form a gate pad contact hole Exposing the inorganic insulating layer by removing the photoresist pattern, removing the inorganic insulating layer and the oxide semiconductor material layer exposed to the outside of the first photoresist pattern to expose the gate insulating film, Forming an oxide semiconductor layer and the inorganic insulating pattern on the first photoresist layer; and performing a second ashing process to reduce the thickness and the width of the first photoresist pattern, Removing the rim of the inorganic insulating pattern exposed outside the first photoresist pattern having a reduced width to form the etch stopper and simultaneously exposing both side edges of the oxide semiconductor layer; , And removing the first photoresist pattern having a reduced width .

The primary ashing has an anisotropic property, and the secondary ashing may have an isotropic property.

The oxide semiconductor material layer may be made of a-IGZO (amorphous-Indium Gallium Zinc Oxide) or ZTO (Zinc Tin Oxide), and the inorganic insulating layer may be made of silicon oxide (SiO 2) The inorganic insulating layer may be simultaneously etched by BOE (Buffered Oxide Etchant).

The rim of the inorganic insulating pattern can be removed by dry etching.

In addition, the pixel electrode may be formed so as to overlap the front gate wiring, so that the front gate wiring, the pixel electrode, and the gate insulating film overlap each other to form a storage capacitor.

According to another aspect of the present invention, there is provided a semiconductor device comprising a gate wiring, a gate electrode connected to the gate wiring, a gate insulating film over the gate wiring and the gate electrode, an oxide semiconductor layer disposed over the gate insulating film, A data line having a double layer structure of a lower layer of a transparent conductive material and an upper layer of a metal material on the gate insulating layer, the data line extending from the etch stopper, Source and drain electrodes each having a two-layer structure of a lower layer of a transparent conductive material and an upper layer of a metal material in contact with both side ends of the oxide semiconductor layer, pixel electrodes extending from the lower layer of the drain electrode on the gate insulating film, Drain electrode and the data line And a protective layer disposed on the upper layer and spaced apart from an upper surface of the lower layer so as to correspond to an upper layer and an upper layer of the metal material of the drain electrode to expose the pixel electrode, The front-end gate line, the pixel electrode, and the gate insulating layer provide an array substrate constituting a storage capacitor.

The array substrate includes a gate pad electrode formed to be connected to an end of the gate line, a data pad electrode connected to an end of the data line and having a single layer structure of a transparent conductive material on the gate insulating layer, And a gate auxiliary pad electrode formed in contact with the gate pad electrode over the gate insulating layer and having a single layer structure of a transparent conductive material.

Also, the oxide semiconductor layer may be made of a-IGZO (amorphous-Indium Gallium Zinc Oxide) or ZTO (Zinc Tin Oxide), and the protective layer may be made of silicon oxide (SiO 2).

According to the method of manufacturing an array substrate according to the present invention, the oxide semiconductor layer and the etch stopper are formed on the oxide semiconductor layer and the etching stopper is completed by a total of four mask processes, thereby reducing the number of mask processes and simplifying the manufacturing process and reducing manufacturing costs.

Also, since the oxide semiconductor layer is not exposed to the dry etching and the etchant of the metal material, the oxide semiconductor layer is not damaged, thereby preventing the characteristics of the thin film transistor from being deteriorated.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a conventional array substrate constituting a liquid crystal display device, in which one pixel region is cut including a thin film transistor; Fig.
FIGS. 2A to 2F are cross-sectional views illustrating steps of manufacturing a portion of one pixel region of an array substrate including a conventional thin film transistor having an oxide semiconductor layer and an etch stopper.
FIGS. 3A to 3I illustrate one pixel region including an oxide semiconductor layer and an etch stopper of an array substrate according to an embodiment of the present invention, a portion where a data line is formed, a gate and a data pad portion (GPA, DPA Sectional view of the manufacturing steps of the manufacturing process.

Hereinafter, preferred embodiments according to the present invention will be described with reference to the drawings.

FIGS. 3A to 3I illustrate one pixel region including a thin film transistor of an array substrate including an oxide semiconductor layer and an etch stopper according to an embodiment of the present invention, a portion DLA where a data line is formed, a gate and a data pad portion GPA, DPA). Here, for convenience of description, a portion where a thin film transistor connected to the gate and data lines in each pixel region P is to be formed is defined as a switching region TrA.

3A, a first metal material such as copper (Cu), a copper alloy (AlNd), aluminum (Al), or the like is coated on a substrate 101 made of a transparent insulating substrate 101, Al) and an aluminum alloy (AlNd) to form a first metal layer (not shown) having a single layer or a bilayer structure.

Thereafter, the first metal layer (not shown) is patterned by performing a mask process including a series of unit processes such as coating of photoresist, exposure using an exposure mask, development of exposed photoresist, and etching, A gate electrode 108 connected to the gate wiring 105 is formed in the switching region TrA and a gate electrode 108 connected to the gate pad portion GPA is formed in correspondence with the gate pad portion GPA A gate pad electrode 109 connected to the gate wiring 105 is formed.

Next, as shown in FIG. 3B, an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx) is deposited on the gate wiring 105, the gate electrode 108 and the gate pad electrode 109 A gate insulating film 112 is formed on the entire surface.

Next, an oxide semiconductor material such as an amorphous-indium gallium zinc oxide (a-IGZO) or a zinc tin oxide (ZTO) is deposited on the gate insulating layer 112 by sputtering to form an oxide semiconductor material layer 118 And subsequently forming an inorganic insulating layer 120 on the oxide semiconductor material layer 115 by depositing silicon oxide, preferably as an inorganic insulating material.

Thereafter, a photoresist layer (not shown) is formed on the inorganic insulating layer 120 to form a light transmission region, a blocking region, and a slit shape with respect to the photoresist layer (not shown) Alternatively, a diffractive exposure or a halftone exposure is performed using an exposure mask (not shown) having a coating film further provided thereon and having a light transmittance lower than that of the transmissive region and a transflective region larger than the blocking region by adjusting the amount of light passing therethrough do.

Next, the exposed photoresist layer (not shown) is developed to form a first photoresist pattern 190a having a first thickness corresponding to the gate electrode 108 in the switching region TrA above the inorganic insulating layer 120, The inorganic insulating layer 120 is exposed in correspondence with the gate pad electrode 109 in the gate pad portion GPA and the switching region TrA and the gate pad portion GPA are exposed And a second photoresist pattern 190b having a second thickness smaller than the first thickness is formed corresponding to all of the regions except for the first thickness.

Next, as shown in FIG. 3C, the inorganic insulating layer 120, the oxide semiconductor material layer 115, and the gate insulating layer 112 exposed to the outside of the first and second photoresist patterns 190a and 190b Thereby forming a gate pad contact hole GPH exposing the gate pad electrode 109 in the gate pad portion GPA.

Next, as shown in FIG. 3D, first ashing with anisotropic characteristics is performed to remove the second photoresist pattern (191b in FIG. 3C) having the second thickness, thereby forming the switching region TrA The inorganic insulating layer 120 is exposed. At this time, the first photoresist pattern 190a is reduced in thickness by the first ashing process, but still remains on the inorganic insulating layer 120 corresponding to the gate electrode 108. In this case,

Next, as shown in FIG. 3E, the inorganic insulating layer (120 in FIG. 3D) exposed at the outside of the first photoresist pattern 190a and the oxide semiconductor material layer (115 in FIG. 3D) The oxide semiconductor layer 116 and the arsenic oxide layer 116 are sequentially deposited on the gate insulating layer 112 in correspondence to the gate electrode 108 in the switching region TrA by exposing the oxide semiconductor layer 116 to a BOE buffered oxide etchant, An insulating pattern 121 is formed. In this case, the silicon oxide (SiO2) forming the inorganic insulating layer (120 in FIG. 3D) and the oxide semiconductor layer material layer (115 in FIG. 3D) have substantially similar etch rates to BOE, 120 are exposed to the BOE for a longer time, the area and width of the oxide semiconductor layer 116 located at the bottom are larger, and the inorganic insulating pattern 121 located on the oxide semiconductor layer 116 is completely overlapped with the oxide semiconductor layer 116 As shown in Fig. The oxide semiconductor layer 116 and the inorganic insulating pattern 121 located on the oxide semiconductor layer 116 are tapered at their side surfaces with respect to the gate insulating layer 112 and the oxide semiconductor layer 116 .

Next, as shown in FIG. 3F, ashing is performed with isotropic characteristics to reduce the thickness and the width of the first photoresist pattern 190a, so that the inorganic insulating pattern 121, So that the rim of the first photoresist pattern 190a is exposed outside the first photoresist pattern 190a.

Next, as shown in FIG. 3G, dry etching is performed to remove the rim of the inorganic insulating pattern 121 (FIG. 3F) exposed outside the first photoresist pattern 190a, thereby forming an etch stopper (122). 3F) exposed at the outside of the first photoresist pattern 190a is removed so that the edge of the oxide semiconductor layer 116 has a larger width and the edge of the etch stopper 122 is removed, And is exposed to the outside. In order to expose the edge of the oxide semiconductor layer 116 to a sufficient width outside the etch stopper 122, it is preferable to expose the edge of the oxide semiconductor layer 116 to a sufficient width so that the contact with the source and drain electrodes (142 and 144 in FIG. 3H) It is for this reason.

The edge of the oxide semiconductor layer 116 is exposed to dry etching for removing the rim of the inorganic insulating pattern 121 in the process of forming the etch stopper 122, Since the edge of the oxide semiconductor layer 116 is exposed to the dry etching for forming the etch stopper 122, the characteristics of the semiconductor layer and the characteristics of the thin film transistor No degradation occurs. In this case, the portion of the oxide semiconductor layer 116 where the channel layer is formed is not covered by the etch stopper 122.

Next, as shown in FIG. 3H, the first photoresist pattern (190a in FIG. 3G) remaining on the etch stopper 122 is stripped to remove the etch stopper 122 .

A transparent conductive material layer (not shown) may be formed on the etch stopper 122 by depositing a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) And one of the second metal materials such as aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo) and chromium (Cr) is sputtered continuously Thereby forming a second metal layer (not shown).

Next, the second metal layer (not shown) and the transparent conductive material layer (not shown) are masked and simultaneously patterned to cross the gate wiring 105 on the gate insulating layer 112 to form the pixel region P And the source and drain electrodes 142 (142a, 140b) are formed in the switching region TrA so as to be spaced apart from each other above the etch stopper 122. The source and drain electrodes 142a, , 142b, 144 (144a, 144b).

At this time, the data line 140 and the source electrode 142 of the double-layer structure are connected to each other. In addition, a pixel pattern 145 having a bilayer structure is formed in the pixel region P while being connected to the drain electrode 144 having the bilayer structure. At this time, the pixel pattern 145 is formed so as to overlap with the gate wiring 105 at the front end, so that the gate wiring 105 and the pixel pattern 145 at the front end overlapping with each other form the gate insulating film 112 as a dielectric layer, Thereby forming a capacitor StgC.

At the same time, in the gate pad portion GPA, auxiliary gate pad electrodes 147 (147a and 147b) having a double-layer structure are formed which are in contact with the gate pad electrode 109 exposed through the gate pad contact hole GPH And a data pad electrode 148 (148a, 148b) having a double layer structure is formed on the gate insulating layer 112 in the data pad unit DPA.

The source and drain electrodes 142 and 144 of the double layer structure which are spaced apart from the gate electrode 108, the gate insulating film 112 and the oxide semiconductor layer 116 sequentially stacked in the switching region TrA, (Tr).

Next, as shown in FIG. 3I, the data line 140, the source and drain electrodes 142 and 144, the pixel pattern 145 (FIG. 3H) and the auxiliary gate pad electrode 147 (FIG. 3H) And the data pad electrode (148 in FIG. 3H), an inorganic insulating material such as silicon oxide or silicon nitride is deposited on the entire surface to form the protective layer 155.

Subsequently, the data line 140, the source and drain electrodes 142 and 144, the pixel pattern 145 (FIG. 3H), the auxiliary gate pad electrode 147 (FIG. 3H), and the data pad electrode 148) corresponding to the pixel pattern (145 in FIG. 3H), the assist gate pad electrode (147 in FIG. 3H) and the data pad electrode (148 in FIG. 3H) A pixel electrode 160 connected to the lower layer 144a of the drain electrode 144 and having a single layer structure of a transparent conductive material is formed in the pixel region P by removing the upper layers 145b, And an auxiliary gate pad electrode 162 having a single layer structure of a transparent conductive material is formed also in the gate pad portion GPA. In addition, the data pad unit (DPA) also includes the data pad electrode 164 having a single layer structure of the transparent conductive material, thereby completing the array substrate 101 according to the present invention.

On the other hand, the array substrate 101 according to the present invention includes the steps of forming the gate wiring 105 and the gate electrode 108, forming the oxide semiconductor layer 116 and the etch stopper 122, Drain electrodes 142 and 144 and forming the pixel electrode 160 and the gate pad electrode 162 of the single layer structure and the data pad electrode 164 and the protective layer 155, It is understood that a total of four masking processes have been carried out.

Therefore, the manufacturing process is simplified by omitting the mask process twice in total compared to the conventional manufacturing method of the array substrate having the oxide semiconductor layer and the etch stopper, thereby improving the productivity per unit time and reducing the manufacturing cost .

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It can be understood that

101: substrate 108: gate electrode
109: Gate pad electrode 112: Gate insulating film
116: oxide semiconductor layer 121: inorganic insulating pattern
DLA: Data wiring formation area DPA: Data pad part
GPA: gate pad portion P: pixel region
TrA: switching area

Claims (10)

Forming a first metal layer on the substrate;
Forming a gate line and a gate electrode by patterning the first metal layer through a first mask process;
Sequentially forming a gate insulating film, an oxide semiconductor material layer, and an inorganic insulating layer on the gate wiring and the gate electrode;
Patterning the inorganic insulating layer and the oxide semiconductor material layer through a second mask process to form an oxide semiconductor layer corresponding to the gate electrode and an etch stopper exposing both side edges of the oxide semiconductor layer;
Sequentially forming a transparent conductive material layer and a second metal layer on the etch stopper;
A source electrode and a drain electrode which are in contact with both side ends of the oxide semiconductor layer, respectively, and a data line extending from the drain electrode, Forming a pixel pattern;
Forming a protective layer on the data line, the source electrode, the drain electrode, and the pixel pattern;
Forming a pixel electrode by patterning the protective layer and the second metal layer of the pixel pattern through a fourth mask process
Wherein the substrate is a substrate.
The method according to claim 1,
Wherein forming the gate wiring and the gate electrode through the first mask process includes forming a gate pad electrode connected to an end of the gate wiring,
Wherein forming the data line through the third mask process includes forming a data pad electrode connected to an end portion of the data line and an assist gate pad electrode contacting the gate pad electrode,
Wherein the step of forming the pixel electrode through the fourth masking step includes patterning the second metal layer of each of the assist gate pad electrode and the data pad electrode.
The method according to claim 1,
Wherein forming the oxide semiconductor layer and the etch stopper through the second mask process comprises:
A first photoresist pattern corresponding to the gate electrode and having a first thickness is formed on the inorganic insulating layer to expose the inorganic insulating layer corresponding to a gate pad electrode connected to an end of the gate wiring, Forming a second photoresist pattern corresponding to a region other than the region where the electrode and the gate pad electrode are formed and having a second thickness smaller than the first thickness;
Forming a gate pad contact hole exposing the gate pad electrode by removing the inorganic insulating layer, the oxide semiconductor material layer, and the gate insulating layer exposed to the outside of the first and second photoresist patterns;
Exposing the inorganic insulating layer by performing first ashing to remove the second photoresist pattern;
Removing the inorganic insulating layer and the oxide semiconductor material layer exposed to the outside of the first photoresist pattern to sequentially form the oxide semiconductor layer and the inorganic insulating pattern on the gate insulating film corresponding to the gate electrode;
Performing a second ashing process to reduce a thickness and a width of the first photoresist pattern so that the rim of the inorganic insulating pattern is exposed to the outside of the first photoresist;
Removing the rim of the inorganic insulating pattern exposed to the outside of the first photoresist pattern to form the etch stopper;
Removing the first photoresist pattern
Wherein the substrate is a substrate.
The method of claim 3,
Wherein the first ashing has anisotropic properties and the second ashing has isotropic properties.
The method of claim 3,
The oxide semiconductor material layer is made of a-IGZO (amorphous-Indium Gallium Zinc Oxide) or ZTO (Zinc Tin Oxide)
Wherein the inorganic insulating layer is made of silicon oxide (SiO2)
Wherein the oxide semiconductor material layer and the inorganic insulating layer are simultaneously etched by BOE (Buffered Oxide Etchant).
The method of claim 3,
Wherein the rim of the inorganic insulating pattern is removed by dry etching.
The method according to claim 1,
Wherein the pixel electrode is formed so as to overlap with the front-end gate wiring, and the front-end gate wiring, the pixel electrode, and the gate insulating film overlap each other to form a storage capacitor.
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