KR102010393B1 - Array substrate for in-plane switching mode liquid crystal display device and method of fabricating the same - Google Patents

Abstract

A method of manufacturing an array substrate for a transverse electric field type liquid crystal display device according to the present invention includes: a first mask process step of forming a gate wiring extending in one direction on a substrate and a gate electrode connected to the gate wiring and the gate wiring; Forming a gate insulating film over the gate wiring and the gate electrode; Stacking a pure amorphous silicon layer, an impurity amorphous silicon pattern, and a conductive metal layer on the gate insulating layer; A second mask process step of forming a source drain pattern and a data line over the gate insulating layer, the active layer overlapping the gate electrode and the impurity amorphous silicon pattern; Forming a first transparent conductive material layer over the source drain pattern; An ohmic contact layer formed on the first transparent conductive material layer to be spaced apart from each other by removing the source and drain electrodes, the pixel electrode in direct contact with the drain electrode, and the impurity amorphous silicon pattern exposed between the source and drain electrodes A third mask process step of forming a; A fourth mask process step of forming a protective film on the entire surface of the substrate; And a fifth mask process step of forming a common electrode on the passivation layer.

Description

Array board for transverse electric field type liquid crystal display device and manufacturing method thereof {ARRAY SUBSTRATE FOR IN-PLANE SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME}

The present invention relates to an array substrate for a transverse electric field type liquid crystal display device and a manufacturing method thereof, and more particularly to an array substrate for a transverse electric field type liquid crystal display device capable of reducing the number of masks and a method of manufacturing the same.

Recently, with increasing interest in information display and increasing demand for using a portable information carrier, a lightweight flat panel display (FPD), which replaces a conventional display device, a cathode ray tube (CRT), is used. The research and commercialization of Korea is focused on. In particular, the liquid crystal display (LCD) of the flat panel display device is an image representing the image using the optical anisotropy of the liquid crystal, is excellent in resolution, color display and image quality, and is actively applied to notebooks or desktop monitors have.

Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, an active matrix liquid crystal display device (AM-LCD: abbreviated as an active matrix LCD, abbreviated as a liquid crystal display device) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has the best resolution and video performance. It is attracting attention. The liquid crystal display includes a color filter substrate on which a common electrode is formed, an array substrate on which pixel electrodes are formed, and a liquid crystal interposed between the two substrates. In such a liquid crystal display, the common electrode and the pixel electrode are caused by an electric field applied up and down. It is excellent in the characteristics, such as transmittance | permeability and aperture ratio, by the method of driving a liquid crystal. However, the liquid crystal drive due to the electric field applied up and down has a disadvantage that the viewing angle characteristics are not excellent.

Accordingly, a transverse field type liquid crystal display device having excellent viewing angle characteristics has been proposed to overcome the above disadvantages.

Hereinafter, a general transverse electric field type liquid crystal display device will be described in detail with reference to FIG. 1.

1 is a plan view of one pixel area of an array substrate for a general transverse electric field type liquid crystal display device.

As shown, a plurality of gate wires 45 extend in one direction, intersect with the plurality of gate wires 45 to define a plurality of pixel regions P, and a plurality of data wires 51 It is composed.

In addition, each of the plurality of pixel areas P is connected to the data line 51 and the gate line 45 defining the gate electrode 43, the gate insulating layer (not shown), the semiconductor layer (not shown), and the source. And a thin film transistor Tr, which is a switching element including drain electrodes 55 and 58, is formed.

Further, in each pixel region P, a plate-shaped pixel electrode 60 is formed in direct contact with the drain electrode 58 of the thin film transistor Tr.

In addition, a front surface of the display area in which the plurality of pixel areas P is formed overlaps the plate-shaped pixel electrode 60 corresponding to each pixel area P, and a plurality of bar-shaped openings oa are formed. The provided common electrode 75 is formed.

A conventional array substrate for a transverse electric field type liquid crystal display device having such a structure is usually manufactured through six mask processes.

2A through 2F are cross-sectional views illustrating a manufacturing process of a conventional array substrate for a transverse electric field type liquid crystal display device, and are provided in one switching region TrA, a pixel region P, a gate pad portion GPA, and a data pad portion DPA. This is a cross section.

As shown in FIG. 2A, a first mask process may be performed to form a gate line (not shown) and a gate electrode 43 connected thereto on the substrate 40 on the substrate 40. The gate pad electrode 44 is formed in the gate pad part GPA.

Next, as shown in FIG. 2B, a second mask process is performed to form a gate insulating film 46 on the entire surface of the substrate 40 including the gate wiring (not shown) and the gate electrode 43. On the switching region TrA of the pixel region P, a doped amorphous silicon pattern 48 and an active layer 49a corresponding to the gate electrode 43 are sequentially formed on the gate insulating layer 46.

Next, as shown in FIG. 2C, a third mask process is performed to correspond to each pixel region P on the front surface of the substrate 40 on which the active layer 49a and the doped amorphous silicon pattern 48 are formed. The pixel electrode 50 is formed.

Next, as shown in FIG. 2D, the fourth mask process is performed, and the data pad 52 intersecting the gate line (not shown) and the data pad part DPA connected thereto are provided with the data pad electrode 53. The source and drain electrodes 54 and 56 spaced apart from each other are formed on the doped amorphous silicon pattern 48 of FIG. 2C.

Thereafter, ohmic contact layers 49b spaced apart from each other are formed under the source and drain electrodes 54 and 56. In this case, the active layer 49a and the ohmic contact layer 49b form a semiconductor layer 49, and the gate electrode 43, the gate insulating layer 46, the semiconductor layer 49, the source and drain electrodes 54, 56 forms a thin film transistor Tr.

Next, as shown in FIG. 2E, a fifth mask process is performed to form a protective layer 60 over the data line 52 and the source and drain electrodes 54 and 56, and the gate and data pad parts. Gate and data pad contact holes 62 and 64 exposing the gate pad electrode 44 and the data pad electrode 53 are formed in the GPA and DPA, respectively.

Next, as illustrated in FIG. 2F, a sixth mask process may be performed to cover a plurality of bars corresponding to the pixel electrodes 50 provided in each pixel area P on the passivation layer 60. The conventional array substrate 10 for a transverse electric field type liquid crystal display device is completed by forming a common electrode 65 having an opening oa.

As described above, when the array substrate 10 for the transverse electric field type liquid crystal display device is completed by performing six mask processes, one mask process includes coating of photoresist, exposure using an exposure mask, development of exposed photoresist, and etching. And a unit process such as a strip of photoresist, there is a problem that the more the mask process, the longer the process time takes.

In addition, the productivity per unit time is lowered, thereby increasing the manufacturing cost of the array substrate, and the more the number of processes, the greater the probability of occurrence of defects, resulting in a lower production yield. There is a problem of this weakening.

Five mask processes have been proposed to solve this problem.

In general, five mask processes use a halftone mask to simultaneously form the source and drain electrodes and the semiconductor layer through one mask process, thereby reducing manufacturing time and manufacturing cost by reducing one mask process compared to the conventional six mask processes. can do.

However, the array substrate fabricated by the conventional five-mask process is configured in such a way that the lower semiconductor layer (amorphous silicon layer) is exposed around the source and drain electrodes and the data wiring.

3A to 3D are enlarged cross-sectional views of part of a switching region A and a data wiring part B of a transverse electric field type liquid crystal display array substrate fabricated by five conventional mask processes.

As illustrated, a gate electrode 43 is formed in the switching region A on the substrate 50, and a gate insulating layer 46 is formed on the gate electrode 43 and the data wiring portion B of the switching region A. ) Is formed. The first and second semiconductor layers 84a and 84b and the source and drain metal layers 80 are continuously formed on the gate insulating layer 46.

The source and drain electrodes 81 and 83 and the data connected thereto are etched by etching the source and drain metal layers 80 formed on the first and second semiconductor layers 84a and 84b on the substrate 50 through photosensitive patterns. The process of forming the wiring 82 is performed.

At this time, as shown in FIG. 3A, the source drain metal layer 80 and the data line 82 are overetched under the first and second photosensitive patterns 78a and 78b to form a source drain metal layer 80 and data. The wiring 82 is patterned inward of the first and second photosensitive patterns 78a and 78b.

Thereafter, as shown in FIG. 3B, a process of removing the first and second semiconductor layers 84a and 84b exposed around the first and second photosensitive patterns 78a and 78b through dry etching is performed. . In this case, since portions of the first and second semiconductor layers 84a and 84b covered by the first and second photosensitive patterns 78a and 78b are not etched by dry etching, the first and second photosensitive layers are not etched. The patterns 78a and 78b are patterned to protrude outward from the source drain metal layer 80 and the data line 82 in an overetched state.

As shown in FIG. 3C, the first and second photosensitive patterns 78a and 78b are ashed to expose the lower source drain metal layer 80 and the data line 82.

3D, the exposed source drain metal layer 80 is removed to form a source electrode 81 and a drain electrode 83 spaced apart from the upper portion of the gate electrode 43. The first semiconductor layer 84a exposed between the drain electrodes 81 and 83 is etched to form an ohmic contact layer, thereby forming the semiconductor layer 85a and the source and drain electrodes 81 and 83.

Then, the data wiring 82 is formed in the data wiring portion B. At this time, a dummy pattern 85b formed of the second semiconductor layer 84b is positioned below the data line 82.

At this time, in the switching region A, the semiconductor layer 85a is exposed to the outside of the source and drain electrodes 81 and 83 to the outside of about 1.8 μm or more, and also in the data wiring portion B, The dummy pattern 85b disposed below is exposed to the outside of the data line 82 by about 1.8 μm or more.

The exposed region may be defined as an active tail. Since the active tail is a very large area exposed to the outside of the source and drain electrodes 81 and 83 and the data line 82, the exposed area is generated by receiving light. The effect of photo-leakage current also causes a big problem.

Due to the photo-leakage current generated as described above, a coupling phenomenon occurs with the adjacent pixel electrode, and there is a problem in that a wavy noise is generated on the screen of the liquid crystal panel.

Therefore, in consideration of the formation of the active tail, it is necessary to widen the area between neighboring data lines, so that a high resolution narrow bezel cannot be realized.

In addition, there is a problem that the opening region is encroached by the active tail.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and reduces the length of an active tail protruding to the periphery of the source and drain electrodes and the data line, thereby improving luminance characteristics by securing an opening area, and achieving uniform image quality. It is a first object of the present invention to provide an array substrate for a transverse electric field type liquid crystal display device and a method of manufacturing the same.

In addition, a second object of the present invention is to provide an array substrate for a transverse electric field type liquid crystal display device and a method of manufacturing the same, which can improve productivity per unit time by reducing the number of mask processes to reduce manufacturing cost and manufacturing time.

In order to achieve the above object, a method of manufacturing an array substrate for a transverse electric field type liquid crystal display device according to the present invention includes a first mask process step of forming a gate wiring extending in one direction on the substrate and a gate electrode connected to the gate wiring; ; Forming a gate insulating film over the gate wiring and the gate electrode; Stacking a pure amorphous silicon layer, a doped amorphous silicon pattern, and a conductive metal layer on the gate insulating layer; A second mask process step of forming a source drain pattern and a data line on the gate insulating layer and overlying an active layer corresponding to the gate electrode and the doped amorphous silicon pattern; Forming a first transparent conductive material layer over the source drain pattern; An ohmic contact formed on the first transparent conductive material layer to be spaced apart from each other by removing a source and drain electrode, a pixel electrode in direct contact with the drain electrode, and the doped amorphous silicon pattern exposed between the source and drain electrodes A third mask process step of forming a layer; A fourth mask process step of forming a protective film on the entire surface of the substrate; And a fifth mask process step of forming a common electrode on the passivation layer.

At this time, the third mask process step, the first photosensitive pattern having a first thickness for forming the pixel electrode and the source and drain electrode on the first transparent conductive material layer, and a second thickness thinner than the first thickness Forming a second photosensitive pattern having; First etching the first transparent conductive material layer exposed to the outside of the first and second photosensitive patterns to expose the source drain pattern; Second etching the exposed source drain pattern to form the drain electrode spaced apart from the source electrode; Removing the doped amorphous silicon layer exposed between the source and drain electrodes to form an ohmic contact layer spaced apart from each other; Performing ashing to remove the second photosensitive pattern having the second thickness; And removing the first transparent conductive material layer exposed to the outside of the first photosensitive pattern remaining on the source and drain electrodes to form the pixel electrode in direct contact with the drain electrode.

The source electrode includes the source pattern and a transparent pattern on the source pattern, and the data line extends from the source pattern to directly contact the passivation layer.

The primary etching is characterized in that the wet etching.

At this time, the etchant of the wet etching is oxalic acid (Oz acid; oxalic acid).

The secondary etching is characterized in that the selected one of dry etching or wet etching.

In this case, when the secondary etching is dry etching, the etching gas is composed of sulfur hexafluoride (SF6), oxygen (O ₂ ), chlorine (Cl ₂ ), hydrogen chloride (HCl), carbon tetrafluoride (CF4) and combinations thereof At least one selected from the group.

Further, when the secondary etching is wet etching, the etching solution is a copper etching solution or a mixed acid including at least one selected from the group consisting of phosphoric acid (H 3 PO 4), nitric acid (HNO 3), acetic acid (CH 3 COOH), and a combination thereof. It is characterized by.

Further forming a gate pad electrode and a first data link wiring on the same layer as the gate electrode in the first mask process step, and further forming a second data link wiring extending from the data line in the second mask process step. Form.

In the second mask process step, a first data pad electrode connected to the first data link wiring and a second data pad electrode connected to the second data link wiring are further formed.

In the fifth mask process step, a gate auxiliary pad electrode in contact with the gate pad electrode is further formed.

In the fifth mask process step, a first data auxiliary pad electrode in contact with the first data pad electrode and a second data auxiliary pad electrode in contact with the second data pad electrode are further formed.

On the other hand, the array substrate for a transverse electric field type liquid crystal display device according to the present invention comprises a gate wiring extending in one direction formed on the substrate and a gate electrode connected to the gate wiring; A gate insulating film covering the gate wiring and the gate electrode; A semiconductor layer formed over the gate insulating layer, the active layer overlapping the gate electrode, and an ohmic contact layer spaced apart from each other above the active layer; A source electrode and a drain electrode formed to be spaced apart from each other above the semiconductor layer; First and second data lines formed over the gate insulating layer to define a pixel area crossing the gate lines; Dummy patterns formed under the first and second data lines; A plate-shaped pixel electrode formed in direct contact with the drain electrode; A protective layer covering the source and drain electrodes, the pixel electrode, and the first and second data lines; A transparent common electrode formed on the protective layer and having a plurality of openings spaced at predetermined intervals in a bar shape corresponding to the pixel electrode, wherein the first and second data lines and the protective layer are in direct contact with each other; The both ends of the source and drain electrodes and the semiconductor layer coincide with each other, and both ends of the first and second data lines and the dummy pattern coincide with each other.

A transparent pattern is positioned on the source electrode.

The dummy pattern includes a first pattern of pure amorphous silicon and a second pattern of doped amorphous silicon.

The method further includes a first data link wiring formed on the same layer as the gate electrode and a second data link wiring extending from the second data wiring.

The first contact hole exposing the first data wire, the second and third contact holes exposing the first data link wire, and the first and second exposing the first and second data pad electrodes. Contains two data pad contact holes.

A first data link connection electrode connecting the first data line and the first data link line through the first contact hole and the second contact hole, the third contact hole and the first data pad contact hole; And a second data link connection electrode connecting the first data link line and the first data pad electrode.

And a second data auxiliary pad electrode connecting the second data pad electrode formed to extend from the second data line through the second data pad contact hole.

On the other hand, the array substrate for a transverse electric field type liquid crystal display device according to a modification of the present invention, the gate wiring extending in one direction formed on the substrate and the gate electrode connected to the gate wiring; A gate insulating film covering the gate wiring and the gate electrode; A semiconductor layer formed over the gate insulating layer, the active layer overlapping the gate electrode, and an ohmic contact layer spaced apart from each other above the active layer; A source electrode and a drain electrode formed to be spaced apart from each other above the semiconductor layer; First and second data lines formed over the gate insulating layer to define a pixel area crossing the gate lines; Dummy patterns formed under the first and second data lines; A plate-shaped pixel electrode formed in direct contact with the drain electrode; A protective layer covering the source and drain electrodes, the pixel electrode, and the first and second data lines; A transparent common electrode formed on the protective layer and having a plurality of openings spaced at predetermined intervals in a bar shape corresponding to the pixel electrode, wherein the first and second data lines and the protective layer are in direct contact with each other; The semiconductor layer and the dummy pattern may be exposed to the outside of the source and drain electrodes and the first and second data lines to be 0.2 μm or less.

A transparent pattern is positioned on the source electrode.

The dummy pattern includes a first pattern of pure amorphous silicon and a second pattern of doped amorphous silicon.

1 is a plan view of one pixel area of an array substrate of a conventional transverse electric field type liquid crystal display device.
2A to 2F are cross-sectional views illustrating manufacturing steps of a conventional array substrate for a transverse electric field type liquid crystal display device.
3A to 3D are enlarged cross-sectional views of a portion of a channel portion and a data wiring portion of an array substrate for a transverse electric field type liquid crystal display device manufactured by a conventional five mask process.
4 is a plan view of one pixel area of an array substrate of a transverse electric field type liquid crystal display device according to an exemplary embodiment of the present invention.
5A through 5E are cross-sectional views illustrating manufacturing steps of an array substrate for a transverse electric field type liquid crystal display device according to an exemplary embodiment of the present invention, which shows cross sections taken along lines IV-IV and V-V of FIG. 4.
6A to 6H are cross-sectional views illustrating a detailed process of FIG. 5C.
7 is a graph showing a correlation between the length of an active tail and transmittance in an array substrate for a transverse electric field type liquid crystal display according to an exemplary embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

4 is a plan view of one pixel area of an array substrate of a transverse electric field type liquid crystal display device according to an exemplary embodiment of the present invention.

As shown, a plurality of gate lines 102 extend in one direction, and intersect with the plurality of gate lines 102 to define a plurality of pixel regions P, and a plurality of data lines 130a and 130b. ) Is configured.

In addition, each of the plurality of pixel regions P is connected to the data lines 130a and 130b and the gate line 102 defining the gate electrodes 108, the gate insulating layer (not shown), and the semiconductor layer (not shown). ) And a thin film transistor Tr, which is a switching element including source and drain electrodes 133 and 136, is formed.

In addition, a pixel electrode 139 is formed in each pixel region P to be in direct contact with the drain electrode 136 of the thin film transistor Tr.

In addition, a plurality of bars overlapping the pixel electrode 139 corresponding to each pixel area P and spaced at regular intervals corresponding to the pixel electrode 139 on the entire display area in which the plurality of pixel areas P are formed. A common electrode 160 having an opening (oa) having a bar shape is formed. In this case, although the common electrode 160 is formed on the entire display area, a portion corresponding to one pixel area P is indicated by a dotted line for the purpose of the drawing.

In particular, the array substrate 100 for a transverse electric field type liquid crystal display device of the present invention is characterized in that the transparent pattern 138 is further formed on the source electrode 133, the present invention is also the first and second data pad It is characterized by being divided into portions (DPA1, DPA2).

That is, in the first data pad part DPA1 of the array substrate 100 for a transverse electric field type liquid crystal display device of the present invention, the first data wire 130a and the first data link wire 107 are formed of first and second contact holes. The first data link wiring 107 is connected to the first data link connecting electrode 159 through the first data link electrode 131, the third contact hole 151, and the first data pad 149 and 150. The second data link connecting electrode 165 and the first data auxiliary pad electrode 163 are formed through the contact hole 152.

In the second data pad unit DPA2, a second data pad electrode 106 extending from the second data line 130b is connected to the second data auxiliary pad electrode 164 through the second data pad contact hole 148. Is formed in connection with

The array substrate 100 for a transverse electric field type liquid crystal display device having such a configuration has a common pixel electrode 139 for each pixel region P and a plurality of bar-shaped openings oa corresponding thereto. The voltage is applied to the electrode 160 to form an electric field.

An array substrate for a transverse electric field type liquid crystal display device according to an embodiment of the present invention having such a structure is manufactured through five mask processes.

5A through 5E are cross-sectional views illustrating manufacturing steps of an array substrate for a transverse electric field type liquid crystal display device according to an exemplary embodiment of the present invention, which shows cross sections taken along lines IV-IV and V-V of FIG. 4.

For convenience of description, an area in which the thin film transistor Tr, which is a switching element, is formed in each pixel area P is defined as a switching area TrA.

In addition, the region where the gate pad electrode is formed is defined as the gate pad portion GPA, the first and second data link wirings, and the region where the first and second data pad electrodes are formed as the data pad portion DPA.

First, as illustrated in FIG. 5A, a metal material such as aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo), and molybdenum alloy (eg, on a transparent insulating substrate 101) may be used. One or more materials of MoTi) and chromium (Cr) are deposited on the entire surface to form a first metal layer (not shown).

Thereafter, the first metal layer (not shown) is coated with a photoresist, exposure using a photo mask, development of the exposed photoresist, etching of the first metal layer (not shown), and a strip of photoresist. By patterning the first mask process including a unit process of, a plurality of gate wirings (not shown) having a single layer or multilayer structure and extending in a first direction are formed, and at the same time, the switching region TrA A gate electrode 108 connected to a gate line (not shown) is formed, and a gate pad electrode 109 connected to the gate line (not shown) and having a single layer or a multilayer structure is formed on the gate pad part GPA. do.

Here, the data pad unit DPA of the present invention may be defined by being divided into a first data pad unit DPA1 and a second data pad unit DPA2, and the first data pad unit DPA1 may be defined as a first data wire ( 4, the second data pad part DPA2 is adjacent to the first data pad part DPA1 and is adjacent to the first data line 130a of FIG. 4 (see FIG. 4). 130b).

The first data pad part DPA1 and the second data pad part DPA2 are alternately formed adjacent to each other.

In this case, a first data link wiring 107 is formed in the first data pad part DPA1, and a second data link wiring 110 is formed in the second data pad part DPA2.

Next, as shown in FIG. 5B, an inorganic insulating material such as silicon oxide (SiO) is formed on the gate wiring (not shown), the gate electrode 108, the gate pad electrode 109, and the first data link wiring 107. ₂ ) or by depositing silicon nitride (SiNx) or by applying an organic insulating material such as benzocyclobutene (BCB) or photo acryl (photo acryl) to form a gate insulating film 115 on the entire surface of the substrate 101 .

In the present invention, for example, the gate insulating film 115 is formed of an organic insulating material.

Subsequently, a pure amorphous silicon layer 120a and a doped amorphous silicon layer 120b are formed on the gate insulating layer 115, and a metal material such as aluminum (Al), is deposited on the doped amorphous silicon layer 120b. A second metal layer (not shown) is formed by depositing one or more materials of aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo), molybdenum alloy (MoTi), and chromium (Cr) on the front surface. .

Thereafter, by forming a photoresist layer (not shown) on the second metal layer (not shown), and performing a second mask process for exposing and developing the photoresist layer. As shown in FIG. 5B, the second metal layer (not shown), the pure amorphous silicon layer 120a and the doped amorphous silicon pattern 120b at the bottom thereof are etched and removed to remove the second metal layer (not shown). A plurality of data lines 130 are formed to cross the gate lines (not shown) and extend in the second direction to define the plurality of pixel regions P. Referring to FIG.

At the same time, the source drain pattern 132 connected to the data line 130 in the switching region TrA, the doped amorphous silicon pattern 120b sequentially stacked below and the active layer 120a of pure amorphous silicon. To form.

In addition, a first data pad electrode 131 and a second data pad electrode 106 are formed in the first and second data pad units DPA1 and DPA2.

In this case, the gate insulating layer 115 is referenced to the first and second data wires 130a and 130b of FIG. 4, the first data pad electrode 131, and the second data pad electrode 106 under the manufacturing process. As a result, a dummy pattern 121 including a first pattern (not shown) of pure amorphous silicon and a second pattern (not shown) of the doped amorphous silicon is formed thereon.

Herein, the source and drain electrodes 133 and 136 of FIG. 5C and the ohmic contact layer 120c of FIG. 5C are formed in a later mask process, so that the source drain pattern 132 may be formed in the second mask process. ) And the source and drain electrodes 133 and 136 of FIG. 5C and the ohmic contact layer 120c of FIG. 5C through the doped amorphous silicon pattern 120b. Active tails exposed to the outside of the drain electrodes 133 and 136 of FIG. 5C are not generated.

We will discuss this in more detail later.

Next, a transparent conductive material such as indium tin oxide (ITO) or the like on the source drain pattern 132, the data line 130, the first data pad electrode 131, and the second data pad electrode 106. Indium-zinc oxide (IZO) is deposited on the entire surface to form a first transparent conductive material layer (not shown).

As shown in FIG. 5C, the source electrode 133 and the drain which are spaced apart from the upper portion corresponding to the gate electrode 108 and expose the lower doped amorphous silicon pattern 120b using a halftone mask. The third mask process of forming the electrode 136 and forming the pixel electrode 139 in direct contact with the drain electrode 136 is performed.

In this case, the first transparent conductive material layer (not shown) is removed on the data line 130 by using a wet etching selectivity, but the transparent pattern 138 is formed on the source electrode 133.

In addition, the ohmic contact layer 120c is formed by removing the lower doped amorphous silicon pattern 120b exposed between the source and drain electrodes 133 and 136 and exposing the lower pure amorphous silicon layer 120a. do.

In this case, the pure amorphous silicon layer 120a and the ohmic contact layer 120c form the semiconductor layer 120.

By this process, the gate electrode 108, the gate insulating layer 115, the semiconductor layer 120, and the source and drain electrodes 133 and 136 spaced apart from each other are sequentially stacked in the switching region TrA. The transistor Tr is completed.

Next, as shown in FIG. 5D, the thin film transistor Tr, the pixel electrode 139, the data line 130, the first data pad electrode 131, and the second data pad electrode 106) Inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the front surface, or an organic insulating material such as benzocyclobutene (BCB) or photo acryl is applied. To form a protective layer 140.

Subsequently, the gate pad contact hole 147 exposing the gate pad electrode 109 is exposed in the gate pad part GPA by patterning the protective layer 140 and the gate insulating layer 115 disposed below the protective layer 140. Form.

In the first data pad part DPA1, the first contact hole 149 exposing the data wire 130a and the second and third contact holes 150 and 151 exposing the first data link wire 107. In addition, a first data pad contact hole 152 exposing the first data pad electrode 131 is formed.

In the second data pad part DPA2, a second data pad contact hole 148 exposing the second data pad electrode 106 is formed.

Next, a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), is deposited on the entire surface of the substrate 101 on the passivation layer 140 (not shown). ).

Subsequently, as illustrated in FIG. 5E, a fifth mask process is performed on the second transparent conductive material layer (not shown) and patterned to correspond to the pixel electrodes 139 provided in each pixel region P. FIG. The common electrode 160 having an opening oa having a bar shape is formed.

At the same time, in the gate pad part GPA, the gate auxiliary pad electrode 162 is formed to contact the gate pad electrode 109 through the gate pad contact hole 147.

In the first data pad part DPA1, the first data link connection electrode 159 contacting the first data line 130a and the first data link line 107 through the first contact hole 149 is provided. The second data link connecting electrode 165 is formed to contact the first data link wiring 107 and the first data pad electrode 131 through the second contact hole 150.

The first data link wiring 107 is brought into contact with the first data link wiring 107 and the first data pad electrode 131 through the third contact hole 151 and the first data pad contact hole 152. ) And a second link connecting electrode 165 and a first data auxiliary pad electrode 163 for electrically connecting the first data pad electrode 131 to each other.

In addition, in the second data pad part DPA2, the second data auxiliary pad electrode contacting the second data pad electrode 106 and the second data link wiring 110 through the second data pad contact hole 148 ( 164).

In this case, although not shown, as a modification, the common electrode may be formed instead of forming the pixel electrode in the third mask process step, and the pixel electrode may be formed instead of the common electrode in the fifth mask process step.

Thus, the array substrate 100 for a transverse electric field type liquid crystal display device of the present invention is completed.

On the other hand, the array substrate 100 for a transverse electric field type liquid crystal display device according to an embodiment of the present invention is provided with a pixel electrode 139 in the form of a plate on the bottom and the pixel region (P) through the protective film 140 on the upper portion thereof. In response to the passivation layer 140, a plurality of bar-shaped openings (oa) are provided, and a common electrode 160 formed on the front of the display area is provided to have a common top structure. As an example, a common electrode is formed of a transparent conductive material on each pixel region P in front of the display area, and the common electrode together with the protective layer is interposed therebetween. A plate-shaped pixel electrode having a plurality of openings exposing the plurality of openings may form a pixel top structure provided to contact the thin film transistor.

Here, conventionally, after forming the pure amorphous silicon layer, the doped amorphous silicon pattern, and the source drain pattern, the source and drain electrodes are separated from the source and drain electrodes by ashing and etching through a halftone mask. A semiconductor layer including an ohmic contact layer from which the doped amorphous silicon exposed to the region is removed is formed.

However, when ashing and etching are performed using a halftone mask on the patterned source drain pattern, the pure amorphous silicon layer, and the doped amorphous silicon pattern, the pure source of the amorphous silicon outside the source and drain electrodes as the source drain pattern is overetched. An active tail is generated that exposes the layer and the doped amorphous silicon pattern.

At this time, the exposed active tail is about 1.8 μm or more.

However, in the present invention, after forming the pure amorphous silicon layer 120a, the doped amorphous silicon layer 120b, and the source drain pattern 132, the pixel electrode 139 is not subjected to a separate ashing and etching process. The source and drain electrodes 133 and 136 and the semiconductor layer 120 are formed in the process of patterning the pixel electrode 139 in the third mask process for forming the source, thereby over-etching the source drain pattern 132. And an active tail phenomenon in which the semiconductor layer 120 is exposed to the outside of the drain electrodes 133 and 136 may be prevented.

  Accordingly, the present invention can reduce the active tail to about 0.2 μm or less, thereby narrowing the area between neighboring data wires, thereby implementing a high resolution narrow bezel.

In addition, since the opening area encroached by the active tail can be deleted, luminance can be improved, and the amount of leakage current generated in the active tail can be minimized, thereby minimizing the generation of wavy noise on the screen. It is effective to realize uniform image quality.

In addition, by directly connecting the drain electrode and the pixel electrode without forming the drain contact hole, the area used to form the existing drain contact hole is used as the opening area, thereby improving the transmittance.

In addition, by forming a transparent pattern on the source electrode, the resistance of the source electrode can be lowered, and there is a protective film effect for protecting the source and drain electrodes.

Here, a third mask process for forming a pixel electrode and an ohmic contact layer using a halftone mask, which is a characteristic configuration of the present invention, will be described in detail with reference to FIGS. 6A to 6H.

6A to 6H are cross-sectional views illustrating a detailed process of FIG. 5C.

First, as shown in FIG. 6A, the gate electrode 108, the gate pad electrode 109, and the first data link wiring 107 are formed on the substrate 101, and then the gate electrode 108 and the gate pad electrode ( 109 and a gate insulating film 115 formed on the first data link wiring 107, the doped amorphous silicon pattern 120b and the active layer 120a of pure amorphous silicon and the source drain on the gate insulating film 115. The pattern 132 and the data line 130, the first data pad electrode 131, the second data pad electrode 106, and the second data link wiring 110 are formed.

In addition, a transparent conductive material, for example, indium, may be formed on the source drain pattern 132, the data line 130, the first data pad electrode 131, the second data pad electrode 106, and the second data link wiring 110. Tin-oxide (ITO) or indium-zinc-oxide (IZO) is deposited on the entire surface to form the first transparent conductive material layer 139a.

Next, as shown in FIG. 6B, a photoresist is applied on the entire surface of the substrate 101 on which the first transparent conductive material layer 139a is formed to form the photosensitive layer 191. Here, the photosensitive layer 191 will be described using a positive type in which the exposed portion is developed as an example.

Next, the mask M including the transmissive part B1, the blocking part B2, and the transflective part B3 is positioned on the spaced upper portion of the photosensitive layer 191, and then a third mask process is performed.

In this case, the transflective portion B3 forms a slit shape or a translucent film on the mask M, thereby lowering the intensity of light or lowering the amount of light transmitted so that only part of the photosensitive layer is exposed.

In addition, the blocking unit B2 functions to completely block light, and the transmitting unit B1 transmits light so that the photosensitive layer 191 is completely chemically changed, that is, completely exposed by light.

On the other hand, in the switching region (TrA), the transmissive portion (B1), the blocking portion (B2) is located on both sides of the transmissive portion (B1) and the transflective portion (B3) is located in the remaining region.

Here, the transmission part B1 is a channel of the source drain pattern 132 in which source and drain electrodes (see 133 and 136 of FIG. 5E) are formed later. Corresponding to the central portion, the blocking portion B2 corresponds to the position where the source and drain electrodes (see 133 and 136 of FIG. 5E) and the pixel electrode (139 of FIG. 5E) are formed, and the transflective portion B3 is the transmissive portion B1. ) And the other part except for the blocking part B2.

Next, light is irradiated to the upper portion of the mask M to expose and develop a lower photosensitive layer 191.

In this way, all of the photosensitive layer (191 of FIG. 6B) corresponding to the transmissive portion B1 is removed, and the upper portion of the photosensitive layer (191 of FIG. 6B) of the portion corresponding to the transflective portion B2 is removed. The photosensitive layer (191 of FIG. 6B) corresponding to the blocking portion B3 is left at its initial applied height.

Accordingly, as shown in FIG. 6C, a first photosensitive pattern 192 having a first thickness and a second photosensitive pattern 193 having a second thickness smaller than the first thickness are formed on the substrate 101. do.

In this case, the first photosensitive pattern 192 is formed corresponding to a portion where a source and drain electrode (see 133 and 136 of FIG. 5E) and a pixel electrode (139 of FIG. 5E) will be formed later, and the second photosensitive pattern ( 193 is formed corresponding to the remaining regions except for the switching region TrA.

In addition, the photosensitive pattern is not formed in the center portion of the source drain pattern 132.

Next, as shown in FIG. 6D, a process of first wet etching and removing the first transparent conductive material layer 139a exposed to the periphery of the first photosensitive pattern 192 is performed. The source drain pattern 132 is exposed.

Here, when the first wet etching is performed, an indium tin oxide (ITO) or an indium zinc oxide (IZO) may be formed using a selectivity ratio between the data line 130 and the first transparent conductive material layer 139a. An etching solution capable of etching the transparent conductive material is used to prevent damage to the source drain pattern 132.

Here, the etchant capable of etching a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) may be an oxalic acid series.

Next, as illustrated in FIG. 6E, the source and drain electrodes 133 and 136 are spaced apart from each other by performing dry etching to etch and remove the center portion of the exposed source drain pattern 132. do.

Here, when the dry etching is performed, materials such as copper (Cu), molybdenum alloy (MoTi), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), and the like can be etched. By using an etching gas that is not used, damage to regions other than the source and drain electrodes 133 and 136 may not occur.

In this case, when the dry etching is performed, at least one selected from the group consisting of sulfur hexafluoride (SF6), oxygen (O ₂ ), chlorine (Cl ₂ ), hydrogen chloride (HCl), carbon tetrafluoride (CF4) and combinations thereof Etching gas may be further included.

On the other hand, when the source and drain electrodes 133 and 136 are formed in the method of manufacturing the transverse electric field type liquid crystal display array substrate 100 according to the embodiment of the present invention, the dry etching has been described. Depending on the material forming the), the wet etching may be performed to form the source and drain electrodes.

In this case, the wet etching solution may be a copper etching solution, or a mixed acid including at least one selected from the group consisting of phosphoric acid (H 3 PO 4), nitric acid (HNO 3), acetic acid (CH 3 COOH), and a combination thereof.

In addition, the ohmic contact layer 120c is formed by removing the lower doped amorphous silicon pattern 120b exposed between the source and drain electrodes 133 and 136 and exposing the lower pure amorphous silicon layer 120a. do.

In this case, the pure amorphous silicon layer 120a and the ohmic contact layer 120c form the semiconductor layer 120.

Next, as shown in FIG. 6F, after the etching process is completed, an ashing process of removing the photosensitive pattern used as the mask is performed to remove the second photosensitive pattern 193 having the second thickness.

At this time, when the ashing process, at least one selected from the group consisting of sulfur hexafluoride (SF6), oxygen (O ₂ ), helium (He), carbon tetrafluoride (CF4), argon (Ar) and combinations thereof. Ashing containing may be used.

In addition, during the ashing process, the first transparent conductive material layer 139a deposits an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx), or an organic insulating material such as benzocyclobutene. (BCB) or photo acryl is applied over the gate insulating film 115 formed.

Therefore, the first transparent conductive material layer 139a may be formed to cover the gate insulating layer 115 to serve as a protective layer. Thus, during the ashing process, the second photosensitive pattern 193 may be removed without damaging the gate insulating layer 115. Can be removed.

Thereafter, as shown in FIG. 6G, the first transparent conductive material layer exposed to the outside of the first photosensitive pattern 192 remaining on the source and drain electrodes 133 and 136 through the second wet etching process (see FIG. 6F). By removing the 139a, the transparent pattern 138 is formed on the source electrode 133, and the pixel electrode 139 is formed in direct contact with the drain electrode 136.

Here, when the second wet etching process is performed, an etching solution capable of etching only a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) may be used to prevent damage to the data line.

Next, as shown in FIG. 6H, a strip is performed to remove the first photosensitive pattern 192 remaining on the source and drain electrodes 133 and 136.

By this process, the array substrate 100 for a transverse electric field type liquid crystal display device according to the embodiment of the present invention is completed.

Meanwhile, the method of manufacturing the array substrate 100 for a transverse electric field type liquid crystal display device has been described only with respect to the embodiment of the present invention having a common top structure. Also, the common electrode provided below is made of a transparent conductive material, and the pixel electrode formed on the common electrode with the transparent conductive material is formed to have a plurality of openings exposing the common electrode. It is obvious that an array substrate in which the upper and lower positions are changed between the common electrode and the pixel electrode overlapping each other can be realized by performing the process.

7 is a graph showing a correlation between the length of an active tail and transmittance in an array substrate for a transverse electric field type liquid crystal display device according to an exemplary embodiment of the present invention.

7 represents the length of the active tail, and the vertical axis represents the transmittance.

As shown, it can be seen that as the length of the active tail increases, the transmittance decreases.

Accordingly, the array substrate for a transverse electric field type liquid crystal display device according to the present invention has almost no active tail, so that the amount of leakage current generated in the active tail can be minimized, thereby minimizing the generation of wavy noise of the screen, thereby making it more uniform. The effect is that one image can be realized.

In addition, since the opening area encroached by the active tail can be deleted, there is an effect of improving the brightness and transmittance.

In the case of the array substrate 100 for a transverse electric field type liquid crystal display device according to the first embodiment of the present invention manufactured as described above, the mask process is simplified and the manufacturing cost is reduced by reducing the mask process once compared to the conventional process by performing a total of five mask processes. It is characterized by the fact that it can be reduced.

In addition, since the drain contact hole is not formed separately, as much as the area of the omitted drain contact hole forming region is secured to the opening region, the transmittance of the pixel can be improved accordingly.

In addition, by forming the pixel electrode 139 on the source and drain electrodes 133 and 136, the resistance of the source electrode 133 can be lowered, and a protective film effect for protecting the source and drain electrodes 33 and 136 is provided. have.

In addition, the present invention defines a data pad unit DPA divided into first and second data pad units DPA1 and DPA2, and the first data pad unit DPA1 is connected to the first data line 130a. The first data link wiring 107 is formed of the same material as the gate electrode 108 and the gate wiring (not shown), and the second data pad part DPA2 is formed of the second data wiring 130b, The second data link wires 110 extending from the second data wires 130b are formed on the same layer as the source and drain electrodes 133 and 136 so that the spaced intervals between the adjacent data wires 130a and 130b are reduced. It can be narrowed, enabling high-resolution narrow bezels to be implemented simultaneously.

That is, when the first data link wiring 107 and the second data link wiring 110 are formed to be formed of the same material on the same layer as the data line 130, the neighboring first data link wiring 107 is formed. And a minimum separation distance between the second data link wires 110 is 2 μm, and the widths of the neighboring first data link wires 107 and the second data link wires 110 must also be at least 2 μm. In order to form the first data link wiring 107 and the second data link wiring 110 with the same layer and the same material, an area of at least 8 μm is required.

This is a very difficult situation to implement the high resolution and narrow bezel that is recently required.

In addition, when the active tail is formed, the separation distance between the neighboring first data link wiring 107 and the second data link wiring 110 should be formed at least 4 μm.

In contrast, the present invention allows the neighboring first data link wiring 107 and the second data link wiring 110 to be formed on different layers so that the neighboring first data link wiring 107 and the second data link are formed. The area between the wirings 110 can be minimized.

Through this, a narrow bezel can be implemented even in a high resolution display device.

The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

101: substrate 106: data pad electrode
107: first data link wiring 108: gate electrode
109: gate pad electrode 110: second data link wiring
115: gate insulating film 120a: active layer
120c: ohmic contact layer 120: semiconductor layer
121: dummy pattern 130: data wiring
132: source drain pattern 133: source electrode
136: drain electrode 138: ITO pattern
139: pixel electrode 140: protective film
147: gate pad contact hole 148: second data pad contact hole
149, 150, and 151: first to third contact holes
152: first data pad contact hole
159 and 165: first and second data link connection electrodes
160: common electrode 162: gate auxiliary pad electrode
163 and 164: first and second data auxiliary pad electrodes

Claims (22)

A first mask process step of forming a gate wiring extending in one direction on the substrate and a gate electrode connected to the gate wiring;
Forming a gate insulating film over the gate wiring and the gate electrode;
Stacking a pure amorphous silicon layer, a doped amorphous silicon pattern, and a conductive metal layer on the gate insulating layer;
A second mask process step of forming a source drain pattern and a data line on the gate insulating layer and overlying an active layer corresponding to the gate electrode and the doped amorphous silicon pattern;
Forming a first transparent conductive material layer over the source drain pattern;
An ohmic contact formed on the first transparent conductive material layer to be spaced apart from each other by removing a source and drain electrode, a pixel electrode in direct contact with the drain electrode, and the doped amorphous silicon pattern exposed between the source and drain electrodes A third mask process step of forming a layer;
A fourth mask process step of forming a protective film on the entire surface of the substrate;
A fifth mask process step of forming a common electrode on the passivation layer,
In the first mask process step, the gate pad electrode and the first data link wiring are formed on the same layer as the gate electrode,
And in the second mask process step, extend from the data line to form a second data link line.
The method of claim 1,
The third mask process step,
Forming a first photosensitive pattern having a first thickness for forming the pixel electrode, the source and drain electrodes, and a second photosensitive pattern having a second thickness thinner than the first thickness on the first transparent conductive material layer; Wow;
First etching the first transparent conductive material layer exposed to the outside of the first and second photosensitive patterns to expose the source drain pattern;
Second etching the exposed source drain pattern to form the drain electrode spaced apart from the source electrode;
Removing the doped amorphous silicon layer exposed between the source and drain electrodes to form an ohmic contact layer spaced apart from each other;
Performing ashing to remove the second photosensitive pattern having the second thickness;
Removing the first transparent conductive material layer exposed outside the first photosensitive pattern remaining on the source and drain electrodes to form the pixel electrode in direct contact with the drain electrode
Method of manufacturing an array substrate for a transverse electric field type liquid crystal display device comprising a.
The method of claim 2,
The source electrode may include the source drain pattern and the transparent pattern on the source drain pattern, and the data line may extend from the source drain pattern to directly contact the passivation layer. Method of manufacturing a substrate.
The method of claim 2,
The primary etching is a wet etching method of manufacturing an array substrate for a transverse electric field type liquid crystal display device.
The method of claim 4, wherein
The wet etching etchant is oxalic acid (Oz acid; oxalic acid) manufacturing method of an array substrate for a transverse field type liquid crystal display device.
The method of claim 2,
The secondary etching is a method of manufacturing an array substrate for a transverse electric field liquid crystal display device, characterized in that the selected one of dry etching or wet etching.
The method of claim 6,
When the secondary etching is a dry etching, the etching gas is from the group consisting of sulfur hexafluoride (SF6), oxygen (O ₂ ), chlorine (Cl ₂ ), hydrogen chloride (HCl), carbon tetrafluoride (CF4) and combinations thereof A method of manufacturing an array substrate for a transverse electric field type liquid crystal display device comprising at least one selected.
The method of claim 6,
When the secondary etching is wet etching, the etching solution is a copper etching solution, or a mixed acid including at least one selected from the group consisting of phosphoric acid (H 3 PO 4), nitric acid (HNO 3), acetic acid (CH 3 COOH) and combinations thereof. A method of manufacturing an array substrate for a transverse electric field liquid crystal display device.
delete The method of claim 1,
In the second mask process step,
And forming a first data pad electrode connected to the first data link wiring, and a second data pad electrode connected to the second data link wiring.
The method of claim 1,
In the fifth mask process step,
And forming a gate auxiliary pad electrode in contact with the gate pad electrode.
The method of claim 10,
In the fifth mask process step,
A first data auxiliary pad electrode in contact with the first data pad electrode and a second data auxiliary pad electrode in contact with the second data pad electrode are formed. Way.
A gate wiring extending in one direction formed on the substrate and a gate electrode connected to the gate wiring;
A gate insulating film covering the gate wiring and the gate electrode;
A semiconductor layer formed over the gate insulating layer, the active layer overlapping the gate electrode, and an ohmic contact layer spaced apart from each other above the active layer;
A source electrode and a drain electrode formed to be spaced apart from each other above the semiconductor layer;
First and second data lines formed over the gate insulating layer to define a pixel area crossing the gate lines;
Dummy patterns formed under the first and second data lines;
A plate-shaped pixel electrode formed in direct contact with the drain electrode;
A protective layer covering the source and drain electrodes, the pixel electrode, and the first and second data lines;
A transparent common electrode formed on the protective layer and having a plurality of openings spaced at regular intervals in a bar shape corresponding to the pixel electrode;
The first and second data lines are in direct contact with the protective layer,
Both ends of the source and drain electrodes and the semiconductor layer coincide with each other, and both ends of the first and second data lines and the dummy pattern coincide with each other.
A first data link wiring formed on the same layer as the gate electrode;
And a second data link wiring formed to extend from the second data wiring.
The method of claim 13,
And a transparent pattern positioned on the source electrode.
The method of claim 13,
And the dummy pattern comprises a first pattern of pure amorphous silicon and a second pattern of doped amorphous silicon.
delete The method of claim 13,
First and second data pad electrodes formed on the same layer as the first and second data lines;
A first contact hole exposing the first data line, second and third contact holes exposing the first data link wire, and first and second data exposing the first and second data pad electrodes. An array substrate for a transverse electric field liquid crystal display device comprising a pad contact hole.
The method of claim 17,
A first data link connection electrode connecting the first data line and the first data link line through the first contact hole and the second contact hole, the third contact hole and the first data pad contact hole; And a second data link connection electrode connecting the first data link line and the first data pad electrode to each other.
The method of claim 17,
And a second data auxiliary pad electrode connected to the second data pad electrode formed to extend from the second data line through the second data pad contact hole. .
A gate wiring extending in one direction formed on the substrate and a gate electrode connected to the gate wiring;
A gate insulating film covering the gate wiring and the gate electrode;
A semiconductor layer formed over the gate insulating layer, the active layer overlapping the gate electrode, and an ohmic contact layer spaced apart from each other above the active layer;
A source electrode and a drain electrode formed to be spaced apart from each other above the semiconductor layer;
First and second data lines formed over the gate insulating layer to define a pixel area crossing the gate lines;
Dummy patterns formed under the first and second data lines;
A plate-shaped pixel electrode formed in direct contact with the drain electrode;
A protective layer covering the source and drain electrodes, the pixel electrode, and the first and second data lines;
A transparent common electrode formed on the protective layer and having a plurality of openings spaced at regular intervals in a bar shape corresponding to the pixel electrode;
The first and second data lines are in direct contact with the protective layer,
The semiconductor layer and the dummy pattern are exposed to the outside of the source and drain electrodes and the first and second data lines to be 0.2 μm or less.
A first data link wiring formed on the same layer as the gate electrode;
And a second data link wiring formed to extend from the second data wiring.
The method of claim 20,
And a transparent pattern positioned on the source electrode.
The method of claim 20,
And the dummy pattern comprises a first pattern of pure amorphous silicon and a second pattern of doped amorphous silicon.

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