KR20120113430A - Method for fabricating array substrate for fringe field switching mode liquid crystal display device - Google Patents

Abstract

PURPOSE: A method for manufacturing an array substrate for a fringe field switching mode liquid crystal display device is provided to reduce the number of mask processes. CONSTITUTION: A photoresist pattern is eliminated. A pixel electrode(121) contacts a portion of an end of a drain electrode. The pixel electrode corresponds to a pixel area. A second protective layer is formed on a frontal side of a substrate with the pixel electrode. A common electrode(125) is formed on the second protective layer. The common electrode includes openings of bar shapes which are separated at a fixed interval. The openings correspond to the pixel area.

Description

Method for fabricating array substrate for fringe field switching mode liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fringe field switched mode liquid crystal display device, and more particularly, to an array substrate for a fringe field switched mode liquid crystal display device using a five-mask process including data wiring and source and drain electrodes made of copper (Cu) or copper alloy. It relates to a manufacturing method.

Liquid crystal display devices (LCDs), which are used for TVs and monitors due to their high contrast ratio and are advantageous for displaying moving images, are characterized by optical anisotropy and polarization of liquid crystals. The principle of image implementation by

Such a liquid crystal display is an essential component of a liquid crystal panel bonded through a liquid crystal layer between two side-by-side substrates, and realizes a difference in transmittance by changing an arrangement direction of liquid crystal molecules with an electric field in the liquid crystal panel. do.

Recently, an active matrix liquid crystal display device that drives liquid crystal with an electric field formed up-down has been widely used because of its excellent resolution and video performance. However, liquid crystal driving due to an electric field that is applied up-down has a disadvantage in that the viewing angle characteristics are inferior.

Accordingly, various methods have been proposed in order to overcome the disadvantage that the viewing angle is narrow. Among them, a liquid crystal driving method by a transverse electric field is attracting attention.

1 is a cross-sectional view of a general transverse electric field type liquid crystal display device.

As shown in the figure, the lower substrate 1, which is an array substrate, and the upper substrate 3, which is a color filter substrate, are spaced apart from each other and face each other. A liquid crystal layer 5 is interposed between the upper and lower substrates 1, .

On the lower substrate 1, the pixel electrode 23 and the common electrode 25 are formed on the same plane, and the liquid crystal layer 5 has a horizontal electric field L formed by the pixel electrode 23 and the common electrode 25. Works by.

A thin film transistor (TFT) is formed in each pixel area defined by a gate wiring (not shown) and a data wiring (not shown) in the lower substrate 1 of the transverse field type liquid crystal display device. 3) a color filter layer (not shown) and a black matrix (not shown) are formed and bonded by a seal material (not shown) such as an epoxy resin.

However, such a transverse field type liquid crystal display device has an advantage of improving the viewing angle, but has a disadvantage of low aperture ratio and low transmittance.

Therefore, in order to improve the disadvantage of the transverse field type liquid crystal display, a fringe field switching mode LCD is characterized in that the liquid crystal is operated by a fringe field.

FIG. 2 is a cross-sectional view schematically illustrating an array substrate for a typical fringe field switching mode liquid crystal display device, and is a cross-sectional view of one pixel area.

As shown in the drawing, on the array substrate 1 for a fringe field switching mode liquid crystal display device, a data wiring (not shown) defining a pixel region P by crossing a plurality of gate wirings (not shown) and gate wirings (not shown). ) Is configured.

In this case, a thin film transistor Tr is formed in the switching region TrA, which is an intersection point of the gate wiring (not shown) and the data wiring (not shown) of the pixel region P, and the pixel is formed in the display area where the image is substantially realized. The electrode 21 and the common electrode 25 are formed.

The thin film transistor Tr includes the semiconductor layer 15, the source and drain electrodes 17 and 19 including the gate electrode 11, the gate insulating layer 13, the active layer 15a and the ohmic contact layer 15b. Is done.

In addition, a plate-shaped pixel electrode 21 is formed on the gate insulating layer 13 in contact with the drain electrode 19, and the front surface of the substrate 1 including the pixel electrode 21. The protective layer 23 is formed in this.

The common electrode 25 is formed over the passivation layer 23 in front of the display area including the pixel areas P, and the common electrode 25 is spaced apart from each other in correspondence with each pixel area P. An opening OP having a bar shape is provided.

Accordingly, a voltage is applied to the pixel electrode 21 and the common electrode 25 to form a fringe field.

On the other hand, the array substrate 1 of the fringe field switching mode liquid crystal display device having the above-described structure is formed by repeating the process of depositing a thin film and photolithography using a mask several times, typically at least six masks It can only be formed.

Here, the one-time mask process involves various processes such as cleaning, application of the photoresist film, exposure using an exposure mask, development, and etching, and thus, the productivity decreases as the number of mask processes increases, thereby increasing the process cost. do.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and a first object of the present invention is to provide a method of manufacturing a transverse electric field type liquid crystal display device which can reduce the number of mask processes.

In addition, the second object is to improve the aperture ratio and transmittance.

In order to achieve the above object, the present invention includes the steps of forming a gate wiring extending in one direction and a gate electrode connected thereto on a substrate in which a plurality of pixel regions are defined; Forming a gate insulating film over the gate wiring and the gate electrode; Forming source and drain electrodes spaced apart from each other on the gate insulating layer, the semiconductor layer including an active layer and an ohmic contact layer; Forming a first protective layer on an entire surface of the substrate including the source and drain electrodes; Forming a photoresist pattern on a portion of the first passivation layer except for the pixel region; Removing the first protective layer exposed to the outside of the photoresist pattern, exposing a portion of ends of the gate insulating layer and the drain electrode corresponding to the pixel area; Forming a metal layer on an entire surface of the substrate including the photoresist pattern and the gate insulating layer; Removing the photoresist pattern to form a pixel electrode in contact with a portion of an end of the drain electrode corresponding to the pixel region; Forming a second passivation layer on an entire surface of the substrate including the pixel electrode; A method of manufacturing an array substrate for a fringe field switching mode liquid crystal display device comprising forming a common electrode having a plurality of bar-shaped openings spaced apart from each other by a predetermined distance on the second passivation layer. to provide.

In this case, the source and drain electrodes are made of copper (Cu) or a copper alloy, and in the forming of the metal layer, the metal layer located on the photoresist pattern and the metal layer located on the gate insulating layer are cut off. This happens.

In addition, the photoresist pattern is removed through a lift-off process, and the metal layer and the common electrode are made of one selected from indium tin oxide (ITO) or indium zinc oxide (IZO).

The forming of the gate wiring and the gate electrode connected thereto may further include forming a gate pad electrode at one end of the gate wiring, and forming the data wiring may include data at one end of the data wiring. The method further includes forming a pad electrode.

The second protective layer may include a gate pad contact hole exposing the gate pad electrode and a data pad contact hole exposing the data pad electrode, and the gate may contact the gate pad electrode through the gate pad contact hole. The pad auxiliary electrode is further formed.

The data pad auxiliary electrode may be further formed to contact the data pad electrode through the data pad contact hole. The forming of the semiconductor layer and the source and drain electrodes may include a gate over the gate wiring and the gate electrode. An insulating film, a pure amorphous silicon layer, an impurity amorphous silicon layer, and a first metal layer are sequentially formed to form source and drain electrodes spaced apart from each other on the data line and the impurity amorphous silicon layer, and between the source and drain electrodes. The exposed impurity amorphous silicon layer is removed to form an ohmic contact layer.

As described above, according to the present invention, an array substrate of a fringe field switching mode liquid crystal display device including a data wiring and a source and a drain electrode of copper (Cu) or copper alloy material is manufactured through a 5-mask process using lift-off. As a result, the aperture ratio is improved, and through this, the viewing angle characteristic, the aperture ratio, and the transmittance are improved, and at the same time, the number of mask processes is reduced to reduce manufacturing costs and simplify the process.

1 is a cross-sectional view of a general transverse electric field type liquid crystal display device.
2 is a cross-sectional view schematically showing an array substrate for a typical fringe field switched mode liquid crystal display device.
3A to 3G are cross-sectional views illustrating manufacturing steps of an array substrate for a fringe field switching mode liquid crystal display device according to a first embodiment of the present invention.
4A is a plan view schematically showing a part of one pixel area of an array substrate for a typical fringe field switched mode liquid crystal display device;
4B is a plan view schematically showing a part of one pixel area of an array substrate for a fringe field switched mode liquid crystal display device according to a first embodiment of the present invention;
5A through 5J are cross-sectional views illustrating manufacturing steps of an array substrate for a fringe field switching mode liquid crystal display device according to a second exemplary embodiment of the present invention.
FIG. 6 is a plan view schematically showing a part of one pixel area of an array substrate for a fringe field switched mode liquid crystal display device according to a second embodiment of the present invention; FIG.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the drawings.

- First Embodiment -

3A to 3G are cross-sectional views illustrating manufacturing steps of an array substrate for a fringe field switching mode liquid crystal display device according to a first embodiment of the present invention.

In this case, for convenience of description, a portion in which the thin film transistor Tr in each pixel region P is to be formed will be defined as a switching region TrA.

First, as shown in FIG. 3A, a first metal material having low resistance on the transparent insulating substrate 101, for example, molybdenum (Mo), aluminum (Al), aluminum alloy (AlNd), and copper (Cu) The material selected from the copper alloy is deposited on the entire surface to form a first metal layer (not shown).

Then, application of a photoresist (not shown), exposure using a photo mask, development of the exposed photoresist (not shown), etching of the first metal layer (not shown), and stripping of the photoresist (not shown) A first mask process including a series of unit processes is performed to form a plurality of gate wirings (not shown) extending in the first direction by patterning a first metal layer (not shown), and simultaneously to the switching region TrA. A gate electrode 111 connected to the gate wiring (not shown) is formed.

In the gate pad part GPA, a gate pad electrode 111 b is formed to extend a gate wiring (not shown).

In this case, the first metal layer (not shown) may be formed by continuously depositing different metal materials into a double layer or more and patterning the same, thereby forming a gate wiring (not shown) and a gate electrode 111 having a double layer or triple layer structure. have.

Next, as shown in FIG. 3B, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is disposed on the gate wiring (not shown), the gate pad electrode 111b, and the gate electrode 111. By depositing, a gate insulating layer 113 is formed on the entire surface of the substrate 101.

Subsequently, pure amorphous silicon and impurity amorphous silicon are sequentially deposited on the gate insulating layer 113 to form the pure amorphous silicon material layer 114a and the impurity amorphous silicon material layer 114b.

Subsequently, a second metal layer 116 is formed by depositing a material selected from among copper (Cu) and a copper alloy, which are metal materials having low resistance, on the impurity amorphous material layer 114b.

Here, copper (Cu) has a lower specific resistance than aluminum (Al) or molybdenum (Mo) to reduce the wiring resistance of the second metal layer 116.

Then, as shown in FIG. 3C, application of a photoresist (not shown), exposure using a photo mask, development of the exposed photoresist (not shown), etching of the second metal layer (116 of FIG. 3B), and photoresist A second mask process including a series of unit processes such as strips (not shown) is performed, and the second metal layer (116 in FIG. 3B) is patterned to extend in the second direction to form a gate wiring (not shown). A plurality of data lines 117 defining pixel regions P are formed to cross each other.

In the data pad part GPA, the data wiring 117 extends to form the data pad electrode 117a. At this time, the data line 117 and the data pad electrode 117a are formed of a double layer semiconductor pattern made of pure and impurity amorphous silicon materials.

At the same time, source and drain electrodes 118 and 119 spaced apart from each other in the switching region TrA are formed, and the impurity amorphous material layer (114b in FIG. 3B) is formed using the source and drain electrodes 118 and 119 as masks. By etching and removing, the ohmic contact layer 115b exposing the active layer 115a is formed.

As a result, the semiconductor layer 115 including the gate electrode 111, the gate insulating film 113, the active layer 115a of pure amorphous silicon and the ohmic contact layer 115b of impurity amorphous silicon, a source spaced apart from each other, The thin film transistor Tr including the drain electrodes 118 and 119 is formed.

In this case, the thin film transistor Tr may have a 'U' shape in a region forming a channel, and may be modified in various shapes.

Next, as shown in FIG. 3D, an inorganic insulating material, for example, silicon oxide (SiO 2) or silicon nitride (SiNx), or an organic insulating material, for example, benzocyclobutene (BCB), may be formed on the entire surface of the substrate 101. ) Or a first protective layer 120a made of photo acryl.

The first protective layer 120a serves to prevent the ohmic contact layer 115b from being damaged in the process of forming the pixel electrode 121 (see FIG. 3E). We will discuss this in more detail later.

Next, as shown in FIG. 3E, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the first passivation layer 120a and a third mask process is performed. By proceeding and patterning, the plate-shaped pixel electrode 121 is formed on the entire display area formed of the pixel areas P. FIG.

Here, the process of patterning the pixel electrode 121 is performed through dry etching, which is a wet etching solution (etchant) and chemical resistance of copper (Cu) weak in the process of patterning the pixel electrode 121 through wet etching. This is because it reacts with the source and drain electrodes 118 and 119 made of a copper alloy to produce a CD (critical dimension) deviation that is larger than the designed value by overetching.

Therefore, in order to prevent the above problem from occurring, when the source and drain electrodes 118 and 119 are made of copper (Cu) or a copper alloy, the pixel electrode 121 is patterned through dry etching.

Here, in the process of patterning the pixel electrode 121, the transparent conductive material on the active layer 115a should be completely removed. In the process of patterning the pixel electrode 121 through dry etching, the dry etching gas of the dry etching is anisotropic ( Since the anisotropy has an etching characteristic, in the absence of the first protective layer 120a, the active layer 115a is overetched by a dry etching gas for patterning the pixel electrode 121, thereby forming an active layer 115a. ) Will cause damage.

In particular, in the present invention, since the source and drain electrodes 118 and 119 are made of copper (Cu) or a copper alloy having poor chemical resistance, the source and drain electrodes 118 and 119 made of copper (Cu) or copper alloy are dry. In the process of being exposed to the etching gas, the source and drain electrodes 118 and 119 and the etching gas may react to form reaction byproducts.

The reaction by-products formed in this way remain on top of the active layer 115a and cause a problem of damaging the channel.

Accordingly, the array substrate for the fringe field switching mode liquid crystal display device of the present invention forms the first protective layer 120a on the entire surface of the substrate 101 including the source and drain electrodes 118 and 119, thereby forming the pixel electrode 121. ), The active layer 115a is prevented from being damaged in the third mask process of forming.

Next, as shown in FIG. 3F, an inorganic insulating material such as silicon oxide (SiO 2) or silicon nitride (SiN x) is deposited on the entire surface of the substrate 101 or an organic insulating material such as benzocyclo. Butene (BCB) or photo acryl (photo acryl) is applied to form a second protective layer (120b).

Subsequently, the fourth mask process is performed to expose the drain contact hole 119a, the gate pad electrode 111b, and the data so that a part of the end of the drain electrode 119 and a part of the pixel electrode 121 to be connected to the drain electrode 119 are exposed. The gate pad contact hole 111b and the data pad contact hole 117b exposing the pad electrode 117b are formed.

Next, as shown in FIG. 3G, a transparent conductive material, for example, indium, is formed on the second protective layer 120b having the drain contact hole 119a, the gate pad contact hole 111b, and the data pad contact hole 117b. The common electrode 125 is formed over the entire display area of the pixel areas P by depositing tin-oxide (ITO) or indium-ink-oxide (IZO) and patterning the fifth mask process. .

In this case, the common electrode 125 is formed to have a plurality of openings OP having a bar shape spaced apart from each other by a predetermined distance corresponding to each pixel area P. The openings OP may be formed in the pixel electrode 121. Correspondingly formed.

At the same time, a connection electrode 130 is formed to electrically connect the drain electrode 119 and the pixel electrode 121 through the drain contact hole 119a. In the gate pad part GPA, the gate pad contact hole 111b is formed. The gate pad auxiliary electrode 111 c is formed to contact the gate pad electrode 111 a through the first through the second pad. In the data pad part DPA, the data pad contacts the data pad electrode 117 a through the data pad contact hole 117 b. The pad auxiliary electrode 117c is formed.

In this case, the gate pad auxiliary electrode 111c and the data pad auxiliary electrode 117c may be omitted.

Meanwhile, in the drawing, although the plurality of openings OP having a bar shape are formed in the common electrode 125, as a further modification, the plurality of openings OP formed in the common electrode 125 of each pixel region P are shown. The opening OP may be omitted to correspond to the common electrode 125 and may be formed with respect to the pixel electrode 121.

The array substrate for the fringe field switching mode liquid crystal display device manufactured as described above may be completed through a five mask process, and by forming a fringe field through the pixel electrode 121 and the common electrode 125 made of a transparent conductive material. In addition, the viewing angle characteristics are excellent, and at the same time, the aperture ratio and the transmittance are superior to the general transverse electric field type liquid crystal display device.

On the other hand, the array substrate for the fringe field switching mode liquid crystal display device according to the first embodiment of the present invention has a disadvantage that the aperture ratio is lower than that for the fringe field switching mode liquid crystal display array substrate formed through the six mask process.

This is caused by shortening one mask process in a typical six mask process and proceeding with a five mask process.

This will be described in more detail with reference to FIGS. 4A and 4B below.

FIG. 4A is a plan view schematically illustrating a part of one pixel area of a typical fringe field switched mode liquid crystal display array substrate, and FIG. 4B is a fringe field switched mode liquid crystal display array according to a first embodiment of the present invention. A plan view schematically showing a part of one pixel region of the substrate.

In this case, for convenience of description, a region in which a plurality of pixel regions P is formed is defined as a display region and a portion in which the thin film transistor Tr, which is a switching element, is formed in each pixel region P is called a switching region TrA. .

As shown in FIGS. 4A to 4B, a plurality of gate wirings 12 and 112 extend in a first direction, and a plurality of gate wirings 12 and 112 intersect with a plurality of gate wirings 12 and 112 by extending in a second direction. A plurality of data wirings 17 and 117 are defined to define the pixel region P of the pixel.

Each pixel region P is connected to the gate wirings 12 and 112 and the data wirings 17 and 117, and includes gate electrodes 11 and 111, a gate insulating film (not shown), and an active layer of pure amorphous silicon. A semiconductor layer (not shown) formed of an ohmic contact layer (not shown) of impurity amorphous silicon and a thin film transistor (Tr) including source and drain electrodes 18, 19, 118, and 119 spaced apart from each other. It is.

In addition, plate-shaped pixel electrodes 21 and 121 contacting the drain electrodes 19 and 119 of the thin film transistor Tr are formed in each pixel region P, and a plurality of spaced apart bars are provided. Common electrodes 25 and 125 having openings OP are formed.

In this case, although the thin film transistor Tr is shown as an example in which the region forming the channel forms a 'U' shape, it may be modified in various forms.

On the other hand, it can be seen that the opening area A 'of FIG. 4B is smaller than the opening area A of FIG. 4A, which is a fringe field switching mode liquid crystal display device according to the first embodiment of the present invention of FIG. 4B. This is because the pixel array 121 and the drain electrode 119 are connected to each other through the connection electrode 130.

That is, the opening regions A and A 'of the pixel region P should be formed to be spaced apart from the switching region by a predetermined distance. The array substrate for a fringe field switching mode liquid crystal display device according to the first embodiment of the present invention may be connected to a connection electrode. The opening area A 'of the pixel area P is reduced by the area of 130.

Therefore, the aperture ratio of the fringe field switching mode liquid crystal display array substrate according to the first embodiment of the present invention is reduced compared to the general fringe field switching mode liquid crystal display array substrate.

- Second Embodiment -

5A through 5I are cross-sectional views illustrating manufacturing steps of an array substrate for a fringe field switching mode liquid crystal display device according to a second exemplary embodiment of the present invention.

In this case, for convenience of description, a portion in which the thin film transistor Tr in each pixel region P is to be formed will be defined as a switching region TrA.

First, as shown in FIG. 5A, a first metal material having low resistance on the transparent insulating substrate 201, for example, molybdenum (Mo), aluminum (Al), aluminum alloy (AlNd), and copper (Cu) The material selected from the copper alloy is deposited on the entire surface to form a first metal layer (not shown).

Then, application of a photoresist (not shown), exposure using a photo mask, development of the exposed photoresist (not shown), etching of the first metal layer (not shown), and stripping of the photoresist (not shown) A first mask process including a series of unit processes is performed to form a plurality of gate wirings (not shown) extending in the first direction by patterning a first metal layer (not shown), and simultaneously to the switching region TrA. A gate electrode 211 connected to the gate wiring (not shown) is formed.

In the gate pad part GPA, a gate wiring (not shown) extends to form the gate pad electrode 211a.

In this case, the first metal layer (not shown) may be formed by continuously depositing different metal materials into a double layer or more and patterning the same, thereby forming a gate wiring (not shown) and a gate electrode 211 having a double- or triple-layer structure. have.

Next, as shown in FIG. 5B, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is disposed on the gate wiring (not shown), the gate pad electrode 211a and the gate electrode 211. By depositing, a gate insulating film 213 is formed on the entire surface of the substrate 201.

Subsequently, pure amorphous silicon and impurity amorphous silicon are sequentially deposited on the gate insulating film 213 to form the pure amorphous silicon material layer 214a and the impurity amorphous silicon material layer 214b.

Subsequently, a second metal layer 216 is formed by depositing a material selected from among copper (Cu) and a copper alloy, which are metal materials having low resistance, on the impurity amorphous material layer 214b.

Here, copper (Cu) has a lower specific resistance than aluminum (Al) or molybdenum (Mo) to reduce the wiring resistance of the second metal layer 216.

Subsequently, as shown in FIG. 5C, application of a photoresist (not shown), exposure using a photo mask, development of the exposed photoresist (not shown), etching of the second metal layer (216 of FIG. 5B), and photoresist are performed. A second mask process including a series of unit processes such as strips (not shown) is performed, and the second metal layer (216 of FIG. 5B) is patterned to extend in the second direction to form a gate wiring (not shown). A plurality of data lines 217 defining pixel areas P are formed to cross each other.

In the data pad part GPA, the data wiring 217 extends to form the data pad electrode 217a. In this case, the data line 217 and the data pad electrode 217a have a single layer structure including a double layer semiconductor pattern made of pure and impurity amorphous silicon materials.

At the same time, source and drain electrodes 218 and 219 spaced apart from each other in the switching region TrA are formed, and the impurity amorphous material layer 214b of FIG. 5B is formed using the source and drain electrodes 218 and 219 as masks. By etching and removing, the ohmic contact layer 215b exposing the active layer 215a is formed.

Thus, the semiconductor layer 215 including the gate electrode 211, the gate insulating film 213, the active layer 215a of pure amorphous silicon, and the ohmic contact layer 215b of impurity amorphous silicon, a source spaced apart from each other, and The thin film transistor Tr including the drain electrodes 218 and 219 is formed.

In this case, the thin film transistor Tr may have a 'U' shape in a region forming a channel, and may be modified in various shapes.

Next, as shown in FIG. 5D, an inorganic insulating material, such as silicon oxide (SiO 2) or silicon nitride (SiNx), is selected on the front surface of the substrate 201 or an organic insulating material such as benzocyclobutene (BCB). ) Or a first protective layer 220a made of photo acryl.

Next, a photoresist (not shown) is applied on the first protective layer 220a to form a photoresist layer, and then a third mask process is performed, that is, an upper portion of the substrate 201 as shown in FIG. 5E. After exposing the exposure mask (M) consisting of a light transmission region and a blocking region on the light, the exposure mask (M) is exposed.

In this case, the transmission area TA of the exposure mask M corresponds to the pixel area P, and the other area corresponds to the blocking area BA of the exposure mask M. FIG.

By exposing and developing the photoresist layer, a photoresist pattern 221 having a predetermined thickness corresponding to the switching region TrA is formed, and the photoresist layer corresponding to other regions, that is, the pixel region P Is removed to expose the first passivation layer 220a.

Next, as shown in FIG. 5F, by removing the first protective layer 220a exposed to the outside of the photoresist pattern 221, a portion of the end of the drain electrode 219 and the gate insulating layer 213 of the pixel region P are removed. ) Will be exposed.

Next, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the entire surface of the photoresist pattern 221 to form the pixel electrode material layer 223a.

In this case, the pixel electrode material layer 223a disposed on the gate insulating layer 213 and the pixel electrode material layer 223a disposed on the photoresist pattern 221 are formed to have a breakage.

Next, as shown in FIG. 5G, a lift-off process including a strip process of exposing the substrate 201 on which the pixel electrode material layer (223a in FIG. 5F) formed with the strip is formed is exposed to the stripping liquid. The strip liquid penetrates into the portion where the breakdown of the pixel electrode material layer (223a in FIG. 5F) occurs, and the photoresist pattern (221 in FIG. 5F) and the pixel electrode material layer (223a in FIG. 5F) formed thereon are formed. Away from the substrate 201.

Therefore, a plate-shaped pixel electrode 223 electrically connected to a part of the end of the drain electrode 219 is formed in the pixel region P by the lift-off process.

Next, as shown in FIG. 5H, an inorganic insulating material such as silicon oxide (SiO 2) or silicon nitride (SiN x) is deposited on the entire surface of the substrate 201, or an organic insulating material such as benzo Cyclobutene (BCB) or photo acryl is applied to form the second protective layer 220b.

Thereafter, a fourth mask process is performed to form a gate pad contact hole 211b and a data pad contact hole 217b exposing the gate pad electrode 211a and the data pad electrode 217a.

Next, as shown in FIG. 5I, a transparent conductive material, for example, indium tin oxide (ITO), is formed on the second protective layer 220b having the gate pad contact hole 211b and the data pad contact hole 217b. Alternatively, the common electrode 225 is formed over the entire display area of the pixel areas P by depositing indium-zinc oxide (IZO) and patterning the fifth mask process.

In this case, the common electrode 225 is formed to have a plurality of bar openings OP that are spaced apart from each other by a predetermined distance corresponding to each pixel area P. The openings OP are formed in the pixel electrode 223. Correspondingly formed.

In the gate pad part GPA, a gate pad auxiliary electrode 211c is formed to contact the gate pad electrode 211 a through the gate pad contact hole 211 b. In the data pad part DPA, the data pad contact is provided. The data pad auxiliary electrode 217c is formed to contact the data pad electrode 217a through the hole 217b.

In this case, the gate pad auxiliary electrode 211c and the data pad auxiliary electrode 217c may be omitted.

Meanwhile, in the drawing, although the plurality of openings OP having a bar shape are formed in the common electrode 225, a plurality of openings OP formed in the common electrode 225 of each pixel region P are shown as another modification. The opening OP may be omitted to correspond to the common electrode 225 and may be formed with respect to the pixel electrode 223.

The array substrate for the fringe field switching mode liquid crystal display device manufactured as described above may be completed through a five mask process, and the fringe field may be formed through the pixel electrode 223 and the common electrode 225 made of a transparent conductive material. In addition, the viewing angle characteristics are excellent, and at the same time, the opening ratio and the transmittance are excellent.

In particular, the array substrate for the fringe field switching mode liquid crystal display device according to the second embodiment of the present invention has a higher aperture ratio than the array substrate for the fringe field switching mode liquid crystal display device according to the first embodiment of the present invention.

In other words, the array substrate for the fringe field switching mode liquid crystal display device according to the second embodiment of the present invention exhibits an aperture ratio characteristic of the pixel region P even though 5 mask processes are performed by shortening one mask process in a conventional 6 mask process. This has excellent characteristics.

FIG. 6 is a plan view schematically illustrating a part of one pixel area of an array substrate for a fringe field switched mode liquid crystal display device according to a second exemplary embodiment of the present invention.

In this case, for convenience of description, a region in which a plurality of pixel regions P is formed is defined as a display region and a portion in which the thin film transistor Tr, which is a switching element, is formed in each pixel region P is called a switching region TrA. .

As shown, a plurality of gate wirings 212 are formed extending in the first direction and extending in the second direction to define the plurality of pixel regions P by crossing the plurality of gate wirings 212. A plurality of data wirings 217 are formed.

Each pixel region P is connected to the gate wiring 212 and the data wiring 217, and has a gate electrode 211, a gate insulating film (not shown), an active layer (not shown) of pure amorphous silicon, and an impurity amorphous material. A semiconductor layer (not shown) including an ohmic contact layer (not shown) of silicon and a thin film transistor Tr including source and drain electrodes 218 and 219 spaced apart from each other are formed.

In addition, a plate-shaped pixel electrode 223 is formed in each pixel region P to contact the drain electrode 219 of the thin film transistor Tr, and a plurality of bar-shaped openings ( A common electrode 225 having OP) is formed.

In this case, although the thin film transistor Tr is shown as an example in which the region forming the channel forms a 'U' shape, it may be modified in various forms.

Meanwhile, it can be seen that the opening region A '' of the array substrate for the fringe field switching mode liquid crystal display according to the second embodiment of the present invention is larger than the opening region A 'of FIG. 4B. This is because the pixel electrode 223 and the drain electrode 219 do not have to be connected to each other through the connection electrode 130 (refer to FIG. 4).

Therefore, the array substrate for the fringe field switching mode liquid crystal display device according to the second embodiment of the present invention has excellent characteristics of the aperture ratio of the pixel region P even though the five mask process is performed by shortening one mask process.

The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

201: substrate, 211: gate electrode, 211a: gate pad electrode
213: gate insulating layer, 215: semiconductor layer (215a: active layer, 215b: ohmic contact layer)
217: data wiring, 217a: data pad electrode, 218: source electrode, 219: drain electrode
220a: first protective layer, 221: photoresist pattern, 223a: pixel electrode material layer
TrA: Switching area, Tr: Thin film transistor, P: Pixel area, GPA: Gate pad part
DPA: Data Pad

Claims (11)

Forming a gate wiring extending in one direction and a gate electrode connected thereto on a substrate on which a plurality of pixel regions are defined;
Forming a gate insulating film over the gate wiring and the gate electrode;
Forming source and drain electrodes spaced apart from each other on the gate insulating layer, the semiconductor layer including an active layer and an ohmic contact layer;
Forming a first protective layer on an entire surface of the substrate including the source and drain electrodes;
Forming a photoresist pattern on a portion of the first passivation layer except for the pixel region;
Removing the first protective layer exposed to the outside of the photoresist pattern, exposing a portion of ends of the gate insulating layer and the drain electrode corresponding to the pixel area;
Forming a metal layer on an entire surface of the substrate including the photoresist pattern and the gate insulating layer;
Removing the photoresist pattern to form a pixel electrode in contact with a portion of an end of the drain electrode corresponding to the pixel region;
Forming a second passivation layer on an entire surface of the substrate including the pixel electrode;
Forming a common electrode having a plurality of bar-shaped openings spaced apart from each other by a predetermined distance on the second passivation layer;
Method for manufacturing an array substrate for a fringe field switching mode liquid crystal display device comprising a.
The method of claim 1,
And the source and drain electrodes are made of copper (Cu) or copper alloy.
The method of claim 1,
In the step of forming the metal layer,
And the metal layer disposed on the photoresist pattern and the metal layer disposed on the gate insulating layer are disconnected.
The method of claim 1,
And removing the photoresist pattern through a lift-off process.
The method of claim 1,
And the metal layer and the common electrode are selected from indium tin oxide (ITO) or indium zinc oxide (IZO).
The method of claim 1,
Forming the gate wiring and the gate electrode connected thereto,
And forming a gate pad electrode at one end of the gate wiring line.
The method of claim 1,
Forming the data line,
And forming a data pad electrode at one end of the data line.
The method according to any one of claims 6 and 7,
And the second passivation layer comprises a gate pad contact hole exposing the gate pad electrode and a data pad contact hole exposing the data pad electrode.
The method of claim 8,
And a gate pad auxiliary electrode contacting the gate pad electrode through the gate pad contact hole is further formed.
The method of claim 8,
And a data pad auxiliary electrode contacting the data pad electrode through the data pad contact hole is further formed.
The method of claim 1,
Forming the semiconductor layer and the source and drain electrodes,
Source and drain electrodes spaced apart from each other on the data line and the impurity amorphous silicon layer by sequentially forming a gate insulating layer, a pure amorphous silicon layer, an impurity amorphous silicon layer, and a first metal layer on the gate wiring and the gate electrode. And forming an ohmic contact layer by removing the impurity amorphous silicon layer exposed between the source and drain electrodes while forming an ohmic contact layer.

Images