KR20110118999A - Fringe field switching mode liquid crystal display device and the method for fabricating the same - Google Patents

Abstract

PURPOSE: An array substrate for fringe field switching mode liquid crystal display device and manufacturing method thereof are provided to reduce the contact badness problem of agate pad. CONSTITUTION: A pixel electrode(121) is located on a substrate(101). A gate pad electrode(133) locates the end of agate line. A gate pad assistant pattern(200) is located in the lower part of the gate pad electrode. A data line(114) defines an image pixel area by crossing the gate line and the gate insulating layer.

Description

Fringe field switching mode liquid crystal display device and the method for fabricating the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a fringe field switching mode liquid crystal display device having a fringe field effect, and a manufacturing method thereof.

Liquid crystal display devices (LCDs), which are used for TVs and monitors due to their high contrast ratio and are advantageous for displaying moving images, are characterized by optical anisotropy and polarization of liquid crystals. The principle of image implementation by

Such a liquid crystal display is an essential component of a liquid crystal panel bonded through a liquid crystal layer between two side-by-side substrates, and realizes a difference in transmittance by changing an arrangement direction of liquid crystal molecules with an electric field in the liquid crystal panel. do.

Recently, an active matrix liquid crystal display device that drives liquid crystal with an electric field formed up-down has been widely used because of its excellent resolution and video performance. However, liquid crystal driving due to an electric field that is applied up-down has a disadvantage in that the viewing angle characteristics are inferior.

Accordingly, various methods have been proposed to overcome the disadvantage of narrow viewing angle, and among them, a liquid crystal driving method using a transverse electric field has attracted attention.

1 is a cross-sectional view of a general transverse electric field type liquid crystal display device.

As shown, the lower substrate 1, which is an array substrate, and the upper substrate 3, which is a color filter substrate, are spaced apart from each other and face each other. A liquid crystal layer 5 is interposed between the upper and lower substrates 1, 3, respectively. It is.

The pixel electrode 21 and the common electrode 25 are formed on the lower substrate 1 on the same plane, and the liquid crystal layer 3 has a horizontal electric field L formed by the pixel electrode 21 and the common electrode 25. Works by.

However, such a transverse field type liquid crystal display device has an advantage of improving the viewing angle, but has a disadvantage of low aperture ratio and low transmittance.

Therefore, in order to characterize the shortcomings of the transverse electric field type liquid crystal display, a fringe field switching mode LCD is characterized in that the liquid crystal is operated by a fringe field.

FIG. 2 is a cross-sectional view schematically illustrating an array substrate for a typical fringe field switching mode liquid crystal display device, and is a cross-sectional view of one pixel area P and a gate pad part GPA.

As shown in the drawing, on the array substrate 1 for a fringe field switching mode liquid crystal display device, a data wiring (not shown) defining a pixel region P by crossing a plurality of gate wirings (not shown) and gate wirings (not shown). ) Is configured.

In this case, a thin film transistor Tr is formed in the switching region TrA, which is an intersection point of the gate wiring (not shown) and the data wiring (not shown) of the pixel region P, and the pixel is formed in the display area where the image is substantially realized. The electrode 21 and the common electrode 25 are formed.

The thin film transistor Tr includes the semiconductor layer 15, the source and drain electrodes 17 and 19 including the gate electrode 11, the gate insulating layer 13, the active layer 15a and the ohmic contact layer 15b. Is done.

In addition, a plate-shaped pixel electrode 21 is formed in the pixel region P in contact with the drain electrode 19, and the gate insulating film 13 is formed on the entire surface of the substrate 1 including the pixel electrode 21. The protective layer 23 is formed.

In this case, the drain electrode 19 and the pixel electrode 21 are in contact with each other through the pixel electrode contact hole 27.

The common electrode 25 is formed over the passivation layer 23 in front of the display area including the pixel areas P. The common electrodes 25 are spaced apart from each other in correspondence with each pixel area P. bar OP is provided.

In addition, the gate pad part GPA includes a gate pad electrode 33 formed of the same material as the gate line (not shown) and the gate electrode 11 and connected to one end of the gate line (not shown). A gate pad auxiliary electrode 35 is formed on the electrode 33 to contact the gate pad electrode 33 through a gate pad contact hole 37 exposing a portion of the gate pad electrode 33.

On the other hand, the gate pad contact hole 37 exposing a part of the gate pad electrode 33 is formed over the gate insulating film 13 and the protective layer 23 to form a deep depth d1. When the depth d1 of 37 is deeply formed, an etch irregularity occurs in the process of forming the contact hole 37 or a constant aspect ratio of the gate pad auxiliary electrode 35 in the process of forming the gate pad auxiliary electrode 35. Since the aspect ratio cannot be obtained, a crack or breakage of the gate pad auxiliary electrode 35 occurs at a portion where the gate pad electrode 33 and the gate pad auxiliary electrode 35 are in contact with each other.

As a result, poor contact between the gate pad electrode 33 and the gate pad auxiliary electrode 35 is caused.

The present invention is to solve the above problems, the first object is to reduce the problem of poor contact of the gate pad portion.

Accordingly, a second object of the present invention is to provide an array substrate for a fringe field switching mode liquid crystal display device having improved display quality.

In order to achieve the object as described above, the present invention is a pixel electrode located on the substrate; A gate wiring extending in one direction on the substrate and a gate pad electrode positioned at one end of the gate wiring; A gate pad auxiliary pattern formed of the same material as the pixel electrode and positioned under the gate pad electrode; A data line crossing the gate line and the gate insulating layer interposed therebetween to define a pixel area; A thin film transistor positioned at an intersection point of the gate line and the data line and including a gate electrode, a semiconductor layer, a source electrode, and a drain electrode; A protective layer covering an entire surface of the substrate including the thin film transistor, the pixel electrode, and the gate pad electrode, and having a gate pad contact hole exposing a gate pad electrode together with a lower gate insulating layer; A common electrode having a plurality of openings on the protective layer corresponding to the pixel area; An array substrate for a fringe field switching mode liquid crystal display device is formed of the same material as the common electrode and includes a gate pad auxiliary electrode on the passivation layer and connected to the gate pad electrode through the gate pad contact hole. do.

In addition, the present invention includes a pixel electrode located on the substrate; A gate wiring extending in one direction on the substrate and a gate pad electrode positioned at one end of the gate wiring; A gate pad auxiliary pattern formed of the same material as the pixel electrode and positioned under the gate pad electrode; A gate insulating layer including a first gate pad contact hole exposing the gate pad electrode; A data line crossing the gate line and the gate insulating layer to define a pixel area; A thin film transistor positioned at an intersection point of the gate line and the data line and including a gate electrode, a semiconductor layer, a source electrode, and a drain electrode; A step compensation pattern formed of the same material as the data line, the source electrode, and the drain electrode, and disposed on the gate insulating layer and in contact with the gate pad electrode through the first gate pad contact hole; A protective layer on the thin film transistor, the pixel electrode, and the step compensation pattern, and including a second gate pad contact hole exposing the step compensation pattern; A common electrode having a plurality of openings on the protective layer corresponding to the pixel area; An array substrate of a fringe field switching mode liquid crystal display device formed of the same material as the common electrode and including a gate pad auxiliary electrode on the passivation layer and in contact with the step compensation pattern through the second gate pad contact hole. To provide.

The gate pad auxiliary pattern may protrude to the side of the gate pad electrode, and the gate insulating layer and the protective layer may expose the first and second gate pad auxiliary contact holes to expose the protruding side surfaces of the gate pad auxiliary pattern. Include.

The first and second gate pad auxiliary contact holes may include first and second gate pad connection electrodes connecting the gate pad auxiliary pattern and the gate pad auxiliary electrode, respectively. The double layer structure includes the same material layer as the pixel electrode.

In addition, the present invention comprises the steps of forming a pixel electrode and a gate pad auxiliary pattern on the substrate; Forming a gate wiring, a gate electrode, and a gate pad electrode on the substrate, the material including the pixel electrode; Forming a gate insulating layer over the pixel electrode, the gate wiring, the gate electrode, and the gate pad electrode; Forming a pixel electrode contact hole and a first gate pad contact hole on the gate insulating layer to form an active layer and an impurity amorphous silicon layer and simultaneously expose a portion of the pixel electrode and a portion of the gate pad electrode; An ohmic contact spaced apart from each other by removing the impurity amorphous silicon layer exposed between the source and drain electrodes while forming a source and a drain electrode over the impurity amorphous silicon layer and the data line defining the pixel area crossing the gate wiring. Forming a layer; Forming a protective layer on an entire surface of the substrate including the source and drain electrodes; Forming a second gate pad contact hole in the protective layer, the second gate pad contact hole overlapping the first gate pad contact hole; A gate pad is formed on the passivation layer to have a plurality of bar-shaped openings spaced at predetermined intervals corresponding to the pixel area, and is connected to the gate pad electrode through the second gate pad contact hole. A manufacturing method for an array substrate for a fringe field switched mode liquid crystal display device comprising forming an auxiliary electrode is provided.

In this case, the forming of the gate pad auxiliary pattern and the forming of the gate pad electrode are performed through one half-tone mask process, forming the active layer and the impurity amorphous silicon layer, and the pixel electrode. The forming of the contact hole and the first gate pad contact hole is performed through one halftone mask process.

The first and second gate pad contact holes are formed at the same time. In the forming of the data wiring, the first gate pad contact hole is in contact with the gate pad electrode through the first gate pad contact hole and is made of the same material as the data wiring. A step compensation pattern is formed.

In the forming of the second gate pad contact hole, first and second gate pad auxiliary contact holes may be formed on both sides of the first and second gate pad contact holes. In the forming of the common electrode, the first and second gate pad auxiliary contact holes are formed of the same material as the common electrode, and the gate pad auxiliary pattern and the gate pad auxiliary electrode are connected to each other. The first and second gate pad connection electrodes are further formed.

1 is a cross-sectional view of a general transverse electric field type liquid crystal display device.
2 is a schematic cross-sectional view of an array substrate for a typical fringe field switching mode liquid crystal display device;
3 is a plan view of an array substrate for a fringe field switching mode liquid crystal display device according to a first embodiment of the present invention.
4 is a cross-sectional view taken along the cut lines IV-IV and IV′-IV ′ of FIG. 3.
FIG. 5 is a schematic cross-sectional view of a portion of an array substrate for a fringe field switched mode liquid crystal display device according to a second embodiment of the present invention; FIG.
6 is a schematic cross-sectional view of yet another embodiment according to a second embodiment of the present invention;
7A to 7M are cross-sectional views illustrating manufacturing steps of an array substrate for a fringe field switching mode liquid crystal display device according to a second exemplary embodiment of the present invention of FIG. 6.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the drawings.

- First Embodiment -

3 is a plan view of an array substrate for a fringe field switching mode liquid crystal display device according to a first embodiment of the present invention.

As shown, the gate wiring 112 extends in a first direction on the fringe field switching mode liquid crystal display array substrate 100 according to the first embodiment of the present invention, and the gate in the second direction. The data wiring 114 defining the pixel region P is formed to cross the wiring 112.

Further, at the intersection of the gate wiring 112 and the data wiring 114 of the pixel region P, the gate electrode 111 and the gate insulating film (not shown), an active layer (not shown) of pure amorphous silicon, and an impurity amorphous A semiconductor layer 115 including an ohmic contact layer (not shown) of silicon and a thin film transistor Tr including source and drain electrodes 117 and 119 spaced apart from each other are formed.

In this case, the source electrode 117 is branched from the data line 114, and the gate electrode 111 is formed to branch from the gate line 112.

On the other hand, although the thin film transistor Tr is formed in the pixel region P by forming the gate electrode 111 in a form branched from the gate wiring 112, the aperture ratio of the pixel region P is modified. For improvement, the gate wiring 112 may be formed on the gate wiring 112 using the gate electrode itself as a gate electrode.

In addition, a pixel electrode 121 having a plate shape is formed in direct contact with the drain electrode 119 of the thin film transistor Tr in the pixel area P, and includes a display area including a plurality of pixel areas P. The common electrode 125 is formed on the front surface of the pixel region P to correspond to each pixel area P.

The common electrode 125 has a plurality of bar-shaped openings OP corresponding to the plate-shaped pixel electrode 121.

In addition, gate and data pad parts GPA and DPA connected to an external circuit are defined at ends of the gate and data lines 112 and 114, and a data pad electrode 151 is formed in the data pad part DPA. The data pad auxiliary electrode 155 made of the same material as the common electrode 125 is formed through the data pad contact hole 153.

In this case, a gate pad electrode 133 is formed in the gate pad part GPA, and a gate pad auxiliary electrode 135 made of the same material as the common electrode 125 is formed through the gate pad contact hole 137. do.

In this case, the array substrate 100 for a fringe field switching mode liquid crystal display device of the present invention further forms a gate pad auxiliary pattern 200 made of the same material as the pixel electrode 121 under the gate pad electrode 133. The gate pad auxiliary pattern 200 and the gate pad auxiliary electrode 135 are electrically connected to each other through the first and second gate pad connection electrodes 220a and 220b.

Therefore, even if a crack or break occurs in the contact portion between the gate pad electrode 133 and the gate pad auxiliary electrode 135, the gate pad auxiliary electrode 135 is formed of the first and second gate pad connection electrodes 220a, As the gate pad auxiliary pattern 200 is connected to the gate pad auxiliary pattern 200 through 220b, contact failure between the gate pad electrode 133 and the gate pad auxiliary electrode 135 may be prevented from occurring.

This can improve the reliability of the pad portion. Let's take a closer look at this.

FIG. 4 is a cross-sectional view of a portion cut along lines IV-IV and IV′-IV ′ of FIG. 3.

In this case, for convenience of description, a portion where the thin film transistor Tr, which is a switching element, is formed in the pixel region P is referred to as a switching region TrA and a portion where the gate pad electrode 133 is formed as a gate pad portion GPA. I'll define it.

As illustrated, the array substrate 101 for a fringe field switching mode liquid crystal display device according to the first embodiment of the present invention includes a gate wiring (not shown) extending in a first direction on the transparent insulating substrate 101. The gate electrode 111 to be connected is located in the switching region TrA.

In addition, a plate-shaped pixel electrode 121 is formed in the pixel region P where the image is substantially implemented.

In this case, the gate wiring (not shown) and the gate electrode 111 is composed of a double layer of a lower layer (110a) made of a transparent conductive material and an upper layer (110b) made of a metal material having low resistance properties, wherein the transparent conductive material is Metal materials selected from indium tin oxide (ITO) or indium zinc oxide (IZO) and having low resistance properties include molybdenum (Mo), aluminum (Al), aluminum alloy (AlNd), and copper (Cu). , Copper alloy is one selected.

The pixel electrode 121 is made of the same material as the lower layer 110a of the gate electrode 111, that is, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

In the gate pad part GPA, the gate pad auxiliary pattern 200 is formed of the same material as the pixel electrode 121, and a gate wiring (not shown) and a gate electrode are formed on the gate pad auxiliary pattern 200. A gate pad electrode 133 connected to one end of the gate wiring (not shown) is formed of the same material as the material of the upper layer 110b of the 111.

Accordingly, the gate pad electrode 133 is positioned as high as the gate pad auxiliary pattern 200 from the substrate 101.

Here, the gate pad auxiliary pattern 200 may be formed at the same time as the mask process for forming the pixel electrode 121, so that it is not necessary to perform an additional mask process.

In addition, the gate pad subsidiary pattern 200 is formed to have a larger area than the gate pad electrode 133. Accordingly, the gate pad subsidiary pattern 200 protrudes laterally than the gate pad electrode 133. It has a shape.

In addition, a gate insulating film made of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) on the entire surface of the substrate 101 on the gate electrode 111, the pixel electrode 121, and the gate pad electrode 133. 113) is formed.

In this case, the gate insulating layer 113 is etched and includes a pixel electrode contact hole 127 exposing a portion of the pixel electrode 121 positioned below.

In addition, a semiconductor layer including an active layer 115a of pure amorphous silicon and an ohmic contact layer 115b of impurity amorphous silicon in the switching region TrA on the gate insulating layer 113 to correspond to the gate electrode 111 ( 115 is formed, and source and drain electrodes 117 and 119 spaced apart from each other are formed on the semiconductor layer 115.

At this time, the active layer 115a is exposed between the source and drain electrodes 117 and 119 spaced apart from each other, and the gate electrode 111, the gate insulating layer 113, and the semiconductor layer (sequentially stacked in the switching region TrA) are exposed. 115 and the source and drain electrodes 117 and 119 form a thin film transistor Tr.

The drain electrode 119 and the pixel electrode 121 are electrically connected to each other through the pixel electrode contact hole 127 formed in the gate insulating layer 113.

In addition, a data line 114 defining the pixel area P is formed to extend in the second direction to intersect with the gate line (not shown). In this case, the source electrode 117 of the thin film transistor Tr is connected to the data line 114.

In addition, an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), or an organic insulating material may be disposed on the thin film transistor Tr, the data wiring 114, and the gate insulating film 113. For example, a protective layer 123 made of one selected from benzocyclobutene (BCB) or photo acryl is formed on the entire surface of the substrate 101.

The gate pad contact hole 137 is formed in the gate pad part GPA to expose the gate pad electrode 133 by etching the protective layer 123 and the gate insulating layer 113 disposed below the protective layer 123.

At this time, when the protective layer 123 is formed of an organic insulating material, the protective layer 123 is formed on the entire surface of the substrate 101, wherein the gate pad electrode 133 is formed on the gate pad auxiliary pattern 200. As a result, the position of the gate pad contact hole 137 may be reduced as compared with the conventional position since the position of the gate pad contact hole 137 is higher than that of the substrate 101.

Therefore, as the depth d1 of the conventional gate pad contact hole (37 of FIG. 2) is deeply formed, etch unevenness may be prevented, and the gate pad electrode 133 may be prevented through the gate pad contact hole 137. In the process of forming the gate pad sub-electrode 135 in contact with the substrate, a constant aspect ratio of the gate pad sub-electrode 135 may be obtained, resulting in poor contact between the gate pad electrode 133 and the gate pad sub-electrode 135. Can be prevented.

In addition, the protective layer 123 and the gate insulating layer 113 may be disposed under the gate pad electrode 133 and expose first and second gate pad auxiliary patterns 200 protruding to the side surface of the gate pad electrode 133. Two gate pad auxiliary contact holes 230a and 230b are further provided.

In addition, a transparent conductive material, for example, indium tin oxide (ITO) or indium, may be disposed on the protective layer 123 including the gate pad contact hole 137 and the first and second gate pad auxiliary contact holes 230a and 230b. As a zinc oxide (IZO), a plate-shaped common electrode 125 is formed on the entire surface of the display area formed of the pixel areas P.

In this case, in the common electrode 125, a plurality of bar-shaped openings OP are formed in parallel with the data line 114 with respect to each pixel electrode 121 formed in each pixel region P. FIG. In the drawing, three openings OP having a bar shape in the common electrode 125 are spaced apart from each other at equal intervals in each pixel region P. However, in order to form an efficient fringe field, The opening OP corresponding to the pixel area P may be formed in an appropriate number within a range of about 2 to about 10.

In this case, in the gate pad part GPA, the gate pad auxiliary electrode 135 is formed on the protective layer 123 to be in contact with the gate pad electrode 133 through the gate pad contact hole 137.

The gate pad auxiliary electrode 135 is made of the same material forming the common electrode 125.

In this case, the gate pad auxiliary electrode 135 is also formed in the first and second gate pad auxiliary contact holes 230a and 230b exposing the gate pad auxiliary pattern 200, thereby providing the gate pad auxiliary electrode 135 and the gate pad auxiliary electrode. First and second gate pad connection electrodes 220a and 220b connecting the pattern 200 are formed.

Thus, the gate pad auxiliary pattern 200 is formed, and the gate pad auxiliary pattern 200 and the gate pad auxiliary electrode 135 are electrically connected to each other through the first and second gate pad connection electrodes 220a and 220b. As a result, even if a crack or a break occurs in the gate pad auxiliary electrode 135 in the process of forming the gate pad contact hole 137, a poor contact between the gate pad electrode 133 and the gate pad auxiliary electrode 135 is prevented from occurring. can do.

In more detail, the gate pad contact hole 137 exposing the gate pad electrode 133 is formed to have a deep depth d1 across the gate insulating layer 113 and the protective layer 123.

In this case, a constant aspect ratio of the gate pad auxiliary electrode 135 may not be obtained in the process of forming the gate pad auxiliary electrode 135 in contact with the gate pad electrode 133. Cracks or breaks in the gate pad subsidiary electrodes 35 occur at portions where the pad subsidiary electrodes 135 contact each other.

However, according to the present invention, after the gate pad auxiliary pattern 200 is further formed on the lower portion of the gate pad electrode 133 with the same material as the pixel electrode 121, the gate pad auxiliary pattern 200 is formed on the gate pad auxiliary electrode 135. The gate pad electrode 133 and the gate pad auxiliary electrode 135 are directly connected to each other by being directly contacted with each other, and the gate pad auxiliary pattern 200 and the first and second gate pad connection electrodes 220a are connected to each other. 220b) is again connected secondarily.

As a result, even if a crack or breakage occurs in the contact region where the gate pad electrode 133 and the gate pad auxiliary electrode 135 contact each other, the gate pad electrode 133 and the gate pad subsidiary 135 The electrodes 135 may still be electrically connected to each other through secondary contact through the gate pad auxiliary pattern 200 and the first and second gate pad connection electrodes 220a and 220b.

The array substrate 101 for a fringe field switching mode liquid crystal display according to the present invention having the above-described structure further includes a gate pad auxiliary pattern 200 made of the same material as the pixel electrode 121 under the gate pad electrode 133. And the gate pad electrode 133 and the gate pad auxiliary electrode 135 are in contact with each other for two times, such that a poor contact between the gate pad electrode 133 and the gate pad auxiliary electrode 135 occurs. It is characterized by not occurring.

- Second Embodiment -

5 is a schematic cross-sectional view of a portion of an array substrate for a fringe field switching mode liquid crystal display device according to a second embodiment of the present invention.

In this case, for convenience of description, a portion where the thin film transistor Tr, which is a switching element, is formed in the pixel region P is referred to as a switching region TrA and a portion where the gate pad electrode 133 is formed as a gate pad portion GPA. I'll define it.

As illustrated, the array substrate 101 for a fringe field switching mode liquid crystal display device according to the second embodiment of the present invention may include a gate wiring (not shown) extending in a first direction on the transparent insulating substrate 101. The gate electrode 111 is formed in the switching region TrA connected thereto.

In addition, a plate-shaped pixel electrode 121 is formed in the pixel region P where the image is substantially implemented.

In this case, the gate wiring (not shown) and the gate electrode 111 is composed of a double layer of a lower layer (110a) made of a transparent conductive material and an upper layer (110a) made of a metal material having low resistance characteristics, wherein the transparent conductive material is Metal materials selected from indium tin oxide (ITO) or indium zinc oxide (IZO) and having low resistance properties include molybdenum (Mo), aluminum (Al), aluminum alloy (AlNd), and copper (Cu). , Copper alloy is one selected.

The pixel electrode 121 is made of the same material as the lower layer 110a of the gate electrode 111, that is, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

In the gate pad part GPA, the gate pad auxiliary pattern 200 is formed of the same material as the pixel electrode 121, and a gate wiring (not shown) and a gate electrode are formed on the gate pad auxiliary pattern 200. A gate pad electrode 133 connected to one end of a gate wiring (not shown) is formed of the same material as the material of the upper layer 110a of the 111.

Accordingly, the gate pad electrode 133 is positioned as high as the gate pad auxiliary pattern 200 from the substrate 101.

Here, the gate pad auxiliary pattern 200 may be formed at the same time as the mask process for forming the pixel electrode 121, so that it is not necessary to perform an additional mask process.

In addition, the gate pad subsidiary pattern 200 is formed to have a larger area than the gate pad electrode 133. Accordingly, the gate pad subsidiary pattern 200 protrudes laterally than the gate pad electrode 133. It has a shape.

In addition, a gate insulating film made of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) on the entire surface of the substrate 101 on the gate electrode 111, the pixel electrode 121, and the gate pad electrode 133. 113) is formed.

In this case, the gate insulating layer 113 includes a pixel electrode contact hole 127 exposing a portion of the pixel electrode 121 disposed below, and the gate insulating layer 113 is a gate insulating layer in the gate pad part GPA. A first gate pad contact hole 137a exposing a portion of the gate pad electrode 133 disposed below the 113 is included.

In addition, an active layer of pure amorphous silicon corresponding to the gate electrode 111 in the switching region TrA over the gate insulating layer 113 including the pixel electrode contact hole 127 and the first gate pad contact hole 137a. The semiconductor layer 115 including the 115a and the ohmic contact layer 115b of impurity amorphous silicon is formed, and source and drain electrodes 117 and 119 spaced apart from each other are formed on the semiconductor layer 115.

At this time, the active layer 115a is exposed between the source and drain electrodes 117 and 119 spaced apart from each other, and the gate electrode 111, the gate insulating layer 113, and the semiconductor layer (sequentially stacked in the switching region TrA) are exposed. 115 and the source and drain electrodes 117 and 119 form a thin film transistor Tr.

The drain electrode 119 and the pixel electrode 121 are electrically connected to each other through the pixel electrode contact hole 127 formed in the gate insulating layer 113.

In addition, a data line 114 defining the pixel area P is formed to extend in the second direction to intersect with the gate line (not shown). In this case, the source electrode 117 of the thin film transistor Tr is connected to the data line 114.

In addition, the step compensation pattern 210 which is in contact with the gate pad electrode 133 through the first gate pad contact hole 137a formed in the gate insulating layer 113 in the gate pad part GPA may be connected to the data line 114. It is made of the same material as the source and drain electrodes 117 and 119 and is formed on the same layer.

Here, the step compensation pattern 210 may be formed at the same time as the mask process for forming the data line 114 and the source and drain electrodes 117 and 119 may be performed without additional mask process.

In addition, an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), or an organic insulating material may be disposed on the thin film transistor Tr, the data wiring 114, and the step compensation pattern 210. For example, a protective layer 123 made of one selected from benzocyclobutene (BCB) or photo acryl is formed on the entire surface of the substrate 101.

In the gate pad part GPA, the passivation layer 123 includes a second gate pad contact hole 137b exposing the step compensation pattern 210.

At this time, the depth of the second gate pad contact hole 137b is formed very shallowly by the step compensation pattern 210.

Thus, as the conventional gate pad contact hole (37 in FIG. 2) has a deep depth d1 formed deeply across the gate insulating film (13 in FIG. 2) and the protective layer (23 in FIG. 2), an etching irregularity occurs. In the process of forming the gate pad subsidiary electrode 135, it is possible to obtain a constant aspect ratio of the gate pad subsidiary electrode 135, so that the crack or disconnection of the gate pad subsidiary electrode 135 occurs. You can prevent it.

The pixel regions P may be formed of a transparent conductive material, for example, indium tin oxide (ITO) or indium zinc oxide (IZO), on the passivation layer 123 including the second gate pad contact hole 137b. The plate-shaped common electrode 125 is formed on the entire display area.

In this case, in the common electrode 125, a plurality of bar-shaped openings OP are formed in parallel with the data line 114 with respect to each pixel electrode 121 formed in each pixel region P. FIG. In the drawing, three openings OP having a bar shape in the common electrode 125 are spaced apart from each other at equal intervals in each pixel region P. However, in order to form an efficient fringe field, The opening OP corresponding to the pixel area P may be formed in an appropriate number within a range of about 2 to about 10.

In this case, in the gate pad part GPA, the gate pad auxiliary electrode 135 is formed to contact the step compensation pattern 210 through the second gate pad contact hole 137b on the passivation layer 123.

The gate pad auxiliary electrode 135 is made of the same material forming the common electrode 125.

In this way, the gate pad auxiliary pattern 200 is formed, and the first and second gate pad contact holes 137a and 137b for connecting the gate pad electrode 133 and the gate pad auxiliary electrode 135 to each other are formed in the gate insulating film ( 113 and the protective layer 123, respectively, so that the contact hole (37 in FIG. 2) is formed deeper over the gate insulating film (13 in FIG. 2) and the protective layer (23 in FIG. 2). Etch non-uniformity can be prevented from occurring during the formation of the first and second gate pad contact holes 137a and 137b.

In addition, in the process of forming the gate pad auxiliary electrode 135, since a constant aspect ratio of the gate pad auxiliary electrode 135 is obtained, a poor contact between the gate pad electrode 133 and the gate pad auxiliary electrode 135 occurs. Can be prevented.

6, the gate pad auxiliary pattern 200 protruding to the side of the gate pad electrode 133 and positioned below the gate pad electrode 133 in the protective layer 123 and the gate insulating layer 113. First and second gate pad auxiliary contact holes 230a and 230b exposing the first and second gate pad auxiliary contact holes 230a and 230b, respectively, to expose the first and second gate pad auxiliary contact holes 230a and 230b. , 220b).

Accordingly, the gate pad electrode 133 and the gate pad auxiliary electrode 135 are primarily connected to each other through the step compensation pattern 210, and the gate pad auxiliary pattern 200 and the first and second gate pad connection electrodes ( 220a, 220b will be connected again and again.

As a result, cracks or breakage of the gate pad auxiliary electrode 135 may occur at a portion where the gate pad electrode 133 and the step compensation pattern 210 or the step compensation pattern 210 and the gate pad auxiliary electrode 135 are in contact with each other. However, the gate pad electrode 133 and the gate pad auxiliary electrode 135 are still mutually contacted through the secondary contact through the gate pad auxiliary pattern 200 and the first and second gate pad connection electrodes 220a and 220b. Can be electrically connected

Hereinafter, a method of manufacturing an array substrate for a fringe field switching mode liquid crystal display device according to a second embodiment of the present invention having the above-described structural features will be described with reference to the accompanying drawings.

7A to 7M are cross-sectional views illustrating manufacturing steps of an array substrate for a fringe field switched mode liquid crystal display device according to a second exemplary embodiment of the present invention of FIG. 5.

In this case, for convenience of description, an area in which the thin film transistor Tr is formed in each pixel area is defined as a switching area TrA.

First, as shown in FIG. 7A, the first metal material 200a, which is a transparent conductive material, and the second metal material 111a, which has low resistance, are sequentially formed on the transparent insulating substrate 101.

In this case, the transparent conductive material is one selected from indium tin oxide (ITO) or indium zinc oxide (IZO), and the metal material having low resistance properties includes molybdenum (Mo), aluminum (Al), and aluminum alloy (AlNd). ), Copper (Cu) and copper alloy.

Subsequently, as shown in FIG. 7B, after forming photoresist layers (not shown) on the first and second metal layers 200a and 111a, the light transmitting region TmA is blocked on the substrate 101. After placing the exposure mask 300 composed of the transmissive region HTmA having a transmittance between the region BkA and the transmittance of the transmission region TmA and the transmittance of the blocking region BkA, the exposure mask 300 passes through the exposure mask 300. Exposure is performed.

In this case, the blocking region BkA of the exposure mask 300 includes the region where the gate electrode 111 of FIG. 5 is to be formed and the gate pad electrode 133 of FIG. 5 of the gate pad part GPA. The transflective area HTmA corresponds to the region to be formed, and the region in which the pixel electrode 121 of FIG. 5 is to be formed and the gate pad electrode 133 of FIG. 5 of the gate pad part GPA are formed. Corresponds to both sides of the region to be formed.

The transmission region TmA corresponds to the other regions.

The first photoresist having a first thickness corresponding to a region where the gate electrode 111 of FIG. 5 is to be formed is formed by performing halftone exposure or diffraction exposure and developing the photoresist layer (not shown). A pattern 240a is formed, and a second photoresist pattern 240b having a second thickness that is thinner than the first thickness is formed in the region where the pixel electrode 121 of FIG. 5 is to be formed.

In the gate pad part GPA, the gate pad electrode GPA has a first thickness corresponding to the region where the gate pad electrode 133 of FIG. 5 is to be formed, and is formed on both sides of the region where the gate pad electrode 133 of FIG. 5 is to be formed. A third photoresist pattern 240c having a second thickness thinner than one thickness is formed.

In the remaining areas, the photoresist layer is removed to expose the second metal layer 111a.

Next, as shown in FIG. 7C, the second metal layer 111a exposed to the outside of the first to third photoresist patterns 240a and 240b and 240c of FIG. 7B is etched.

Subsequently, ashing is performed to remove the second photoresist pattern 240b of FIG. 7B having a second thickness, thereby forming a second electrode in the region where the pixel electrode 121 of FIG. 5 is to be formed. The first metal layer except for the region where the gate electrode 111 of FIG. 5 is to be formed and the region where the gate pad electrode 133 of FIG. 5 is to be formed. Expose 200a.

Next, as shown in FIG. 7D, the gate and the second metal layer (111a in FIG. 7C) of the region where the exposed first metal layer 200a and the pixel electrode (121 in FIG. 5) of the pixel region P are to be formed are formed. By etching the second metal layer 111a exposed to both sides of the third photoresist pattern 240c of the pad part GPA, the pixel electrode 121 of the pixel region P is formed.

Subsequently, the substrate 101 is exposed to a region other than a region where the pixel electrode 121 is formed and a region covered with the first and third photoresist patterns 240a and 240c.

Next, as shown in FIG. 7E, by ashing or stripping the substrate 101, the first and third photoresist patterns 240a and 240c of FIG. 7D are removed to remove the gate of the switching region TrA. The gate pad auxiliary pattern 200 and the gate pad electrode 133 of the electrode 111, the gate pad part GPA are formed.

In this case, the gate electrode 111 has a double layer structure consisting of a lower layer 110a made of the first metal layer 200a and an upper layer 110b made of the second metal layer 111a.

Next, as shown in FIG. 7F, an inorganic insulating material such as silicon oxide (SiO ₂ ) is formed on the entire surface of the substrate 101 on which the gate electrode 111, the pixel electrode 121, and the gate pad electrode 133 are formed. Alternatively, silicon nitride (SiNx) is deposited to form a gate insulating film 113 on the entire surface of the substrate 101.

Thereafter, the pure amorphous silicon layer 215a and the impurity amorphous silicon layer 215b are sequentially formed on the gate insulating layer 113.

After forming a photoresist layer (not shown) on the impurity amorphous silicon layer 215b, as shown in FIG. After exposing the exposure mask 310 composed of the transflective area HTmA having a transmittance between the transmittance of the area TmA and the transmittance of the blocking area BkA, exposure through the exposure mask 310 is performed.

In this case, the blocking region BkA of the exposure mask 310 corresponds to the gate electrode 111 of the switching region TrA, and the transmission region TmA corresponds to a portion of the pixel electrode 121 of the pixel region P. The area corresponds to the center portion of the gate pad electrode 133 of the gate pad part GPA. The transflective area HTmA corresponds to the other areas.

The photoresist layer (not shown) is subjected to halftone exposure or diffraction exposure and developed to form a first photoresist pattern 240a having a first thickness corresponding to the switching region TrA, thereby forming a pixel region P. A second photoresist pattern 240b having a second thickness that is thinner than the first thickness is formed in a region except for the partial region of the pixel electrode 121 of the pixel electrode 121 and the center portion of the gate pad electrode 133 of the gate pad portion GPA. .

At this time, the photoresist layer is removed in the partial region of the pixel electrode 121 of the pixel region P and the central portion of the gate pad electrode 133 of the gate pad portion GPA to expose the impurity amorphous silicon layer 215b. .

Next, as shown in FIG. 7H, the impurity amorphous silicon 215b exposed to the outside of the first and second photoresist patterns 240a and 240b of FIG. 7G, the pure amorphous silicon layer 215a and the gate insulating film underneath. By etching 113, the pixel electrode contact hole 127 exposing a part of the pixel electrode 121 in the pixel region P and the center portion of the gate pad electrode 133 in the gate pad part GPA are exposed. A first gate pad contact hole 137a is formed.

Thereafter, ashing is performed to remove the second photoresist pattern 240b of FIG. 7G to expose the impurity amorphous silicon layer 215b in a region other than the switching region TrA.

Next, as shown in 7i, the exposed impurity amorphous silicon layer (215b in FIG. 7H) and the pure amorphous silicon layer (215a in FIG. 7H) below it are still covered with the first photoresist pattern 240a. The gate insulating layer 113 in which the pixel electrode contact hole 127 and the first gate pad contact hole 137a are formed is exposed to regions other than the regions in which the regions are located.

At this time, the active layer 115a and the impurity ohmic contact pattern 216 are formed in the switching region TrA.

Next, as shown in 7j, the first photoresist pattern 240a of FIG. 7I is removed by ashing or stripping the substrate, and then a third metal material example is formed on the gate insulating layer 113. For example, a material selected from aluminum (Al), aluminum alloy (AlNd), copper (Cu), and copper alloy is deposited on the entire surface to form a third metal layer 218.

Then, a series of application of a photoresist (not shown), exposure using a photo mask, development of the exposed photoresist (not shown), etching of the third metal layer 218 and stripping of the photoresist (not shown), etc. By performing a mask process including a unit process of FIG. 7K, by patterning the third metal layer (218 of FIG. 7J) as shown in FIG. 7K, the pixel region extends in the second direction and intersects with the gate wiring (not shown). The data wiring 114 defining P) is formed.

At the same time, the source and drain electrodes 117 and 119 spaced apart from each other are formed by etching and removing the center portion of the third metal layer 218 and the ohmic contact pattern (216 of FIG. 7J) in the switching region TrA. An ohmic contact layer 115b is formed below the source and drain electrodes 117 and 119 to expose the active layer 115a.

The semiconductor layer 115 including the gate electrode 111, the gate insulating layer 113, the active layer 115a and the ohmic contact layer 115b sequentially stacked in the switching region TrA, and the source and drain electrodes 117 spaced apart from each other. , 119 forms a thin film transistor (Tr).

In this case, the drain electrode 119 is in contact with the pixel electrode 121 through the pixel electrode contact hole 127.

In the gate pad part GPA, a shortwave compensation pattern 210 is formed to contact the gate pad electrode 133 through the first gate pad contact hole 137a.

The step compensation pattern 210 is made of the same material as the data line 114 and is formed on the same layer.

Next, as shown in FIG. 7L, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride is formed on the entire surface of the substrate 101 on which the source and drain electrodes 117 and 119 and the step compensation pattern 210 are formed. (SiNx) is deposited or an organic insulating material such as benzocyclobutene (BCB) or photo acryl is applied to form the protective layer 123.

Afterwards, a photoresist pattern (not shown) is formed over the protective layer 123 in all regions except for portions corresponding to the step compensation pattern 210 and both sides of the step compensation pattern 210, and a photoresist pattern (not shown). The second gate pad contact hole exposing the step compensation pattern 210 in the gate pad part GPA by patterning the protective layer 123 exposed to the outside of the photoresist pattern (not shown). 137b) and first and second gate pad auxiliary contact holes 230a and 230b.

Next, as shown in FIG. 7M, a transparent conductive material, for example, indium, is disposed on the protective layer 123 having the second gate pad contact hole 137b and the first and second gate pad auxiliary contact holes 230a and 230b. Tin-oxide (ITO) or indium-zinc-oxide (IZO) is deposited and patterned by a mask process to form a plate-shaped common electrode 125 on the entire display area (not shown).

At the same time, the gate pad portion GPA contacts the top surface of the step compensation pattern 210 through the second gate pad contact hole 143b and the first and second gate pad auxiliary contact holes 230a and 230b. The pad auxiliary electrode 135 is formed.

In this case, the common electrode 125 formed on the entire surface of the display area (not shown) is formed to have a plurality of bar-shaped openings OP corresponding to the pixel electrode 121 in each pixel area P during its patterning. Is characteristic.

Meanwhile, in the drawing, although the plurality of openings OP having a bar shape are formed in the common electrode 125, as a further modification, the plurality of openings OP formed in the common electrode 125 of each pixel region P are shown. The opening OP may be omitted to correspond to the common electrode 125 and may be formed with respect to the pixel electrode 121.

The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

101: substrate, 111: gate electrode, 112: gate wiring, 113: gate insulating film
114: data wiring, 115: semiconductor layer (115a: active layer, 115b: ohmic contact layer)
117, 119: source and drain electrodes, 121: pixel electrodes, 123: protective layer
125: common electrode, 133: gate pad electrode, 135: gate pad auxiliary electrode
137a and 137b: first and second gate pad contact holes
200: gate pad auxiliary pattern, 210: step compensation pattern
220a and 220b: first and second gate pad connection electrodes
230a, 230b: first and second gate pad auxiliary contact holes
Tr: thin film transistor, OP: opening, TrA: switching area
GPA: Gate pad part, P: Pixel area

Claims (13)

A pixel electrode positioned on the substrate;
A gate wiring extending in one direction on the substrate and a gate pad electrode positioned at one end of the gate wiring;
A gate pad auxiliary pattern formed of the same material as the pixel electrode and positioned under the gate pad electrode;
A data line crossing the gate line and the gate insulating layer interposed therebetween to define a pixel area;
A thin film transistor positioned at an intersection point of the gate line and the data line and including a gate electrode, a semiconductor layer, a source electrode, and a drain electrode;
A protective layer covering an entire surface of the substrate including the thin film transistor, the pixel electrode, and the gate pad electrode, and having a gate pad contact hole exposing a gate pad electrode together with a lower gate insulating layer;
A common electrode having a plurality of openings on the protective layer corresponding to the pixel area;
A gate pad auxiliary electrode made of the same material as the common electrode and connected to the gate pad electrode through the gate pad contact hole.
An array substrate for a fringe field switching mode liquid crystal display device comprising a.
A pixel electrode positioned on the substrate;
A gate wiring extending in one direction on the substrate and a gate pad electrode positioned at one end of the gate wiring;
A gate pad auxiliary pattern formed of the same material as the pixel electrode and positioned under the gate pad electrode;
A gate insulating layer including a first gate pad contact hole exposing the gate pad electrode;
A data line crossing the gate line and the gate insulating layer to define a pixel area;
A thin film transistor positioned at an intersection point of the gate line and the data line and including a gate electrode, a semiconductor layer, a source electrode, and a drain electrode;
A step compensation pattern formed of the same material as the data line, the source electrode, and the drain electrode, and disposed on the gate insulating layer and in contact with the gate pad electrode through the first gate pad contact hole;
A protective layer on the thin film transistor, the pixel electrode, and the step compensation pattern, and including a second gate pad contact hole exposing the step compensation pattern;
A common electrode having a plurality of openings on the protective layer corresponding to the pixel area;
The gate pad auxiliary electrode is formed of the same material as the common electrode and is in contact with the step compensation pattern through the second gate pad contact hole.
An array substrate for a fringe field switching mode liquid crystal display device comprising a.
The method according to any one of claims 1 and 2,
And the gate pad auxiliary pattern protrudes laterally relative to the gate pad electrode.
The method of claim 3, wherein
And the gate insulating layer and the protective layer include first and second gate pad auxiliary contact holes exposing protruding side surfaces of the gate pad auxiliary pattern.
The method of claim 4, wherein
And first and second gate pad connection electrodes connecting the gate pad auxiliary pattern and the gate pad auxiliary electrode to the first and second gate pad auxiliary contact holes, respectively.
The method of claim 1,
And the gate wiring and the gate electrode have a double layer structure including the same material layer as the pixel electrode.
Forming a pixel electrode and a gate pad auxiliary pattern on the substrate;
Forming a gate wiring, a gate electrode, and a gate pad electrode on the substrate, the material including the pixel electrode;
Forming a gate insulating layer over the pixel electrode, the gate wiring, the gate electrode, and the gate pad electrode;
Forming a pixel electrode contact hole and a first gate pad contact hole on the gate insulating layer to form an active layer and an impurity amorphous silicon layer and simultaneously expose a portion of the pixel electrode and a portion of the gate pad electrode;
An ohmic contact spaced apart from each other by removing the impurity amorphous silicon layer exposed between the source and drain electrodes while forming a source and a drain electrode over the impurity amorphous silicon layer and the data line defining the pixel area crossing the gate wiring. Forming a layer;
Forming a protective layer on an entire surface of the substrate including the source and drain electrodes;
Forming a second gate pad contact hole in the protective layer, the second gate pad contact hole overlapping the first gate pad contact hole;
A gate pad is formed on the passivation layer to have a plurality of bar-shaped openings spaced at predetermined intervals corresponding to the pixel area, and is connected to the gate pad electrode through the second gate pad contact hole. Forming an auxiliary electrode
Method for manufacturing an array substrate for a fringe field switching mode liquid crystal display device comprising a.
The method of claim 7, wherein
And forming the gate pad auxiliary pattern and forming the gate pad electrode are performed through a one-time halftone mask process.
The method of claim 7, wherein
The forming of the active layer and the impurity amorphous silicon layer, and the forming of the pixel electrode contact hole and the first gate pad contact hole are performed through a single halftone mask process for a fringe field switching mode liquid crystal display device. Manufacturing method for array substrate.
The method of claim 7, wherein
And the first and second gate contact contact holes are formed at the same time.
The method of claim 7, wherein
In the forming of the data line, an array for a fringe field switching mode liquid crystal display device contacting the gate pad electrode through the first gate pad contact hole and further forming a step compensation pattern made of the same material as the data line. Manufacturing method for a substrate.
The method of claim 7, wherein
In the forming of the second gate pad contact hole, the first and second gate pad auxiliary contact holes are further formed on both sides of the first and second gate pad contact holes, respectively, on the protective layer and the gate insulating layer under the protective layer. A method for manufacturing an array substrate for a fringe field switching mode liquid crystal display device to be formed.
The method of claim 12,
In the forming of the common electrode, the first and second gate pad auxiliary contact holes are made of the same material as the common electrode, and the first and second connecting the gate pad auxiliary pattern and the gate pad auxiliary electrode to each other. 2 A manufacturing method for an array substrate for a fringe field switching mode liquid crystal display device further forming a gate pad connection electrode.

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