KR20070106260A - Array substrate for liquid crystal display device and method of fabricating the same - Google Patents

Abstract

An array substrate for a liquid crystal display device and a method for fabricating the same are provided to reduce the manufacturing cost by reducing the number of masks, prevent wavy noises by forming source and drain electrodes to shield an end of an active layer, and improve an aperture ratio and brightness by not forming a semiconductor pattern under data lines. Gate lines extended in one direction through a first mask process are formed on a substrate(201) having a pixel area. Gate electrodes(208) branched from the gate lines are formed on the substrate. A gate insulating film(215), a pure amorphous silicon layer, and an impure amorphous silicon layer are sequentially formed on the gate electrodes. The impure amorphous silicon layer, the pure amorphous silicon layer, and the gate insulating film are patterned through a second mask process to form an active layer(218) of the pure amorphous silicon layer and an impure amorphous silicon pattern in a state of being connected with an upper part of the active layer corresponding to the gate electrodes. At the same time, a substrate surface of a center of the pixel area is exposed and the gate insulating film is exposed correspondingly to the gate lines. A metal layer is formed on the impure amorphous silicon pattern. Data lines(235) crossing the gate lines for defining the pixel area are formed through a third mask process. A source electrode(240) connected with the data lines is formed on the impure amorphous silicon pattern. A drain electrode exposing a center of the impure amorphous silicon pattern is formed. An insulating layer is formed on the data lines, and the source and drain electrodes. A photo resist pattern(285) is formed on the insulating layer correspondingly to the source and drain electrodes, and the data and gate lines. The insulating layer exposed out of the photo resist pattern is removed by etching to form a protecting layer pattern exposing the substrate surface of the center of the pixel area and an end of the drain electrode. A transparent conductive material(258) is deposited on the photo resist pattern for generating natural disconnection at an end of the photo resist pattern to form a pixel electrode at the center of the pixel area for directly contacting with the end of the drain electrode and the substrate surface. The photo resist pattern and the transparent conductive material layer are removed by stripping.

Description

Array substrate for liquid crystal display device and method of fabricating the same

1 is an exploded perspective view of a general liquid crystal display device.

2 is a cross-sectional view of one pixel area including a thin film transistor of an array substrate of a liquid crystal display device manufactured by a conventional five mask process.

3 is a cross-sectional view of one pixel region including a thin film transistor of an array substrate for a liquid crystal display device manufactured by a conventional four mask process.

4A to 4D are plan views of manufacturing process steps (mask processes) for one pixel region including a thin film transistor and a storage capacitor of an array substrate for a liquid crystal display according to the present invention.

5A to 5K are cross-sectional views of the manufacturing process of the portion (switching region) cut along the cutting line V-V in FIGS. 4A to 4D.

6A to 6K are sectional views of the manufacturing process of the portion (storage region) cut along the cutting line VI-VI in FIGS. 4A to 4D.

7A to 7K are cross-sectional views of a manufacturing process of a cut portion of a gate pad portion of an array substrate for a liquid crystal display device according to the present invention.

8A to 8K are cross-sectional views of a manufacturing process of a portion cut out of a data pad portion of an array substrate for a liquid crystal display device according to the present invention;

9 is a plan view of one pixel region of an array substrate for a liquid crystal display device according to a first modification of the embodiment of the present invention;

Fig. 10 is a plan view of one pixel region of an array substrate for a liquid crystal display device according to a second modification of the embodiment of the present invention.

FIG. 11 is a cross-sectional view of a portion taken along the cutting line VI-XI of FIG. 9. FIG.

FIG. 12 is a cross-sectional view of a portion taken along cut line XXX-XII of FIG. 10; FIG.

<Description of Symbols for Main Parts of Drawings>

201: substrate 208: gate electrode

215: gate insulating film 218: active layer

223: ohmic contact layer 227: semiconductor layer

235 data wiring 240 source electrode

243: drain electrode 250: protective layer

258 transparent conductive material layer 285 photoresist pattern

P: pixel area

TrA: switching area

The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing an array substrate for a liquid crystal display device.

Recently, liquid crystal displays have been spotlighted as next generation advanced display devices having low power consumption, good portability, high technology value, and high added value.

Among the liquid crystal display devices, an active matrix liquid crystal display device having a thin film transistor, which is a switching element that can control voltage on and off for each pixel, has the best resolution and video performance. I am getting it.

In general, an LCD device forms an array substrate and a color filter substrate through an array substrate manufacturing process for forming a thin film transistor and a pixel electrode, and a color filter substrate manufacturing process for forming a color filter and a common electrode, and between the two substrates. It completes through the cell process through liquid crystal in the process.

In more detail, referring to FIG. 1, which is an exploded perspective view of a general liquid crystal display device, as illustrated, the array substrate 10 and the color filter substrate 20 face each other with the liquid crystal layer 30 interposed therebetween. The array substrate 10 of the lower part includes a plurality of gate lines 14 and data lines 16 arranged vertically and horizontally on the upper surface of the transparent substrate 12 to define a plurality of pixel regions P. Thin film transistors T are provided at the intersections of the two wires 14 and 16 to be connected one-to-one with the pixel electrodes 18 provided in the pixel regions P. FIG.

In addition, the upper color filter substrate 20 facing the array substrate may cover a non-display area such as the gate line 14, the data line 16, and the thin film transistor T on the rear surface of the transparent substrate 22. Grid-like black matrix 25 is formed so as to border each pixel region P, and the red, green, and blue color filter layers 26 are sequentially arranged to correspond to each pixel region P in the grid. ) Is formed, and a transparent common electrode 28 is provided over the entirety of the black matrix 25 and the red, green, and blue color filter layers 26.

Although not shown in the drawings, these two substrates 10 and 20 are sealed with a sealant or the like along the edges to prevent leakage of the liquid crystal layer 30 interposed therebetween. In the boundary portion of each substrate (10, 20) and the liquid crystal layer 30 is interposed upper and lower alignment layer that provides reliability in the molecular alignment direction of the liquid crystal, and at least one outer surface of each substrate (10, 20) A polarizing plate is provided.

In addition, a back-light is provided on the outer surface of the array substrate to supply light. The on / off signals of the thin film transistor T are sequentially scanned by the gate wiring 14. When the image signal of the data wiring 16 is transmitted to the pixel electrode 18 of the pixel region P applied and selected, the liquid crystal molecules are driven by the vertical electric field therebetween, and thus the light transmittance is changed. Branch images can be displayed.

FIG. 2 is a cross-sectional view of one pixel region including a thin film transistor in the array substrate of the liquid crystal display device described above.

Although not shown in the drawing, a gate electrode 60 is formed in a plurality of pixel regions P defined by crossing a plurality of gate lines (not shown) and data lines (not shown) on the substrate 59. A gate insulating film 68 is formed on the entire surface of the gate electrode 60, and a semiconductor layer 70 including an island-like active layer 70a and an ohmic contact layer 70b is sequentially formed thereon.

A source electrode 76 and a drain electrode 78 facing each other at a predetermined distance from the source electrode 76 are formed on the ohmic contact layer 70b. In this case, the semiconductor layer 70 is patterned through one mask process, and then a metal layer is formed, and then source and drain electrodes 76 and 78 are formed through another mask process, thereby forming the source and drain electrodes 76 and 78. Each end of the N-axis is extended so as to completely cover the edge of the semiconductor layer 70.

In addition, a protective layer 86 including a drain contact hole 80 exposing the drain electrode 78 is formed over the source and drain electrodes 76 and 78 and the exposed active layer 70a. The pixel electrode 88 is formed on the passivation layer 86 independently of each pixel region P and contacts the drain electrode 78 through the drain contact hole 80.

In this case, the wiring and the electrode pattern of the above-mentioned array substrate for a liquid crystal display device are formed by a photolithography process using a photoresist that is a photosensitive material.

In the photolithography process, a photoresist is applied on the metal material layer, the insulating material layer, or the semiconductor material layer, a step of placing and exposing a mask having a predetermined pattern, and a photoresist is developed by developing the exposed photoresist layer. A pattern is formed, and the metal material layer, the insulating material layer, or the semiconductor material layer is etched using the photoresist pattern as a mask to form a wiring, an electrode, a contact hole, or a semiconductor pattern.

In this case, the photoresist material may be divided into a positive type in which the exposed part is developed and a negative type in which the exposed part remains. In general, a positive photoresist material is used in an array process. .

Since the number of steps is determined according to the number of masks, the photolithography step will be referred to as a mask step.

Referring to the manufacturing process of the array substrate for a liquid crystal display device having the above-described cross-sectional structure, after depositing a first metal material on the substrate 59, the gate electrode 60 and the gate wiring (by the first mask process) are deposited. The first insulating material, pure amorphous silicon (a-Si), and impurity amorphous silicon (n + a-Si) are successively deposited, and then the first insulating material is transferred to the gate insulating film 68. The pure amorphous silicon layer and the impurity amorphous silicon layer are formed as the active layer 70a and the ohmic contact layer 70b at positions covering the gate electrode 60 by the second mask process to form the semiconductor layer 70. Configure.

Next, after the deposition of the second metal material, source and drain electrodes 76 and 78 spaced apart from each other by a third mask process on the data line 73 and the semiconductor layer 70 are formed. In this step, the ohmic contact layer 70b in the spaced intervals is removed using the source and drain electrodes 76 and 78 as a mask, and the active layer 70a, which is a lower layer thereof, is exposed to form a channel. The gate electrode 60, the semiconductor layer 70, the source and drain electrodes 76 and 78 form a thin film transistor Tr.

Next, after the deposition of the second insulating material, a protective layer 86 having a drain contact hole 80 exposing a part of the drain electrode 78 is formed by a fourth mask process, and then the protective layer 86 is formed. The pixel electrode 88 is formed by depositing a transparent conductive material on the substrate) and patterning the same by a fifth mask process.

As described above, in the conventional array process for liquid crystal display devices, an array substrate is usually manufactured by a five mask process.

However, the mask process requires equipment for each deposition, exposure, development, and etching process, and the process cost is high due to repeated physical and chemical processes, and there is a high possibility of damaging other devices during the process, which lowers the process efficiency. There is this.

To solve this problem, as shown in FIG. 3 (sectional view of one pixel region including a thin film transistor of an array substrate for a liquid crystal display device manufactured by a conventional four mask process), a gate on the substrate 101 is formed. After forming the electrode 105 and the gate wiring (not shown), the gate insulating material layer, the amorphous silicon material layer, the impurity amorphous material layer, and the metal material layer are successively formed and patterned by diffraction exposure. The semiconductor layer 120 including the active layer of amorphous silicon and the ohmic contact layer 120b of impurity amorphous silicon, the source and drain electrodes 130 and 135, and the data line 127 are formed by one mask process. A method of manufacturing the array substrate 101 for a liquid crystal display device through four mask processes has been proposed.

However, in order to reduce one mask process, the liquid crystal display manufactured by the above-described four mask process sequentially stacks a pure amorphous silicon layer, an impurity amorphous silicon layer, and a metal layer, applies a photoresist, and then performs diffraction exposure. The semiconductor layer 120 including the source and drain electrodes 130 and 135 and the active layer 120a and the ohmic contact layer 120b is formed by one mask process, that is, the source and drain electrodes. (130, 135) by extending to the outside of both ends to form a structure to expose the active layer 121 other than the active layer 120 that forms a channel exposed to the outside of the source and drain electrodes (130, 135) When the active layer 121 exposed to the outside of the ends of the source and drain electrodes 130 and 135 is driven using the array substrate 101 having such a structure, Excited by light incident from a backlight (not shown), etc. provided in the device, or from external light, it affects the data wiring 127 for switching the thin film transistor or inputting a data signal, thereby causing stains on the screen. It causes a problem of wavy noise. Furthermore, a semiconductor including an impurity amorphous pattern 122b made of impurity amorphous silicon, including an active pattern 122a of pure amorphous silicon having a width wider than the width of these data lines 127 even below the data line 127. The pattern 122 is formed, in order to prevent the parasitic capacitance with these semiconductor patterns 122, the data wiring (73 in FIG. 2) of the array substrate (59 in FIG. 2) manufactured by a conventional five-mask process. In other words, the data line 150 has a larger spacing (d2> d1 in FIG. 2) between the pixel electrode 150 and the data line 127 than the spaced distance d1 from the pixel electrode (88 in FIG. 2). 127) The spacing d3 at the end of the active pattern 122a exposed to the outside is the same size as the spacing (d1 in FIG. 2) on the array substrate (59 in FIG. 2) manufactured by the 5 mask process (FIG. 2). The pixel electrode 150 such that d3 of 3 = d1 of FIG. To form.

As a result, the width of the black matrix (not shown) formed on the color filter substrate (not shown) opposite to the light filter to prevent light leakage from the light through the widened spacing (d2) is increased. Since it is necessary to form a wider than the width of the (not shown), there is a problem that the opening ratio is lowered compared to the array substrate manufactured by the conventional five mask process.

In order to solve the above problems, the present invention has a first object of simplifying the manufacturing process and cost reduction compared to the progress of the five mask process by proceeding to the four mask process.

In addition, as in the 5 mask process, the active layer is not exposed outside the ends of the source and drain electrodes, and further, the semiconductor pattern is not formed under the data line, thereby preventing the wavy noise caused by the photo current. At the same time, it is a second object to improve the aperture ratio compared with the array substrate by the conventional four mask process.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display device, including a gate wiring extending in one direction and a gate electrode branched from the gate wiring on a substrate on which a pixel region is defined through a first mask process. Forming; The gate insulating film, the pure amorphous silicon layer, and the impurity amorphous silicon layer are sequentially formed on the entire surface of the gate electrode, and the impurity amorphous silicon layer, the pure amorphous silicon layer, and the gate insulating film are patterned through a second mask process to form the gate. Forming an impurity amorphous silicon pattern in a state of being connected to an active layer of pure amorphous silicon in correspondence with an electrode, simultaneously exposing the substrate surface of the central portion of the pixel region, and exposing the gate insulating film to correspond to the gate wiring; Steps; A metal layer is formed on the entire surface of the impurity amorphous silicon pattern, and a third mask process is performed to form a data line defining the pixel area by crossing the gate line, and at the same time, connect the data line over the impurity amorphous silicon pattern. Forming a source electrode and a drain electrode spaced apart from the source electrode to expose a center portion of the impurity amorphous silicon pattern; Forming an insulating layer over the data line and over the source and drain electrodes; Forming a photoresist pattern on the insulating layer corresponding to the source and drain electrodes, the data wirings, and the gate wirings through a fourth mask process; Removing the insulating layer exposed to the outside of the photoresist pattern by performing etching to form a protective layer pattern exposing the substrate surface of the center of the pixel region and the end of the drain electrode; The transparent conductive material is deposited on the entire surface of the photoresist pattern on which the protective layer pattern is formed, thereby causing a natural break at the end of the photoresist pattern, thereby directly contacting the end of the drain electrode and the substrate surface at the center of the pixel region. Forming an electrode; Advancing a strip to remove the photoresist pattern and the transparent conductive material layer formed thereon.

The method may further include forming an ohmic contact layer under the source and drain electrodes by removing the impurity amorphous silicon pattern between the spaced source and drain electrodes, wherein one end of the source and drain electrodes faces each other. The other end is characterized in that it is formed to sufficiently cover the other end of the ohmic contact layer below.

In addition, the insulating layer has a first thickness, and the transparent conductive material is deposited to have a second thickness thinner than the first thickness.

In addition, the etching for forming the protective layer pattern is preferably over-etched so that the protective layer pattern forms an under cut under the photoresist pattern.

 The forming of the gate line and the gate electrode may further include forming a first storage electrode branched from the gate line in the pixel area, wherein forming the pixel electrode And forming a second storage electrode as the same material forming the pixel electrode by preventing the photoresist pattern from being formed corresponding to the first storage electrode, wherein the active layer and the impurity amorphous silicon pattern are formed. The forming may further include forming an auxiliary storage electrode having a double layer structure as pure amorphous silicon and impurity amorphous silicon forming the active layer on the gate insulating layer corresponding to the first storage electrode.

The forming of the data line with the source and drain electrodes may further include forming an island-shaped second storage electrode corresponding to the first storage electrode, wherein the pixel electrode is the second storage. It is characterized in that it is formed in contact with the electrode.

The method may further include forming an impurity amorphous silicon pattern in a state of being connected to the active layer and an upper portion thereof through a second mask process, and simultaneously exposing the gate insulating layer to correspond to the substrate surface and the gate wiring in the center of the pixel region. A first photoresist pattern having a first thickness is formed in a region where the impurity amorphous silicon pattern is to be formed on the impurity amorphous silicon layer, and at the same time, a second photoresist having a second thickness is formed at a portion where the exposed gate insulating layer is to be formed. Forming a pattern, and exposing the impurity amorphous silicon layer in other regions; Etching the impurity amorphous silicon layer, the pure amorphous silicon layer, and the gate insulating film of the portion exposed to the outside of the first and second photoresist patterns to expose the substrate surface; Removing the second photoresist pattern of the second thickness by ashing; Etching away the impurity amorphous silicon layer exposed by removing the second photoresist pattern and the pure amorphous silicon layer thereunder to expose the gate insulating film; Removing the first photoresist pattern.

The forming of the gate wiring and the gate electrode may further include forming a gate pad electrode connected to the gate wiring at one end of the gate wiring, wherein the second mask process includes a central portion of the gate pad electrode. And exposing the source and drain electrodes and the data line, further comprising forming a data pad electrode connected to the data line at one end of the data line. Forming the electrode and the data line further includes forming an auxiliary gate pad electrode covering the exposed gate pad electrode with the same material on which the data line is formed.

The method may further include exposing the substrate surface and the drain electrode end of the center of the pixel region, and forming the protective layer pattern under the photoresist pattern, further including exposing the gate pad electrode and the data pad electrode. In this case, the forming of the pixel electrode may further include forming a gate auxiliary pad electrode and a data auxiliary pad electrode on the exposed gate pad electrode and the data pad electrode, respectively, using the same material forming the pixel electrode. Include.

In addition, the data line is formed in direct contact with the gate insulating film.

An array substrate for a liquid crystal display device according to the present invention includes: the gate wiring extending in one direction on a substrate on which a pixel region is defined; A gate electrode branched from the gate wiring in the pixel region; A gate insulating layer formed on the gate electrode, the gate wiring, and the first storage electrode and exposing the substrate at the center of the pixel electrode; An active layer formed over the gate insulating layer on the gate electrode; An ohmic contact layer spaced apart from each other on the active layer; A source and a drain electrode formed on the ohmic contact layer, the other end of the ohmic contact layer being completely in contact with the other end of the ohmic contact layer and completely covering the other end of the ohmic contact layer; A data line connected to the source electrode over the gate insulating layer, the data line being formed to define the pixel area crossing the gate line; A protective layer formed while exposing the other end of the drain electrode; And a pixel electrode formed in direct contact with the other end of the drain electrode exposed to the outside of the protective layer and an exposed substrate of a central portion of the pixel region.

In this case, the data line is formed in direct contact with the gate insulating layer, the protective layer has a first thickness, and the pixel electrode has a second thickness thinner than the first thickness.

The first storage electrode may be formed in the pixel region on the substrate, the first storage electrode being branched from the gate wiring; The gate insulating layer further formed on the first storage electrode; And further comprising a second storage electrode formed to extend the pixel electrode over the gate insulating layer, wherein the active layer is formed between the gate insulating layer and the second storage electrode in correspondence to the first storage electrode. And an auxiliary storage electrode having a double pattern structure of impurity amorphous silicon in which the ohmic contact layer is formed.

The first storage electrode may be formed in the pixel region on the substrate, the first storage electrode being branched from the gate wiring; The gate insulating layer further formed on the first storage electrode; The upper layer further includes an island-shaped second storage electrode formed on the same layer of the same material on which the data line is formed on the gate insulating layer, and an upper end of the one end thereof is in contact with the pixel electrode.

In addition, a gate pad electrode connected to the gate line is formed at one end of the gate line on the substrate, and a data pad electrode connected to the data line is further formed at one end of the data line over the gate insulating layer. A gate insulating layer exposing the center portion and a gate first auxiliary pad electrode formed in the same step as the data line and contacting the exposed gate pad electrode are formed, wherein the gate first auxiliary pad electrode is formed. The gate second auxiliary pad electrode and the data auxiliary pad electrode formed in the same step as the pixel electrode may be further formed on the data pad electrode.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

4A to 4D are plan views of manufacturing process steps (mask processes) of one pixel region P including a thin film transistor and a storage capacitor of an array substrate for a liquid crystal display according to the present invention. 4A to 4D are sectional views of the manufacturing process of the portion (switching region) cut along the cutting line VV, and FIGS. 6A to 6K are the portions (storage region) of Fig. 4A to 4D cutting along the cutting line VI-VI. 7A to 7K are manufacturing process cross sectional views of the cut portion of the gate pad portion at the gate wiring end, and FIGS. 8A to 8K are manufacturing process sectional views of the portion cut at the data pad portion of the data wiring edge. .

In this case, for convenience of description, a portion in which the thin film transistor is to be formed in each pixel region P is defined as a switching region TrA and a portion in which a storage capacitor is to be formed as a storage region StgA.

First, as shown in FIGS. 4A, 5A, 6A, 7A, and 8A, a metal material is deposited on a transparent insulating substrate 201 to form a first metal layer (not shown), and then a photoresist coating and masking is performed. A first mask process including exposure, development of photoresist, etching, strip of photoresist, and the like, to form a gate wiring 205 extending in one direction, and simultaneously the switching region TrA. ), A gate electrode 208 protruding from the gate line 205 is formed.

Meanwhile, in the storage area StgA, the gate wiring 205 formed above and below the pixel area P is formed to have a wider width than other areas, so that the wider portion of the storage area StgA extends the first storage electrode 210. In the gate pad part GPA, an end of the gate line 205 forms a gate pad electrode 212 as itself.

In this case, the first metal layer (not shown) may be formed of at least a double layer by continuously depositing different metal materials, thereby forming a gate wiring, a gate electrode, a first storage electrode, and a gate pad electrode having a double layer or triple layer structure. It may be. In the drawings it is shown as a single layer formed for convenience.

Next, as shown in FIGS. 5B, 6B, 7B, and 8B, silicon oxide (SiO ₂ ) or silicon nitride (SiNx) may be formed on the entire surface of the substrate 201 where the gate wiring 205 and the gate electrode 208 are formed. By sequentially depositing an inorganic insulating material, pure amorphous silicon, and impurity amorphous silicon, the gate insulating film 215, the pure amorphous silicon layer 216, and the impurity amorphous silicon layer 217 are sequentially formed from the bottom thereof.

Thereafter, a photoresist is applied on the impurity amorphous silicon layer 217 to form a photoresist layer 280. In this case, the photoresist layer 280 will be described by using a positive type (positive type) having a characteristic that the light-received portion is removed during development. However, the opposite result, that is, the case of the negative type that remains after development is the same result using a mask in which the positions of the transmission and blocking regions are changed in the mask to be described later. Can be obtained.

Next, the light transmitting area TA and the blocking area BA and the slit-shaped structure are formed on the substrate 201 on which the photoresist layer 280 is formed. After the mask 291 is made of a semi-transmissive area (HTA) that can further control the amount of light passing through the coating of the film, the exposure through the mask 291 is performed.

The photoresist may vary in thickness by applying a diffraction exposure technique or a halftone exposure to adjust the amount of light reaching the photoresist layer 280 by exposing using the mask 291 provided with the transflective area HTA. In order to form a pattern, the amount of light transmitted through exposure through the mask 291 is almost 100% transmitted in the transmission area TA, and light is not transmitted at all in the blocking area BA. In the semi-transmissive area (HTA), light having a transmission amount determined between 10% and 90% is transmitted according to the slit structure or the thickness of the coating film (or the coating water of the coating film). In this case, the exposure corresponds to a portion where the blocking region BA of the mask 291 corresponds to a portion where the semiconductor layer is formed in the switching region TrA, that is, the gate electrode 208, and the storage region StgA. Preferably, the transmission area TA corresponds to a portion of the center portion of the pixel region P where the pixel electrode is to be formed and a portion of the center portion of the gate pad electrode 212 in the gate pad portion GPA, and half of the other region. It proceeds in the state which made the transmission area correspond.

Next, as described above, after exposing the mask 291 to correspond to the photoresist layer 280 on the substrate 201, and then developing the exposed photoresist layer 280, FIGS. 5C, 6C, 7C and As shown in FIG. 8C, a portion of the gate wiring 205 including the gate electrode 208 and the first storage electrode 210 to branch the first storage electrode 210 onto the impurity amorphous silicon layer 217. Correspondingly, the first photoresist pattern 281a having the first thickness t1 and the portion and data on which the gate wiring 205 and the data wiring are to be formed are formed at portions not used as the first storage electrode 210. In response to the pad portion DPA, a second photoresist pattern 281b having a second thickness t2 that is thinner than the first thickness t1 is formed, and a portion of the center and the pixel region of the gate pad electrode 212 is formed. P) the impurities are removed corresponding to the central portion Amorphous, thereby exposing the silicon layer 217.

In this case, as a modification, a second photoresist pattern having a second thickness, rather than a first photoresist pattern having a first thickness, may also be formed on the first storage electrode of the storage region and the gate wiring portion which branches the same. This modification will be described later.

Next, as shown in FIGS. 5D, 6D, 7D, and 8D, 217 of the impurity amorphous silicon layer (FIGS. 5C, 6C, 7C, and 8C) using the first and second photoresist patterns 281a and 281b as an etching mask. ) And the pure amorphous silicon layer (216 in FIGS. 5C, 6C, 7C, and 8C) and the gate insulating film 215 are exposed to expose the substrate 201 to the central portion of the pixel region P where the pixel electrode is to be formed. At the same time, the center portion of the gate pad electrode 212 is exposed in the gate pad portion GPA. In other regions, the first or second photoresist patterns 281a and 281b are formed over the impurity amorphous silicon layer (217 in FIGS. 5C, 6C, 7C and 8C), and still have an impurity amorphous silicon layer ( In addition to the 217, the pure amorphous silicon layer 216 and the gate insulating layer 215 remain.

Next, as shown in FIGS. 5E, 6E, 7E, and 8E, the substrate 201 having the surface of the substrate 201 in the pixel area P and the gate pad electrode 212 exposed in the gate pad part GPA is exposed. ) And the gate including the gate electrode 208 and the first storage electrode 210 by removing the second photoresist pattern 281b of FIGS. 5D and 6D having the second thickness. The impurity amorphous silicon layer (217 in FIGS. 5D, 6D, 7D, and 8D) is exposed in an area except the upper portion of the wiring 205 portion. In this case, the thickness of the first photoresist pattern 281a and a predetermined width of the side portion thereof are also reduced, so that a portion of an end portion of the impurity amorphous silicon layer (217 in FIGS. 5D and 6D) is changed in the switching region TrA and the storage region StgA. Exposed.

The gate pad electrode 212 is then etched by etching the exposed impurity amorphous silicon layer (217 in FIGS. 5D, 6D, 7D, and 8D) and the pure amorphous silicon layer (216 in FIGS. 5D, 6D, 7D, and 8D) below. An upper portion of the gate electrode 208 and a first storage electrode 210 which are still covered by the central portion, the central portion of the pixel region P, and the first photoresist pattern 281a include a branch of the gate wiring 205. The gate insulating layer 215 may be disposed in an area excluding the upper portion, that is, an area where a data line is to be formed, a pure gate line area, a data pad part DPA, and a gate pad part GPA except the exposed gate pad electrode 212. Expose

Next, as shown in FIGS. 4B and 5F, 6F, 7F, and 8F, ashing or stripping is performed on the gate insulating film 215 and the substrate 201 where the surface of the substrate 201 is exposed in the pixel region. the first impurity amorphous silicon pattern 221 and the pure amorphous silicon active in a state connected corresponding to the gate electrode 208 by removing the first photoresist pattern (281a in FIGS. 5E and 6E) by performing a strip. A layer 218 is formed, and a second storage electrode 228 having a double layer structure formed of a second impurity amorphous silicon pattern 222 and a pure amorphous silicon pattern 219 is formed to correspond to the first storage electrode 210. . At this time, only the gate insulating layer 215 is still formed in the portion where the data line is to be formed.

In this case, the structure according to the process steps that have been performed so far will be described. The gate insulating layer 215 and the pure amorphous silicon patterns 218 and 219 (switching) correspond to the upper portions of the gate electrode 208 and the first storage electrode 210. In the region TrA, the active layer 218 is formed) and the first or second impurity amorphous silicon patterns 221 and 222 are stacked. In the pixel region P, the central portion where the pixel electrode is to be formed is formed. All material layers stacked for the first time are removed to expose the surface of the substrate 201, and the gate pad electrode 212 is exposed to the center portion of the gate pad electrode 212. For the upper portion of the gate wiring formed in the remaining region except for the portion of the gate wiring 205 for branching the electrode, the region where the data wiring is to be formed, and the gate and data pad portions (GPA, DPA) are included. It is characterized bit insulating film 215, only that make up the structure formed.

Next, as illustrated in FIGS. 4C and 5G, 6G, 7G, and 8G, a first impurity amorphous silicon pattern 221 of FIG. 5F is formed on the gate electrode 208 and connected to the active layer 218. In the storage area StgA, a metal material, for example, molybdenum (Mo), chromium (Cr), aluminum (Al), and aluminum alloy (AlNd), is formed on the entire surface of the substrate 201 on which the auxiliary storage electrode 228 having a double layer structure is formed. ), A second metal layer (not shown) is formed by depositing one of copper (Cu) and a copper alloy and patterned to form a data line 235 crossing the gate line 205 to define a pixel region P. And a data pad electrode 245 on the gate insulating film 215 at the data pad part DPA at the end of the data line 235, and the exposed gate pad in the gate pad part GPA. The first gate auxiliary pad electrode 247 is covered with the electrode 212. Innovation is formed.

At the same time, the source electrode 240 connected to the data line 235 and the drain electrode 243 are formed in the switching region TrA at a predetermined distance from the source electrode 240. In this case, the source and drain electrodes 240 and 243 completely cover the ends of the impurity amorphous silicon pattern 221 of FIG. 5F, that is, longer than the ends of the impurity amorphous silicon pattern 221 of FIG. 5F. It is a characteristic aspect of this invention to form this. In this case, the other end of the drain electrode 243 may be extended to the pixel region P. This is to ensure that the drain electrode 243 and the pixel electrode are in direct contact with each other when the pixel electrode is formed later.

At this time, referring to FIG. 4C, which is a plan view, the source and drain electrodes 240 and 243 have a shape in which a channel region defined as their separation region is rotated 90 degrees clockwise on the lower semiconductor layer 227. It can be seen that formed to form a U 'shape. This is because the source and drain electrodes 240 and 243 are formed in a bar shape to improve the characteristics of the thin film transistor, rather than forming an 'I' channel region.

Next, after forming the source and drain electrodes 240 and 243 and the data line 235 spaced apart from each other by patterning the second metal layer, an impurity amorphous state in the connected state exposed to the outside of the source and drain electrodes 240 and 243 is formed. The silicon pattern (221 of FIG. 5F) is removed by dry etching to form an ohmic contact layer 223 spaced apart from each other. In this case, the spaced apart ohmic contact layer 223 has one side end facing each other coinciding with one end of each of the source and drain electrodes 240 and 243 formed thereon, and the other side end thereof is the source and It is characterized in that it forms a form completely covered by the other ends of the drain electrodes (240, 243).

Next, as shown in FIGS. 5H, 6H, 7H, and 8H, an inorganic insulating material such as silicon oxide (SiO ₂ ) is formed on the substrate 201 where the data line 235 and the source and drain electrodes 240 and 243 are formed. ) Or a silicon nitride (SiNx) or by depositing an organic insulating material, for example, photo acryl or benzocyclobutene (BCB) to form a protective layer (250).

Thereafter, a photoresist is formed on the passivation layer 250 to form a photoresist layer (not shown). The photoresist layer is exposed and developed to expose the gate wiring 205 and the data wiring 235 and the switching region TrA. In response to this, the photoresist pattern 285 is formed.

Next, as shown in FIGS. 5I, 6I, 7I, and 8I, the gate and the protective layer 250 exposed to the outside of the photoresist pattern 285 are removed by using the photoresist pattern 285 as an etching mask. The first gate auxiliary pad electrode 247 and the data pad electrode 245 are respectively exposed in the data pad parts GPA and DPA, and the other end of the drain electrode 243 is included in the pixel area P. The surface of the substrate 201 is exposed by removing the protective layer 250 at the center portion.

In this case, the etching of the protective layer 250 may be performed by over-etching so that the protective layer 250 having a predetermined width below the end of the photoresist pattern 285 may be removed. (285) It is preferable to form a protective layer 250 formed under the cut (under cut).

Forming the protective layer 250 so as to have an under cut shape with respect to the photoresist pattern 285 may include a transparent conductive material layer formed on the photoresist pattern 285 and a layer thereof. This is to prevent the transparent conductive material layer formed on the other substrate 201 surface or the gate insulating layer 215 from being connected to the under cut portion.

Next, as illustrated in FIGS. 5J, 6J, 7J, and 8J, examples of a transparent conductive material on the substrate 201 where the gate insulating layer 215 or the substrate 201 surface are exposed to the outside of the photoresist pattern 285. For example, a transparent conductive material layer 258 is formed by depositing indium tin oxide (ITO) or indium zinc oxide (IZO) on the front surface. In this case, the transparent conductive material layer 258 is preferably formed to have a thickness thinner than the thickness of the protective layer 250 due to the characteristics of the lift off process to be carried out.

This is because the transparent conductive material layer 258 having a thickness thinner than the thickness of the protective layer 250 has a photoresist pattern 285 formed in the previous step and an under cut shape under the protective layer 250. In order to form the undercut (under) is not connected to each other due to the structural characteristics of the ().

Therefore, the film is deposited by the structural features, and at the same time, breakage occurs in a portion where the undercut occurs, and thus a portion exposed to the outside of the photoresist pattern 285 in the gate and data pad portions GPA and DPA is formed. 2 auxiliary gate pad electrodes 265 and auxiliary data pad electrodes 267 are formed, respectively. At this time, the second auxiliary gate pad electrode 265 and the data auxiliary pad electrode 267 are made of a transparent conductive material having a strong corrosion resistance, and the first auxiliary gate pad electrode 247 and the data pad formed on the bottom thereof, respectively. It serves to prevent corrosion of the electrode 245.

In the pixel region P, the pixel electrode 260 is formed on the exposed substrate 201 surface to cover the other end of the drain electrode 243. In the storage region StgA, the pixel electrode 260 is formed. The second storage electrode 263 is formed by itself.

Next, as shown in FIGS. 4D and 5K, 6K, 7K, and 8K, a stripping liquid is formed on the substrate 201 having the transparent conductive material layer (258 of FIGS. 5J, 6J, 7J, and 8J) formed on the front surface thereof. It is removed from the substrate 201 by immersing in it or spraying a strip liquid onto the substrate 201 to react with the photoresist patterns 285 of FIGS. 5J, 6J, 7J and 8J.

The strip liquid is formed through the portion where the photoresist pattern (285 of FIGS. 5J, 6J, 7J, and 8J) and the protective layer 250 have an under cut shape, and is formed through the photoresist pattern (FIG. 5J, Reaction with 285 of 6j, 7j, and 8j) and by digging into the interface between the photoresist pattern (285 of FIGS. 5j, 6j, 7j, and 8j) and the protective layer 250 and weakening its contact force. 585, 6j, 7j, and 8j of FIG. 5j are separated from the protective layer 250, and the photoresist pattern 285 of FIGS. 5j, 6j, 7j, and 8j is separated from the protective layer 250. The layers of transparent conductive material (258 in FIGS. 5J, 6J, 7J, and 8J) that are removed as they separate, are also removed together, resulting in other than the photoresist patterns (285 in FIGS. 5J, 6J, 7J, and 8J). Only the transparent conductive material layer formed directly on the substrate 201 remains, so that the pixel region P The pixel electrode 260 is in contact with the other end of the drain electrode 243, and the second gate auxiliary pad electrode 265 and the data auxiliary pad electrode 267 are disposed in the gate and data pad units GPA and DPA. The second storage electrode 263 is formed in the storage region StgA at the same time.

A process of removing the photoresist pattern (285 of FIGS. 5J, 6J, 7J, and 8J) and the material layer (transparent conductive material layer) formed thereon from the substrate 201 together is called a lift off process. In the present invention, the protective layer 250 and the pixel electrode 260 are formed by performing one mask process by performing such a lift off process. An active layer 218 made of amorphous silicon may complete an array substrate for a liquid crystal display device, which is free from wave noise caused by exposure to the data line 235 or the source and drain electrodes 240 and 243. have.

The reason is that the semiconductor layer 227 including the active layer 218 and the ohmic contact layer 223, the source and drain electrodes 240 and 243 and the data line 235 are formed in different mask processes. The semiconductor pattern having a width wider than the width of the data line 235 is not formed below the data line 235, and the active layer 218 and the ohmic formed under the source and drain electrodes 240 and 243. In the contact layer 223, the other ends of the source and drain electrodes 240 and 243 other than the opposite ends of the source and drain electrodes 240 and 243 may sufficiently cover the ends of the ohmic contact layer 223 and the active layer 218 thereunder. Because it becomes.

9 and 10 are plan views of one pixel area of the array substrate for a liquid crystal display device according to the first and second modified examples of the present invention, and FIGS. 11 and 12 show cut lines VII- of FIG. 9 and FIG. 10, respectively. It is sectional drawing about the part cut along II, II-XI.

In this case, the array substrate for the liquid crystal display device according to the first and second modifications is the same for the other components of the above-described embodiment of the present invention, and only different shapes of the second storage electrode and the auxiliary storage electrode in the storage area. Only those differences are described.

First, referring to FIGS. 9 and 11, as shown in the first modification, the first storage electrode 310 formed by extending the second storage electrode 363 made of a transparent conductive material and the gate wiring 305 is extended. Note that only the gate insulating layer 315 is present between the two layers, and the semiconductor pattern 228 of the double layer structure of pure amorphous silicon and impurity amorphous silicon is not formed as in the embodiment (see FIG. 6K).

 In order to form the storage capacitor StgC in this manner, since the pure and impurity amorphous silicon patterns of the storage region StgA must be removed, referring to FIGS. 5B to 5F and 6B to 6F, the switching region TrA Instead of forming a photoresist pattern having a first thickness in the storage region StgA in the step of forming the semiconductor layer 227 on the substrate, the photoresist pattern having a second thickness is formed, and then the storage is performed. The gate insulating layer 315 is exposed in the region StgA, and the second storage electrode 363 of the transparent conductive material may be formed on the gate insulating layer 315 by proceeding in the same manner as in the above embodiment.

Meanwhile, referring to FIGS. 10 and 12, in the second modified example, there is no auxiliary storage electrode 228 of FIG. 6K, and a gate is formed between the first storage electrode 410 and the second storage electrode 469. It is similar to the first modified example in that only the insulating film 415 is formed.

However, unlike the first modification, in the second modification, as in the first modification, the semiconductor pattern is removed to form the gate insulating layer to be exposed, and then the second storage electrode 469 is connected to the data line. The data line, the source and the drain electrode are formed on the gate insulating layer 415 of the storage region StgA in the step of forming the data line and the source and the drain electrode of the material forming the source and drain electrodes (see FIGS. 5G and 6G). After forming the second metal layer for formation, the island-shaped second storage electrode 469 may be formed together with the source and drain electrodes by patterning, and then in the step of forming the pixel electrode 460 with a transparent conductive material. One end of the pixel electrode 460 may be formed in contact with the second story electrode 469 to complete the array substrate 401 according to the second modification. The.

Therefore, the embodiments of the present invention and the first and second modified examples are types in which the storage capacitor is formed in the portion by using the front gate wiring as the first storage electrode, thereby reducing the separation distance between the first and second electrodes. In this case, a protective layer and a gate insulating film are formed between the first and second storage electrodes), thereby improving the capacity of the storage capacitor.

As such, by reducing the number of masks used in comparison with the manufacturing method completed by the five mask process by the method of manufacturing the array mask for liquid crystal display device of the four masks according to the present invention, the process efficiency is increased, and the liquid crystal display is simplified due to the process simplification. There is an effect of reducing the manufacturing cost of the array substrate for the device.

In addition, the data lines including the active layer and the source and drain electrodes are formed by dualization through different mask processes, and at the same time, the source and drain electrodes are formed to cover the ends of the active layer to the outside of the source and drain electrodes. There is an effect of preventing image quality defects such as wave noise caused by the exposed active layer.

In addition, since the semiconductor pattern made of pure and impurity amorphous silicon is not formed under the data line, the gap between the data line and the pixel electrode is narrowed, thereby improving aperture ratio and improving luminance.

In addition, since the pixel electrode is directly contacted with the substrate surface in the center portion of the pixel region P, the gate insulating film and the protective layer are not formed therebetween, so that there is no decrease in transmittance caused by passing through the gate insulating film and the protective layer. It is effective to further improve.

Claims (26)

Forming a gate wiring extending in one direction and a gate electrode branched from the gate wiring on a substrate on which the pixel region is defined through a first mask process; The gate insulating film, the pure amorphous silicon layer, and the impurity amorphous silicon layer are sequentially formed on the entire surface of the gate electrode, and the impurity amorphous silicon layer, the pure amorphous silicon layer, and the gate insulating film are patterned through a second mask process to form the gate. Forming an impurity amorphous silicon pattern in a state of being connected to an active layer of pure amorphous silicon in correspondence with an electrode, simultaneously exposing the substrate surface of the central portion of the pixel region, and exposing the gate insulating film to correspond to the gate wiring; Steps; A metal layer is formed on the entire surface of the impurity amorphous silicon pattern, and a third mask process is performed to form a data line defining the pixel area by crossing the gate line, and at the same time, connect the data line over the impurity amorphous silicon pattern. Forming a source electrode and a drain electrode spaced apart from the source electrode to expose a center portion of the impurity amorphous silicon pattern; Forming an insulating layer over the data line and over the source and drain electrodes; Forming a photoresist pattern on the insulating layer corresponding to the source and drain electrodes, the data wirings, and the gate wirings through a fourth mask process; Removing the insulating layer exposed to the outside of the photoresist pattern by performing etching to form a protective layer pattern exposing the substrate surface of the center of the pixel region and the end of the drain electrode; The transparent conductive material is deposited on the entire surface of the photoresist pattern on which the protective layer pattern is formed, thereby causing a natural break at the end of the photoresist pattern, thereby directly contacting the end of the drain electrode and the substrate surface at the center of the pixel region. Forming an electrode; Performing a lift off process to remove the photoresist pattern and the transparent conductive material layer formed thereon by proceeding with a strip Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 1, And removing the impurity amorphous silicon pattern between the spaced apart source and drain electrodes to form an ohmic contact layer under the source and drain electrodes. The method of claim 2, And the other end other than one end of the source and drain electrodes facing each other to sufficiently cover the other end of the ohmic contact layer below the liquid crystal display device. The method of claim 1, The insulating layer has a first thickness, and the transparent conductive material is deposited to have a second thickness thinner than the first thickness, the manufacturing method of the array substrate for a liquid crystal display device. The method of claim 1, The etching process for forming the protective layer pattern is over-etched so that the protective layer pattern under the photoresist pattern to form an under cut (under cut) manufacturing method of the array substrate for a liquid crystal display device. The method of claim 1,  Forming the gate wiring and the gate electrode, And further forming a first storage electrode branched from the gate wiring inside the pixel region. The method of claim 6, Forming the pixel electrode, And forming a second storage electrode as the same material for forming the pixel electrode by preventing the photoresist pattern from being formed in correspondence to the first storage electrode. The method of claim 7, wherein Forming the impurity amorphous silicon pattern with the active layer, And forming an auxiliary storage electrode having a double layer structure as pure amorphous silicon and impurity amorphous silicon forming the active layer on the gate insulating layer corresponding to the first storage electrode. The method of claim 6, Forming the data line with the source and drain electrodes, And forming an island-shaped second storage electrode corresponding to the first storage electrode. The method of claim 9, And the pixel electrode is in contact with the second storage electrode. The method of claim 1,  The method may further include forming an impurity amorphous silicon pattern in a state of being connected to the active layer and an upper portion thereof through a second mask process, and simultaneously exposing the gate insulating layer to correspond to the substrate surface and the gate wiring in the center of the pixel region. A first photoresist pattern having a first thickness is formed on a region where the impurity amorphous silicon pattern is to be formed on the impurity amorphous silicon layer, and at the same time, a second photoresist pattern having a second thickness is formed on a portion where the exposed gate insulating layer is to be formed. Exposing the impurity amorphous silicon layer in other regions; Etching the impurity amorphous silicon layer, the pure amorphous silicon layer, and the gate insulating film of the portion exposed to the outside of the first and second photoresist patterns to expose the substrate surface; Removing the second photoresist pattern of the second thickness by ashing; Etching away the impurity amorphous silicon layer exposed by removing the second photoresist pattern and the pure amorphous silicon layer thereunder to expose the gate insulating film; Removing the first photoresist pattern Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 1, The forming of the gate line and the gate electrode may further include forming a gate pad electrode connected to the gate line at one end of the gate line. The method of claim 12, The second mask process may further include exposing a center portion of the gate pad electrode. The method of claim 13, The forming of the data wires with the source and drain electrodes may include forming a data pad electrode connected to the data wires at one end of the data wires. The method of claim 14, The forming of the data line and the source and drain electrodes may further include forming an auxiliary gate pad electrode covering the exposed gate pad electrode with the same material on which the data line is formed. Manufacturing method. The method of claim 14, Exposing the substrate surface of the center portion of the pixel region and the end of the drain electrode, and forming the protective layer pattern under the photoresist pattern; And exposing the gate pad electrode and the data pad electrode. The method of claim 16, Forming the pixel electrode, And forming a gate auxiliary pad electrode and a data auxiliary pad electrode on the exposed gate pad electrode and the data pad electrode, respectively, from the same material forming the pixel electrode. The method of claim 1, And said data line is formed in direct contact with said gate insulating film. The gate wiring extending in one direction on a substrate on which a pixel region is defined; A gate electrode branched from the gate wiring in the pixel region; A gate insulating layer formed on the gate electrode, the gate wiring, and the first storage electrode and exposing the substrate at the center of the pixel electrode; An active layer formed over the gate insulating layer on the gate electrode; An ohmic contact layer spaced apart from each other on the active layer; A source and a drain electrode formed on the ohmic contact layer, the other end of the ohmic contact layer being completely in contact with the other end of the ohmic contact layer and completely covering the other end of the ohmic contact layer; A data line connected to the source electrode over the gate insulating layer, the data line being formed to define the pixel area crossing the gate line; A protective layer formed while exposing the other end of the drain electrode; A pixel electrode formed in direct contact with the other end of the drain electrode exposed outside the protective layer and an exposed substrate of a central portion of the pixel region;  Array substrate for a liquid crystal display device comprising a. The method of claim 19, And the data line is in direct contact with the gate insulating layer. The method of claim 19, And the protective layer has a first thickness, and the pixel electrode has a second thickness thinner than the first thickness. The method of claim 19, A first storage electrode branched from the gate wiring in the pixel region on the substrate; The gate insulating layer further formed on the first storage electrode; A second storage electrode formed to extend the pixel electrode over the gate insulating layer Array substrate for a liquid crystal display device further comprising. The method of claim 22, A liquid crystal further comprising an auxiliary storage electrode having a double-pattern structure of amorphous silicon in which the active layer is formed between the gate insulating layer and the second storage electrode and an impurity amorphous silicon in which the ohmic contact layer is formed to correspond to the first storage electrode. Array substrate for display device. The method of claim 19, A first storage electrode branched from the gate wiring in the pixel region on the substrate; The gate insulating layer further formed on the first storage electrode; An island-shaped second storage electrode formed on the same layer of the same material as the data line on the gate insulating layer, and having an upper end thereof in contact with the pixel electrode; Array substrate for a liquid crystal display device further comprising. The method of claim 19, A gate pad electrode connected to the gate line is formed at one end of the gate line on the substrate, and a data pad electrode connected to the data line is further formed at one end of the data line over the gate insulating layer. And a gate insulating layer exposing the gate insulating layer and a gate first auxiliary pad electrode formed in the same step as the data line and in contact with the exposed gate pad electrode. The method of claim 25, And a gate second auxiliary pad electrode and a data auxiliary pad electrode formed on the gate first auxiliary pad electrode and the data pad electrode on the same material as the pixel electrode.

Images