KR101180273B1 - The method of fabricating the array substrate for liquid crystal display device - Google Patents

Abstract

In the present invention, while manufacturing the array substrate for the liquid crystal display device through a total of four mask process, the active layer is further extended from the end of the drain electrode so that the end of the drain electrode does not coincide with the end of the active layer below it. By reducing the step thickness of the protective layer formed on the upper layer, the breakage of the pixel electrode formed on the protective layer is prevented from occurring. Furthermore, during the dry etching proceeding to expose the active layer corresponding to the gate electrode, the drain electrode By performing the dray etching while exposing a part of the metal pattern of the portion to be formed, the undercut of the gate insulating layer that meets the end of the active layer can be prevented, thereby further preventing the breakage of the pixel electrode. Provided is a method of manufacturing an array substrate.

LCD, Array Board, 4 Mask, Dry Etch, Under Cut

Description

The method of fabricating the array substrate for liquid crystal display device

1 is an exploded perspective view of a general liquid crystal display device.

2 is an enlarged plan view of one pixel area in an array substrate of a conventional liquid crystal display device;

3 is a cross-sectional view of a portion cut along the cutting line III-III of FIG.

4A to 4D are cross-sectional views of a manufacturing process of one pixel region including a switching element of a conventional array substrate for a liquid crystal display device.

5A through 5H are cross-sectional views illustrating manufacturing processes of one pixel area including a thin film transistor, which is a switching element of an array substrate for a liquid crystal display according to the present invention.

Description of the Related Art

110: (array) substrate 115: gate electrode

120 gate insulating film 122 active layer

126: ohmic contact layer 127: semiconductor layer

133: source electrode 136: drain electrode

140: protective layer 190a: first photoresist pattern

ch: Channel area P: Pixel area

SA1: first stepped part SA2: second stepped part

Tr: Thin Film Transistor TrA: Switching Area

The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing an array substrate for a liquid crystal display device.

Recently, liquid crystal displays have been spotlighted as next generation advanced display devices having low power consumption, good portability, high technology value, and high added value.

Of these liquid crystal display devices, an active matrix type liquid crystal display device having a thin film transistor, which is a switching device capable of controlling voltage on and off for each pixel, .

In general, a liquid crystal display device forms an array substrate and a color filter substrate through an array substrate manufacturing process for forming thin film transistors and pixel electrodes, and a color filter substrate manufacturing process for forming color filters and common electrodes, And a liquid crystal interposed therebetween.

In more detail, the structure of the liquid crystal display device will be described with reference to FIG. 1, which is an exploded perspective view of a general liquid crystal display device. As shown in FIG. 60 has a conjoined configuration, wherein the lower array substrate 10 is arranged horizontally and crosswise to the upper surface thereof, and includes a plurality of gate lines 13 and data lines 30 defining a plurality of pixel regions P. As shown in FIG. The thin film transistor Tr, which is a switching element, is provided at an intersection point of the two wires 13 and 30, and is connected one-to-one with the pixel electrode 47 formed independently in each pixel region P. As shown in FIG.

In addition, each color filter substrate 60 facing the array substrate 10 has a rear surface thereof so as to cover non-display areas such as the gate line 13, the data line 30, and the thin film transistor Tr. A grid-like black matrix 63 bordering the region P is formed, and red, green, and blue color filter layers 67 sequentially and sequentially arranged corresponding to each pixel region P are formed in the grid. The common electrode 70 is provided over the entire surface of the black matrix 63 and the red, green, and blue color filter layers 67.

Although not shown in the drawings, these two substrates 10 and 60 have seal patterns formed with sealants or the like along edges to prevent leakage of the liquid crystal layer 80 interposed therebetween. Upper and lower alignment layers (not shown) are further formed at the boundary between the substrates 10 and 60 and the liquid crystal layer 30 to provide reliability in the initial molecular alignment direction of the liquid crystal. At least one outer surface is provided with a polarizing plate (not shown).

In addition, a back-light is provided on the outer surface of the array substrate 10 to supply light, and the on / off signal of the thin film transistor Tr is provided to the gate line 13. When the scan signal is sequentially applied and the image signal of the data line 30 is transferred to the pixel electrode 47 of the selected pixel region P, a vertical electric field is formed between the pixel electrode 47 and the upper common electrode 70. The generated liquid crystal molecules in the liquid crystal layer are driven by the vertical electric field, and various images can be displayed by the change in the transmittance of light.

In the liquid crystal display device having such a structure, the structure of the array substrate as the lower substrate and the manufacturing method thereof will be described in more detail.

FIG. 2 is an enlarged plan view of one pixel area in an array substrate of a conventional liquid crystal display, and FIG. 3 is a cross-sectional view of a portion taken along the cutting line III-III of FIG. 2.

As shown in the drawing, the gate wiring 13 and the data wiring 30 intersect with the gate insulating film 20 therebetween on the insulating substrate 10 to define the pixel region P. Each pixel region P is connected to the two wires 13 and 30 simultaneously and is spaced apart from the gate electrode 15, the gate insulating film 20, and the semiconductor layer 27 from the surface of the substrate 10. And a thin film transistor Tr constituted by the drain electrodes 33 and 36.

In addition, through the drain contact hole 43 over the passivation layer 40 including the thin film transistor Tr and including a drain contact hole 43 exposing a portion of the drain electrode 36 on the front surface thereof. In contact with the drain electrode 36, a pixel electrode 47 is formed for each pixel region P. In FIG.

  In the array substrate 10 having the above structure, the overlapping portion of the pixel electrode 47 and the drain electrode 36 in the pixel region P is described along the edge of the drain electrode 36. It can be seen that disconnection of the pixel electrode 47 occurs.

This is because the semiconductor layer 27, the source and drain electrodes 33 and 36, and the data line 30 are formed in one mask process through one mask.

The reason why such pixel electrode break occurs will be described through a conventional array substrate manufacturing method.

4A to 4D are cross-sectional views of a pixel area including a switching element of a conventional array substrate for a liquid crystal display device, and are shown only for some process steps.

First, as shown in FIG. 4A, an inorganic insulating material, an amorphous silicon, an impurity amorphous silicon, and a metal material are sequentially stacked on the substrate 10 having the gate electrode 15 and a gate wiring connected thereto. The insulating film 20, the pure amorphous silicon layer 21, the impurity amorphous silicon layer 24, and the metal material layer 28 are formed.

Thereafter, a photoresist is formed on the metal material layer 28 to form a photoresist layer (not shown), and then a mask (not shown) having a transmissive region, a transflective region, and a blocking region is positioned thereon. By exposing and developing the photoresist layer (not shown), the first photoresist pattern 90a having a first thickness and a second thickness having a second thickness thinner than the first thickness are different. The photoresist pattern 90b is formed.

Next, as illustrated in FIG. 4B, the metal material layer (28 of FIG. 4A) exposed to the outside of the first and second photoresist patterns 90a and 90b of FIG. 24A of FIG. 4A and the pure amorphous silicon layer (21 of FIG. 4A) are successively etched to form a metal pattern 29 having the same shape, an impurity amorphous silicon pattern 25 and an active layer 22 of pure amorphous silicon under the same shape. ).

Thereafter, ashing is performed to remove the second photoresist pattern (90b of FIG. 4A) having the second thickness.

Next, as shown in FIG. 4C, the metal pattern exposed to the outside of the first photoresist pattern 90a by dry etching using the first photoresist pattern 90a as an etching mask (see FIG. 4B). 29) and the source and drain electrodes 33 and 36 spaced apart from each other by removing the impurity amorphous silicon pattern (25 in FIG. 4B) below and the same pattern as each of the source and drain electrodes 33 and 36 below. An ohmic contact layer 26 having a shape is formed. In this case, it can be seen that the ends of the source and drain electrodes 33 and 36 coincide with the ends of the ohmic contact layer 26 and the active layer 22 disposed below the source and drain electrodes 33 and 36.

In this case, the metal pattern (29 of FIG. 4B) exposed between the first photoresist pattern 90a and the impurity amorphous silicon pattern (25 of FIG. 4B) underneath the dry etching process may be performed. 4B of FIG. 4 and an impurity amorphous silicon pattern 25 of FIG. 4B are removed, but a part of the gate insulating film 20 exposed to the outside of the metal pattern 29 of FIG. 4B is also removed. The end portion of the electrode 36 is in a state in which the end state of the dry etching process coincides with the active layer 22, the impurity amorphous silicon pattern (25 in FIG. 4B), the metal pattern (29 in FIG. 4B), and the first photo. Since the resist pattern 90a is formed, a very high step is formed from the exposed surface of the gate insulating film 20, so that the active layer 22 and the gate insulating film 20 meet under the influence of the high step. Corners LA is emanating other is undercut (under cut) occurs as in the gate insulating film 20 over phenomenon that the dry etching is concentrated in part caused the gate insulating film 20 is etched to the bottom of the active layer 22. In this case, although an under cut has occurred only in the lower portion of the drain electrode 26, the under cut also occurs in the lower end of the source electrode 33. However, since the pixel electrode is not formed at the end of the source electrode 33, it is not shown in the drawing because it is not a structural problem.

Next, as shown in FIG. 4D, when the inorganic insulating material is deposited on the entire surface of the source and drain electrodes 33 and 36 and the exposed gate insulating film 20 in this state, the protective layer 40 is formed. The protective layer 40 is formed in the same shape along the portion where the under cut has occurred, that is, the form in which the under cut has occurred, and the transparent conductive material layer over the protective layer 40 in this state. When 46 is deposited, the transparent conductive material is formed in a state where the step between the semiconductor layer 27 and the source and drain electrodes 33 and 36 formed so as to coincide with the gate insulating film 20 thereon is very high. Deposition of the material layer 46 causes breakage of the transparent conductive material layer 46 in the portion of the protective layer 40 where the under cut has occurred. This is because the thickness of the semiconductor layer 27 and the drain electrode 36 which are sequentially formed in the state where the ends thereof coincide with the upper portion from the gate insulating film 20 is very thick. Since the deposition rate is substantially perpendicular to the deposition rate, the deposition rate decreases during deposition, and the deposition thickness becomes thin. As a result, a break occurs in a portion where the under cut occurs.

In order to solve the above problems, in the present invention, while manufacturing the array substrate for a liquid crystal display device by a four-mask process, the undercut by dry etching does not occur in the portion where the gate insulating film and the semiconductor layer meet, It is an object of the present invention to provide a manufacturing method which can suppress the occurrence of breakage between an electrode and a drain electrode.

According to another aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display device, the method including: forming a gate electrode on the substrate; Forming a gate insulating film on the gate electrode; Forming a pure amorphous silicon layer, an impurity amorphous silicon layer, and a metal material layer on the gate insulating layer; Forming a first photoresist pattern having a first thickness and a second photoresist pattern having a second thickness thinner than the first thickness over the metal material layer; The metal material layer exposed to the outside of the first and second photoresist patterns, an impurity amorphous silicon layer and a pure amorphous silicon layer below the portion are etched to form an active layer, an impurity amorphous pattern, and a metal pattern on the gate insulating layer. Making a step; Exposing the region corresponding to the gate electrode and the metal pattern corresponding to a predetermined width at one end thereof by removing the second photoresist pattern; Forming a source and a drain electrode spaced apart from each other by etching the exposed metal pattern and an impurity amorphous silicon layer thereunder, and simultaneously exposing an active layer having a predetermined width outside the end of the drain electrode; Forming a protective layer having a drain contact hole exposing the drain electrode on a front surface of the source and drain electrodes and the exposed active layer; Forming a pixel electrode contacting the drain electrode through the drain contact hole on the passivation layer.

In this case, the end of the drain electrode and the end of the active layer is formed to be spaced apart from each other, wherein the end of the drain electrode and the end of the active layer is formed to be spaced apart to reduce the height of the stepped portion of the drain electrode It is characterized in that the break of the pixel electrode at the end.

The forming of the gate electrode may further include forming a gate wiring connected to the gate electrode, and forming the source and drain electrodes may define a pixel region crossing the gate wiring and define the source. The method may further include forming a data line connected to the electrode.

In addition, forming a first photoresist pattern having a first thickness on the metal material layer and a second photoresist pattern having a second thickness thinner than the first thickness may include forming a photoresist layer on the metal material layer. Making a step; A transflective region corresponds to a portion corresponding to the gate electrode and a predetermined width of the drain electrode end portion over the photoresist layer, and a transmissive region is formed for the drain electrode and the source electrode except for the predetermined width of the drain electrode end portion thereof. Positioning and exposing the mask to areas other than the blocking area; And developing the exposed photoresist layer.

In addition, the step of exposing the active layer to the outside of the drain electrode end by a predetermined width is characterized in that the predetermined width of the exposed active layer is 3㎛ to 10㎛.

An array substrate for a liquid crystal display device according to the present invention comprises: a gate electrode on the substrate; A gate insulating film formed over the gate electrode; An active layer formed on the gate insulating layer to cover the gate electrode; An ohmic contact layer stacked on the active layer with the gate electrode spaced apart from each other and exposing a predetermined width of one end of the active layer; Source and drain electrodes spaced apart from each other over the ohmic contact layers spaced apart from each other, and the ends of the ohmic contact layers formed to coincide with each other; A protective layer formed on the source and drain electrodes and having a drain contact hole exposing as part of the drain electrode; And a pixel electrode contacting the drain electrode through the drain contact hole on the passivation layer.

In this case, the gate wiring is connected to the gate electrode and extends in one direction; And a data line connected to the source electrode over the gate insulating layer and crossing the gate line to define a pixel area.

In addition, the predetermined width of the active layer exposed to the outside of the ohmic contact layer under the drain electrode is preferably 3 μm to 10 μm.

Hereinafter, preferred embodiments according to the present invention will be described with reference to the drawings.

5A through 5H are cross-sectional views illustrating manufacturing processes of one pixel area including a thin film transistor, which is a switching element of an array substrate for a liquid crystal display according to the present invention.

First, as shown in FIG. 5A, a first metal material is formed on the insulating substrate 110 to form a first metal layer (not shown), and then a photoresist layer is formed by coating a photoresist over the first metal layer. Formation, exposure of the photoresist layer using a mask, formation of a photoresist pattern (not shown) through development of the exposed photoresist layer, and the first metal layer (not shown) exposed to the outside of the photoresist pattern (not shown) ) And branching from the gate wiring (not shown) and the gate wiring (not shown) by performing a first mask process including an etching process and a strip of the photoresist pattern (not shown). A gate electrode 115 is formed in the switching region TrA in the pixel region P.

Next, as shown in FIG. 5B, an inorganic insulating material, such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx), is formed on the entire surface of the substrate 110 on which the gate wiring (not shown) and the gate electrode 115 are formed. By depositing, the gate insulating film 120 is formed.

Subsequently, pure amorphous silicon, impurity amorphous silicon, and a second metal material, for example, molybdenum (Mo), are sequentially deposited on the gate insulating layer 120 to sequentially form the pure amorphous silicon layer 121 and the impurity amorphous silicon layer 124. And the second metal material layer 128 is formed.

Next, as shown in FIG. 5C, the photoresist is formed on the second metal material layer 124 to form the photoresist layer 190, and the light transmitting area TA transmits 100% of light and light. After placing the mask 195 including the blocking area BA that blocks 100% and the transflective area HTA, which can control the amount of light transmission between 0% and 100%, over the photoresist layer 190, Exposure through the mask 195 is performed.

In this case, when the photoresist on which the photoresist layer 190 is formed receives a light, and is a negative type remaining during development, the data line on the array substrate 110 and the switching region TrA Corresponding to the portion where the source and drain electrodes (not shown) are to be formed, the transmissive region TA of the mask 191 may overlap the region of the switching region TrA with the gate electrode 115 and later the drain electrode. The mask 195 is positioned such that the transflective area HTA of the mask 195 corresponds to the predetermined width of the outer portion of the mask 195, and the blocking area BA of the mask 195 corresponds to the other areas. After exposing, exposure is performed.

In this case, when the photoresist is a positive tape, the positions corresponding to the array substrate 110 of the transmission area TA and the blocking area BA on the mask 195 are changed to correspond to each other. The exposure results in the same results as those using the negative type photoresist.

Next, as shown in FIG. 5D, after exposing through the mask 195 positioned as described above, and developing the exposed photoresist layer 190 (FIG. 5C), a transmission region of the mask 195 is developed. A first photoresist pattern 190a having a thick first thickness is formed in a region corresponding to TA, and a portion corresponding to the transflective region HTA of the mask 195 is thinner than the first thickness. A second photoresist pattern 190b having two thicknesses is formed. In addition, all of the photoresist layers 190 of FIG. 5C corresponding to the blocking area BA of the mask 195 are removed to expose the lower second metal material layer 128 of FIG. 5C.

Next, a second metal material layer (128 in FIG. 5C), an impurity amorphous silicon layer (124 in FIG. 5C) and a pure amorphous silicon layer exposed to the outside of the first and second photoresist patterns 190a and 190b. By sequentially etching 121 of FIG. 5C, a data line (not shown) defining each pixel area P is formed on the gate insulating layer 120 to intersect the gate line (not shown), and at the same time, a switching region. In TrA, an active layer 122 of pure amorphous silicon, an ohmic contact layer 125 in a state of being connected as impurity amorphous silicon, and a metal pattern 129 in a state of being connected to the upper part are formed.

Next, as illustrated in FIG. 5E, an ashing process is performed on the substrate 110 formed by the data line (not shown) and the metal pattern 129 to form the photoresist pattern having the second thickness (FIG. 5D). The upper portion of the bottom portion of the metal pattern 129 and the central portion corresponding to the gate electrode 115 are exposed.

At this time, the ashing of the photoresist pattern 190a of the first thickness also becomes thinner, but after the ashing is completed, it still has a predetermined thickness and still remains on the substrate 110. .

Next, as shown in FIG. 5F, the ohmic contact connected to the exposed metal pattern (129 in FIG. 5E) and the lower part by removing the second photoresist pattern (190b in FIG. 5D) by the ashing. The layer (125 in FIG. 5E) is removed by dry etching, so that the source and drain electrodes 133 and 136 spaced apart from each other in the switching region TrA, and the ohmic of impurity amorphous silicon spaced apart from each other below them. The active layer of pure amorphous silicon is formed in the contact region 126 and the channel region ch spaced between the source and drain electrodes 133 and 136 and the region having a predetermined width outside the drain electrode 136. 122). At this time, the predetermined width is preferably 3㎛ to 10㎛. The larger the width of the exposed active layer is, the smaller the opening ratio is, and the smaller the distance between the step portions becomes so narrow that even though the step portions are formed apart from each other, it is as if the material layer formed by deposition thereafter. This is because there is a possibility that breakage may occur because the stepped portion is formed.

In this case, the gate insulating layer 120 that meets the exposed end of the active layer 122 may have the source electrode 133 and the drain electrode 136 spaced apart from each other, and an ohmic of impurity amorphous silicon spaced apart from each other. The gate insulating layer 120 is partially etched at the end SA2 of the exposed active layer 122 due to the effect of dry etching performed to form the contact layer 126, but the etching degree is very high. It becomes a weak level and hardly etched under the active layer 122 so that an under cut is hardly generated or occurs at a very weak level.

This is dry-etched to the metal pattern (129 of FIG. 5E) SA2 made of the metallic material by the exposed metal pattern (129 of FIG. 5E) by removing the second photoresist pattern (190b of FIG. 5D). Etching) The electric field in the device chamber and the etching gas thereby are concentrated, so that the etching is less affected by dry etching around the exposed metal pattern 129 of FIG. 5E. This is because the gate insulating layer 120 at the end SA2 of 129 of FIG. 5E is less affected by the dry etching.

4B and 4C, ends of the metal pattern 29 forming the source and drain electrodes 33 and 36 may be covered by the first photoresist pattern 90a. The stepped with the insulating film 20 is formed so large that when the dry etching proceeds, the side of the step, that is, the ohmic contact layer 25 in the state connected to the active layer 22 formed to match the end An electric field concentration phenomenon occurs in the gate insulating film 20 that meets the side surfaces of the metal pattern 29 and the first photoresist pattern 90a, so that the gate insulating film 20 is more than other areas at the end of the active layer 22. By etching, an under cut is formed on the active layer 22.

However, in the exemplary embodiment of the present invention, before the dry etching is performed, referring to FIG. 5E, a part of the end portion of the metal pattern 129 is exposed and the second photoresist is exposed on the array substrate 110. Since the pattern (190b of FIG. 5D) is removed, the etching of the gate insulating layer 120 of the portion SA2 that meets the end of the metal pattern 129 is almost performed by the dry etching. Since the process does not proceed, the under cut does not occur under the exposed active layer 122.

Accordingly, in the state where such dry etching is completed, as shown in FIG. 5F, the active layer 122 has a predetermined width exposed between the end of the drain electrode 136 and the gate insulating layer 120 as the most characteristic of the present invention. Is formed, the drain electrode 136 and the gate insulating film (unlike the conventional array substrate in which the end of the drain electrode, the ohmic contact layer and the end of the active layer coincide with each other and the step is very high) are formed. The double stepped structure is formed between 120).

That is, the first step SA1 of the drain electrode 136 and the exposed active layer 122 and the second step SA2 between the active layer 122 and the gate insulating layer 120 may be the drain electrode ( 136) The height of the stepped portion is reduced by being formed to be spaced apart from each other by the width of the active layer 122 exposed to the outside.

Therefore, in the transparent conductive material layer formed by deposition in a later process. Due to the deposition characteristics, when the thickness of the stepped parts SA1 and SA2 is formed to be thin and has a high step, it is a structure that solves the problem of breakage.

Furthermore, in the related art, the gate insulating film 120 is under cut by the dry etching to form an under cut under the active layer 122. The side of the stepped portion is made thinner, and the protective layer formed by depositing on the upper part of the under cut-generating portion has the same shape as the under cut. The breakage of the transparent conductive material layer formed over the layer occurs, but in the case of the present invention, under cut of the gate insulating layer 120 disposed below the active layer 122 does not occur, and Since the drain electrode 136 and the ohmic contact layer 126 are not formed on the exposed active layer 122, the second stepped portion SA2 at which the exposed end of the active layer 122 forms the gate insulating layer 120. Height of It is not high, and furthermore, an under cut does not occur in the lower portion of the exposed active layer 122, so that a break between the protective layer formed thereon and the transparent conductive material layer formed thereon may not occur. do.

Next, as shown in FIG. 5G, the metal pattern (129 of FIG. 5E) corresponding to the gate electrode 115 and the ohmic contact layer (125 of FIG. 5E) corresponding to the gate electrode 115 are formed by the dry etching. Is removed by stripping the first photoresist pattern (190a in FIG. 5F) remaining on the source and drain electrodes 133 and 136 formed by removing the first and second electrodes 133 and 136. An inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), is deposited on the front surface of the wiring (not shown) to form the protective layer 140 on the front surface.

In this case, the passivation layer 140 may be formed such that the gate insulating layer 120 that meets the end portion of the active layer 122 formed further extending from the end of the drain electrode 136 is hardly etched and has no under cut. Bar and over the source and drain electrodes 133 and 136 and the gate insulating film 120 without under cut (under cut).

In addition, in this case, the protective layer 140 is formed in the drain electrode 136 and the lower active layer 122 has a double step (SA1, SA2) structure in the shape of a staircase bar, It can be seen that there is no part forming a sudden stepped portion.

Subsequently, a new photoresist is formed on the passivation layer 140 to form a photoresist layer, and a mask process is performed to form a third photoresist pattern (not shown) and to expose the third photoresist pattern outside of the third photoresist pattern. By etching the protective layer 140, a drain contact hole 143 exposing a part of the drain electrode 136 is formed.

Next, as shown in FIG. 5H, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is disposed on the protective layer 140 on which the drain contact hole 143 is formed. Deposited on the substrate to form a transparent conductive material layer (not shown) in contact with the drain electrode 136 through the drain contact hole 143.

At this time, the transparent conductive material layer (not shown) is also not under cut (under cut) is formed in the lower protective layer 140, and the stepped portion of the protective layer 140, in particular of the drain electrode 136 Step height at the end portion SA2 is formed to be much reduced compared to the conventional form.

That is, in the first stepped part SA1, the thickness of the drain electrode 136 and the thickness of the ohmic contact layer 126 is the sum of the thicknesses, and the second stepped part SA2 is spaced apart from the active layer 122. Since a step is formed as a thickness of the transparent conductive material layer (not shown) deposited on the side surfaces of the stepped portions SA1 and SA2, the breakage due to the thinning of the transparent conductive material layer is not caused.

Next, a new photoresist is applied onto the transparent conductive material layer (not shown) and a mask process is performed to form a fourth photoresist pattern (not shown), and the fourth photoresist pattern (not shown) is exposed. By etching the transparent conductive material layer (not shown) to form a pixel electrode 147 that is independent for each pixel region P and contacts the drain electrode 136 through the drain contact hole 143. The array substrate 110 is completed.

As described above, in the present invention, an active layer is formed by further extending from the end of the drain electrode so that the end of the drain electrode does not coincide with the end of the active layer under the same while manufacturing the array substrate for the liquid crystal display device by the four mask process. By reducing the step thickness of the protective layer formed on the upper portion, there is an effect that the breakage failure of the pixel electrode formed on the protective layer does not occur.

Further, during the dry etching proceeding to expose the active layer corresponding to the gate electrode, the dray etching is performed while exposing a part of the metal pattern of the portion where the drain electrode is to be formed. There is an effect of preventing the occurrence of the undercut to further prevent the defective disconnection of the pixel electrode.

Claims (10)

Forming a gate electrode on the substrate; Forming a gate insulating film on the gate electrode; Forming a pure amorphous silicon layer, an impurity amorphous silicon layer, and a metal material layer on the gate insulating layer; Forming a first photoresist pattern having a first thickness and a second photoresist pattern having a second thickness thinner than the first thickness over the metal material layer; The metal material layer exposed to the outside of the first and second photoresist patterns, an impurity amorphous silicon layer and a pure amorphous silicon layer below the portion are etched to form an active layer, an impurity amorphous pattern, and a metal pattern on the gate insulating layer. Making a step; Exposing a region corresponding to the gate electrode and a predetermined width of one end of the metal pattern by removing the second photoresist pattern; Forming a source and a drain electrode spaced apart from each other by etching the exposed metal pattern and an impurity amorphous silicon layer thereunder, and simultaneously exposing an active layer having a predetermined width outside the end of the drain electrode; Forming a protective layer having a drain contact hole exposing the drain electrode on a front surface of the source and drain electrodes and the exposed active layer; Forming a pixel electrode contacting the drain electrode through the drain contact hole on the passivation layer; And a plurality of pixel electrodes formed on the substrate. The method of claim 1, And an end of the drain electrode and an end of the active layer are spaced apart from each other. The method of claim 2, And forming a gap between the end of the drain electrode and the end of the active layer to reduce the height of the stepped portion to prevent the pixel electrode from being cut off at the end of the drain electrode. The method of claim 1, Forming the gate electrode And forming a gate wiring connected to the gate electrode. The method of claim 4, wherein Forming the source and drain electrodes And defining a pixel area crossing the gate line and forming a data line connected to the source electrode. The method of claim 1, Forming a first photoresist pattern having a first thickness and a second photoresist pattern having a second thickness thinner than the first thickness above the metal material layer, Forming a photoresist layer over the metal material layer; A transflective region is formed on the photoresist layer to correspond to the portion corresponding to the gate electrode and a predetermined width outside the end of the drain electrode, and a transmissive region is formed for the drain electrode and the source electrode except for the predetermined width outside the drain electrode end. Positioning and exposing the mask so that the blocking area corresponds to the other areas; Developing the exposed photoresist layer Method of manufacturing an array substrate for a liquid crystal display device further comprising. The method of claim 1, Exposing the active layer to the outside of the drain electrode end by a predetermined width And a predetermined width of the exposed active layer is set to 3 µm to 10 µm. delete delete delete

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