KR101294691B1 - Array substrate for liquid crystal display device and method of fabricating the same - Google Patents

Abstract

The present invention provides a gate wiring having a double layer structure extending in one direction on a defined substrate of a pixel region, and a gate electrode branched from the gate wiring; A pixel electrode formed in the pixel region on the substrate; A gate insulating film formed over the gate wiring and the gate electrode and the pixel electrode; A data line formed over the gate insulating layer to define the pixel area crossing the gate line; Source and drain electrodes spaced apart from each other on the gate electrode; An ohmic contact layer formed on each of the source and drain electrodes; An active layer formed over the ohmic contact layer and spaced apart from the source and drain electrodes; A protective layer having a contact hole for simultaneously exposing an ohmic contact layer on the drain electrode and a portion of the pixel electrode over the active layer; An array substrate for a liquid crystal display device including a metal pattern formed by electrically connecting the drain electrode and the pixel electrode in the contact hole and a manufacturing method thereof are provided.

        Mask reduction, array board, 4 masks, wave noise, process simplicity

Description

Array substrate for liquid crystal display device and method of fabricating the same

1 is an exploded perspective view of a general liquid crystal display device.

2 is a cross-sectional view of one pixel area including a thin film transistor of an array substrate of a liquid crystal display device manufactured by a conventional five mask process.

3 is a cross-sectional view of one pixel region including a thin film transistor of an array substrate for a liquid crystal display device manufactured by a conventional four mask process.

4A to 4D are plan views of manufacturing process steps (mask processes) for one pixel region including a thin film transistor of an array substrate for a liquid crystal display device according to the present invention.

5A to 5H are cross-sectional views of the manufacturing process of the portion (switching region) cut along the cutting line V-V in FIGS. 4A to 4D.

Description of the Related Art

201: substrate 203a, 203b: first and second transparent conductive patterns

205a, 205b; First and Second Metal Patterns 208: Gate Electrodes

210: gate wiring 215: pixel electrode

220: gate insulating film 225: source electrode

227: drain electrodes 230a, 230b: ohmic contact layer

250: active layer 255: protective layer

257 contact hole 263 metal pattern

P: Pixel Area Tr: Thin Film Transistor

TrA: Switching Area

The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing an array substrate for a liquid crystal display device.

Recently, liquid crystal displays have been spotlighted as next generation advanced display devices having low power consumption, good portability, high technology value, and high added value.

Of these liquid crystal display devices, an active matrix type liquid crystal display device having a thin film transistor, which is a switching device capable of controlling voltage on and off for each pixel, .

In general, an LCD device forms an array substrate and a color filter substrate through an array substrate manufacturing process for forming a thin film transistor and a pixel electrode, and a color filter substrate manufacturing process for forming a color filter and a common electrode, and between the two substrates. It completes through the cell process through liquid crystal in the process.

In more detail, referring to FIG. 1, which is an exploded perspective view of a general liquid crystal display device, as illustrated, the array substrate 10 and the color filter substrate 20 face each other with the liquid crystal layer 30 interposed therebetween. The array substrate 10 of the lower part includes a plurality of gate lines 14 and data lines 16 arranged vertically and horizontally on the upper surface of the transparent substrate 12 to define a plurality of pixel regions P. Thin film transistors T are provided at the intersections of the two wires 14 and 16 so as to correspond one-to-one with the pixel electrodes 18 provided in the pixel regions P. FIG.

In addition, the upper color filter substrate 20 facing the array substrate may cover a non-display area such as the gate line 14, the data line 16, and the thin film transistor T on the rear surface of the transparent substrate 22. Grid-like black matrix 25 is formed so as to border each pixel region P, and the red, green, and blue color filter layers 26 are sequentially arranged to correspond to each pixel region P in the grid. ) Is formed, and a transparent common electrode 28 is provided over the entirety of the black matrix 25 and the red, green, and blue color filter layers 26.

Although not shown in the drawings, these two substrates 10 and 20 are sealed with a sealant or the like along the edges to prevent leakage of the liquid crystal layer 30 interposed therebetween. In the boundary portion of each substrate (10, 20) and the liquid crystal layer 30 is interposed upper and lower alignment layer that provides reliability in the molecular alignment direction of the liquid crystal, and at least one outer surface of each substrate (10, 20) A polarizing plate is provided.

A back-light is provided on the outer surface of the array substrate to supply light. An on / off signal of the thin film transistor T is sequentially scanned by the gate wiring 14, When the image signal of the data line 16 is transferred to the pixel electrode 18 of the selected pixel region P, the liquid crystal molecules therebetween are driven by the vertical electric field therebetween. As a result, It is possible to display branch images.

2 is a cross-sectional view of one pixel region in the array substrate of the above-described liquid crystal display device including a thin film transistor.

Although not shown in the drawing, a gate electrode 60 is formed in a plurality of pixel regions P defined by intersecting a plurality of gate wirings (not shown) and data wirings (not shown) on the substrate 59, A gate insulating layer 68 is formed on the entire surface of the gate electrode 60 and a semiconductor layer 70 composed of an island-shaped active layer 70a and an ohmic contact layer 70b is sequentially formed thereon.

A source electrode 76 and a drain electrode 78 facing each other at a predetermined distance from the source electrode 76 are formed on the ohmic contact layer 70b. At this time, the source and drain electrodes 76 and 78 (not shown) are formed by patterning the semiconductor layer 70 through a single mask process and then forming a metal layer and then forming another source and drain electrodes 76 and 78 through another mask process Are formed so as to extend so as to sufficiently cover the edge portions of the semiconductor layer 70.

In addition, a protective layer 86 including a drain contact hole 80 exposing the drain electrode 78 is formed over the source and drain electrodes 76 and 78 and the exposed active layer 70a. The pixel electrode 88 is formed on the passivation layer 86 independently of each pixel region P and contacts the drain electrode 78 through the drain contact hole 80.

At this time, the wiring and the electrode pattern of the above-described array substrate for a liquid crystal display device are formed by a photo-etching process using a photoresist as a photosensitive material.

In the photolithography process, a photoresist is applied on a metal material layer, an insulating material layer or a semiconductor material layer, a mask having a predetermined pattern is disposed and exposed, a photoresist layer is developed by developing an exposed photoresist layer. And forming a wiring and an electrode, a contact hole or a semiconductor layer by etching the metal material layer, the insulating material layer or the semiconductor material layer using the photoresist pattern as a mask.

Since the number of processes is determined by the number of masks in the photolithography process, it will be referred to as a mask process.

Referring to the manufacturing process of the array substrate for a liquid crystal display device having the above-described cross-sectional structure, after depositing a first metal material on the substrate 59, the gate electrode 60 and the gate wiring (by the first mask process) are deposited. The first insulating material, pure amorphous silicon (a-Si), and impurity amorphous silicon (n + a-Si) are successively deposited, and then the first insulating material is transferred to the gate insulating film 68. The pure amorphous silicon layer and the impurity amorphous silicon layer are formed as the active layer 70a and the ohmic contact layer 70b at positions covering the gate electrode 60 by the second mask process to form the semiconductor layer 70. Configure.

Next, after the deposition of the second metal material, source and drain electrodes 76 and 78 spaced apart from each other by a third mask process on the data line 73 and the semiconductor layer 70 are formed. In this step, the ohmic contact layer 70b in the spaced intervals is removed using the source and drain electrodes 76 and 78 as a mask, and the active layer 70a, which is a lower layer thereof, is exposed to form a channel. The gate electrode 60, the semiconductor layer 70, the source and drain electrodes 76 and 78 form a thin film transistor Tr.

Next, after the deposition of the second insulating material, a protective layer 86 having a drain contact hole 80 exposing a part of the drain electrode 78 is formed by a fourth mask process, and then the protective layer 86 is formed. The pixel electrode 88 is formed by depositing a transparent conductive material on the substrate) and patterning the same by a fifth mask process.

As described above, in the conventional array process for liquid crystal display devices, an array substrate is usually manufactured by a five mask process.

However, the mask process requires equipment for each deposition, exposure, development, and etching process, and the process cost is high due to repeated physical and chemical processes, and there is a high possibility of damaging other devices during the process, which lowers the process efficiency. There is this.

To solve this problem, as shown in FIG. 3, which is a cross-sectional view of one pixel region including a thin film transistor of an array substrate for a liquid crystal display device manufactured by a conventional four mask process, a gate electrode on a substrate 101 is provided. 105 and a gate wiring (not shown) are formed thereon, and the gate insulating material layer, the amorphous silicon material layer, the impurity amorphous material layer, and the metal material layer are successively formed, and patterned using diffraction exposure to pure amorphous. The semiconductor layer 120 including the active layer of silicon and the ohmic contact layer 120b of impurity amorphous silicon, the source and drain electrodes 130 and 135 and the data line 127 are formed by one mask process. A method of manufacturing the array substrate 101 for a liquid crystal display device through a meeting mask process has been proposed.

However, in order to reduce one mask process, the liquid crystal display manufactured by the above-described four mask process sequentially stacks a pure amorphous silicon layer, an impurity amorphous silicon layer, and a metal layer, applies a photoresist, and then performs diffraction exposure. The semiconductor layer 120 including the source and drain electrodes 130 and 135 and the active layer 120a and the ohmic contact layer 120b is formed by one mask process, that is, the source and drain electrodes. (130, 135) by extending to the outside of both ends to form a structure to expose the active layer 121 other than the active layer 120 that forms a channel exposed to the outside of the source and drain electrodes (130, 135) When the active layer 121 exposed to the outside of the ends of the source and drain electrodes 130 and 135 is driven using the array substrate 101 having such a structure, Excited by light incident from a backlight (not shown), etc. provided in the device, or from external light, it affects the data wiring 127 for switching the thin film transistor or inputting a data signal, thereby causing stains on the screen. It causes a problem of wavy noise.

In order to solve the above problems, the present invention aims to simplify the manufacturing process and cost reduction compared to the progress of the five mask process by proceeding to the four mask process.

In addition, the active layer is not exposed outside the ends of the source and drain electrodes, and furthermore, the semiconductor pattern is prevented from being formed under the data line, thereby preventing the wavy noise caused by the photo current. do.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display device, wherein a gate layer and a gate electrode having a double layer structure extending in one direction by performing a first mask process on a substrate having a pixel region defined therein, and the pixel Forming a pixel electrode of a single layer in the region; Forming a gate insulating film over the gate wiring and over the gate electrode and the pixel electrode; A second mask process is performed on the gate insulating layer to form a data line defining the pixel region crossing the gate line, and source and drain electrodes spaced apart from each other on the gate electrode; Forming a ohmic contact layer; Forming an active layer by performing a third mask process on the ohmic contact layer and on an area between the source and drain electrodes; Performing a fourth mask process on the entire surface of the active layer to form a protective layer having a contact hole exposing the ohmic contact layer and the pixel electrode on the drain electrode at the same time; Forming a metal layer by applying a liquid metal material onto the protective layer having the contact hole; Dry etching the metal layer to form a metal pattern connecting the drain electrode and the pixel electrode to the inside of the contact hole.

In this case, the step of forming the pixel electrode in the gate wiring and the gate electrode of the double-layer structure and the pixel region by performing the first mask process, by sequentially depositing a transparent conductive material and a first metal material on the substrate transparent transparent material Forming a layer and a first metal layer; Forming a first photoresist pattern of a first thickness and a second photoresist pattern of a second thickness thicker than the first thickness above the first metal layer; Etching the first metal layer and the transparent conductive material layer exposed outside the first and second photoresist patterns to form the gate wiring and the gate electrode having a double layer structure, and forming a pixel pattern having a double layer structure in the pixel region; ; Removing the second photoresist pattern; Etching the first metal layer exposed to the outside of the first photoresist pattern; Removing the first photoresist pattern.

The forming of the data line and the source and drain electrodes spaced apart from each other on the gate electrode and the ohmic contact layer formed on the source and drain electrodes at the same time may overlap the pixel electrode. The method may further include forming common wiring spaced apart from the data wiring by a predetermined interval.

The drain electrode may be formed such that an end other than an end facing the source electrode is spaced apart from the pixel electrode. The contact hole may be formed by removing a gate insulating layer formed in a space between the drain electrode and the pixel electrode. Characterized by exposing the surface of the substrate.

In addition, the metal layer is characterized in that the silver (Ag) metal based on the liquid nanoparticles (nano particles).

An array substrate for a liquid crystal display device according to the present invention includes a gate wiring having a double layer structure extending in one direction on a defined substrate of a pixel region, and a gate electrode branched from the gate wiring; A pixel electrode formed in the pixel region on the substrate; A gate insulating film formed over the gate wiring and the gate electrode and the pixel electrode; A data line formed over the gate insulating layer to define the pixel area crossing the gate line; Source and drain electrodes spaced apart from each other on the gate electrode; An ohmic contact layer formed on each of the source and drain electrodes; An active layer formed over the ohmic contact layer and spaced apart from the source and drain electrodes; A protective layer having a contact hole for simultaneously exposing an ohmic contact layer on the drain electrode and a portion of the pixel electrode over the active layer; And a metal pattern formed in the contact hole to electrically connect the drain electrode and the pixel electrode.

At this time, the gate layer and the gate electrode of the double layer structure is characterized in that the lower layer is made of the same material as the material forming the pixel electrode.

The drain electrode and the pixel electrode may be formed to be spaced apart from each other. In this case, the contact hole may be formed corresponding to the separation region of the drain electrode and the pixel electrode to expose a substrate in the separation region. do.

The metal pattern may be made of silver (Ag) metal, and the ohmic contact layer formed on the source and drain electrodes may have the same shape as the source and drain electrodes.

In addition, an impurity amorphous pattern having the same shape as that of the ohmic contact layer may be further formed on the data line.

In addition, the gate insulating layer may further include a common wiring spaced apart from the data line and parallel to the data line and overlapping the pixel electrode.

Hereinafter, preferred embodiments according to the present invention will be described with reference to the drawings.

4A to 4D are plan views of manufacturing process steps (mask processes) of one pixel region P including a thin film transistor of an array substrate for a liquid crystal display device according to the present invention, and FIGS. 5A to 5H are FIGS. It is sectional drawing of the manufacturing process about the part (switching area | region) cut | disconnected along cut line VV.

In this case, for convenience of description, a portion in which the thin film transistor which is the switching element in each pixel region P is formed is defined as a switching region TrA.

First, as shown in FIGS. 4A and 5A, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the transparent insulating substrate 201 on the front surface. The transparent conductive material layer 203 is formed.

Next, a first metal material having low resistance on the transparent conductive material layer 203, for example, aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo), and chromium (Cr). The first metal layer 205 is formed by depositing one of the materials.

Thereafter, a photoresist is applied on the first metal layer 205 to form a photoresist layer 281. In this case, in the present invention, the photoresist constituting the photoresist layer 281 will be described as an example of using a positive type having a characteristic in which light-received portions are removed during development. However, in the case where the photoresist layer is formed of a negative type photoresist in which the lighted portion remains during development, the positions of the transmission region and the blocking region in the exposure mask for diffraction exposure or halftone exposure used in the present invention are used. The same result can be obtained by using the mask of the form changed to.

Next, the light transmitting area TA and the blocking area BA and the plurality of slits are formed on the substrate 201 on which the photoresist layer 281 is formed, or the light is compared with the light transmitting area TA. An exposure mask 291 including a semi-transmissive area (HTA) configured to control the amount of light passing through is further provided with a plurality of coating films to reduce transmission, and exposure is performed therethrough.

In this case, the amount of light transmitted by the transflective area HTA of the exposure mask 291 is less than the amount of light of the transmissive area TA, so that in the case of the photoresist layer 281 corresponding to the portion, the light is completely When developing by not reacting, a photoresist pattern having a thickness thinner than that corresponding to the transmission area (negative type) or the blocking area (positive type) is formed. This is called halftone exposure.

In the present invention, the blocking area BA of the exposure mask 291 corresponds to the portion where the gate wiring is to be formed and the portion where the gate electrode is to be formed in the pixel region P, and the pixel region ( After the exposure mask 291 is positioned so that the transflective area HTA corresponds to the portion where the pixel electrode is to be formed in P) and the transmissive area TA corresponds to the other area, the exposure mask 291 is exposed. Is carried out.

Next, as shown in FIGS. 4A and 5B, when a developing process of exposing the exposed photoresist layer (281 of FIG. 5A) to a developer is performed, a first photoresist pattern 281a having a first thickness t1 is performed. ) And a second photoresist pattern 281b having a second thickness t2 that is thinner than the first thickness t1.

Thereafter, the first metal layer (203 of FIG. 5A) and the transparent conductive material layer (205 of FIG. 5A) exposed to the outside of the first and second photoresist patterns 281a and 281b are etched collectively or continuously. A gate electrode 208 having a double layer structure of a first transparent conductive pattern 203a and a first metal pattern 205a on the substrate 201, connected to the gate electrode 208, and a second transparent conductive pattern 203b and a second metal pattern A gate wiring 210 having a double layer structure of 205b is formed, and at the same time, the pixel pattern of the double layer structure of the third transparent conductive pattern 203c and the third metal pattern 205c corresponds to each pixel region P. 212).

Next, as shown in FIGS. 4A and 5C, the pixel pattern (212 of FIG. 5B) is exposed by removing the second photoresist pattern (281b of FIG. 5B) by ashing.

Subsequently, the exposed pixel pattern (212 of FIG. 5B) is etched to remove the third metal pattern (205c of FIG. 5B) forming the upper layer by etching to remove the pixel pattern having a single layer structure of a transparent conductive material. 212 of FIG. 5B is formed. In this case, the pixel pattern (212 of FIG. 5B) made of a transparent conductive material in each pixel region P forms a pixel electrode 215 (first mask process).

Next, as shown in FIGS. 4B and 5D, the first photoresist pattern remaining on the gate wiring 210 and the gate electrode 208 by ashing or stripping (see FIG. 5D). 281a) is removed.

Subsequently, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the entire surface of the exposed gate wiring 210, the gate electrode 208, and the pixel electrode 215. ) To the front. Subsequently, a second metal material, for example, molybdenum (Mo) or chromium (Cr), is deposited on the gate insulating layer 220 in succession to form a second metal layer (not shown), and the impurity amorphous silicon is continuously deposited thereon. As a result, an impurity amorphous silicon layer (not shown) is formed.

Next, the impurity amorphous silicon layer (not shown) and the second metal layer (not shown) include a series of unit processes of applying a photoresist, exposing and developing using an exposure mask, and etching (dry etching in this step). By performing a second mask process, source and drain electrodes 225 and 227 spaced apart from each other on the gate electrode 208 are formed in the switching region TrA, and are connected to the source electrode 225 at the same time. A data line (not shown) defining the pixel area P is formed to cross the gate line 210. In this case, ohmic contact layers 230a and 230b made of impurity amorphous silicon are formed on the source and drain electrodes 225 and 227 spaced apart from each other, in the same form as the source and drain electrodes 225 and 227. The impurity silicon pattern (not shown) is also formed on the wiring line 240 (in FIG. 4B).

In addition, a common wiring (243 in FIG. 4B) is also formed in parallel with the data wiring (240 in FIG. 4B) extending by a predetermined interval by the same process. At this time, the common wiring 243 of FIG. 4B partially overlaps the lower pixel electrode 215 so that a part of the overlapping pixel electrode is formed on the first storage electrode (not shown), and the gate insulating layer 220 on the dielectric layer is formed. The storage capacitor StgC is formed by using a portion of the common wiring on the upper side as a second storage electrode (not shown).

Meanwhile, the source and drain electrodes 225 and 227 and the ohmic contact layers 230a and 230b formed thereon are simultaneously etched by anisotropic dry etching, and are formed in the same pattern shape. For the same reason, the impurity amorphous silicon pattern (not shown) formed on the data line 240 (see FIG. 4B) also has the same shape as that of the data line (240 of FIG. 4B) positioned below the common line (FIG. 4B). 243) also has the same cross-sectional structure as the data line 240 (see FIG. 4B).

In addition, as a characteristic part of the present invention in this step, the drain electrode 227 is formed so as not to overlap the pixel electrode 215. The reason will be explained later.

Next, as shown in FIGS. 4C and 5E, pure amorphous silicon is deposited on the entire surface of the ohmic contact layers 230a and 230b and the impurity amorphous silicon pattern (not shown), and the patterning process is performed by performing a third mask process. Islands in contact with the spaced apart ohmic contact layers 230a and 230b on the source and drain electrodes 225 and 227, including spaced apart regions of the source and drain electrodes 225 and 227 of each switching region TrA. To form the active layer 250 of pure amorphous silicon. In this case, the gate electrode 208, the gate insulating layer 220, the source and drain electrodes 225 and 227, the ohmic contact layers 230a and 230b and the active layer 250 stacked from the bottom in the switching region TrA. The thin film transistor (Tr) is a switching element.

Next, as shown in FIGS. 4D and 5F, an organic insulating material such as benzocyclobutene (BCB) or photo acryl is coated on the entire surface of the active layer 250, or an inorganic insulating material may be applied. For example, the protective layer 255 is formed by thickly depositing silicon oxide (SiO ₂ ) or silicon nitride (SiNx). In this case, when the protective layer is formed by applying the organic insulating material, the protective layer is formed to have a thickness of about 1 μm to 2 μm, and the thin film transistor Tr protruding from the other area of the switching region TrA is formed. Since it has a thickness larger than the height, the surface is flat without being affected by the step, so it is not a problem in the subsequent process progress that is characterized by the present invention.

On the other hand, when the protective layer 255 is formed by depositing an inorganic insulating material (in the embodiment of the present invention, the protective layer is formed by depositing an inorganic insulating material as an example), rather than the thickness of the conventional 2000Å to 3000Å It should be thicker and preferably formed to have a thickness of at least 5000 mm 3. The reason will be explained later in the process.

Next, the ohmic contact layer 230b and the drain electrode 227 on the drain electrode 227 are patterned by patterning the protective layer 255 having a relatively thicker thickness, that is, 5000 즉 or more, by performing a fourth mask process. A contact hole 257 is formed to simultaneously expose one end side of the N-side and one end of the pixel electrode 215 formed closest thereto. In this case, since the gate insulating film 220 exists in a portion of the contact hole 257 that does not correspond to the drain electrode 227, the gate insulating film 220 is also removed to remove the ohmic inside the contact hole 257. The contact hole 257 is formed to expose the contact layer 230b, the drain electrode 227, the substrate 201, and the pixel electrode 215.

Next, as shown in FIGS. 4D and 5G, a metal material that can be applied by having a liquid property, for example, a silver (Ag) metal based on nano particles, has the contact hole 257. The metal layer 260 is formed by coating the entire protective layer 255 and firing the same. In this case, the metal layer 260 is formed by the coating to fill the contact hole 257, and the contact hole 257 is thicker than the third thickness t3 formed in another area, that is, the upper portion of the protective layer. The metal layer 260 has a thickness t4 of 4 and is formed.

Next, as shown in FIGS. 4D and 5H, dry etching using plasma is performed on the metal layer (260 of FIG. 5G). In the case of the dry etching, since the entire process proceeds at the same level, the metal layer (260 of FIG. 5G) is etched to the same thickness as time passes from the surface thereof, so that the protective time 255 is appropriately adjusted. The contact hole 257 is finished by completely removing the metal layer (260 of FIG. 5G) formed thereon and ending the dry etching when the metal layer (260 of FIG. 5G) remains for the inside of the contact hole 257. The metal layer 260 of FIG. 5G may be formed more precisely only inside the metal pattern 263.

In this case, the metal pattern 263 electrically connects the side surfaces of the ohmic contact layer 230b and the drain electrode 227 with the pixel electrode 210.

In the present invention, in the forming of the source and drain electrodes 225 and 227, the drain electrode 227 and the pixel electrode 215 are formed so as not to overlap each other in the contact hole 257. In order to increase the depth of the contact hole 257 by exposing the surface, the reason why the thickness of the protective layer 250 is thicker than in the conventional forming of the protective layer 255 is also greater. This is to deeply form the depth of the tab hole 257.

In addition, the reason for forming the depth of the contact hole 257 deeply is due to the characteristics of the present invention by applying a liquid metal to form a metal layer (260 of FIG. 5G) and removing it by dry etching. The contact hole 257 If the depth is not deeply formed, the thickness of the metal layer (260 of FIG. 5G) formed on the contact hole 257 and the silver (Ag) metal layer (260 of FIG. 5G) formed on the protective layer 255 (FIG. This is because the metal layers (260 of FIG. 5G) may be etched even inside the contact hole 257 due to the etching error of dry etching since tg and t4 of 5g do not show much difference.

Therefore, the contact hole 257 is formed to form a metal layer (260 of FIG. 5G) having a thickness difference (t 4 -t 3> thickness change due to an error of dry etching) of the etching thickness difference due to the dry etching. It is because it is desirable to form as deep as possible.

As such, by reducing the number of masks used in comparison with the manufacturing method completed by the five mask process by the method of manufacturing the array mask for liquid crystal display device of the four masks according to the present invention, the process efficiency is increased, and the liquid crystal display is simplified due to the process simplification. There is an effect of reducing the manufacturing cost of the array substrate for the device.

In addition, since the data layer including the active layer and the source and drain electrodes is formed by dualization through different mask processes, image quality such as wavy noise due to the active layer exposed to the outside of the source and drain electrodes is generated. There is an effect that can prevent the defect.

Claims (14)

Forming a gate layer and a gate electrode having a double layer structure extending in one direction by performing a first mask process on a substrate on which the pixel region is defined, and forming a single layer pixel electrode in the pixel region; Forming a gate insulating film over the gate wiring and over the gate electrode and the pixel electrode; A second mask process is performed on the gate insulating layer to form a data line defining the pixel region crossing the gate line, and source and drain electrodes spaced apart from each other on the gate electrode; Forming a ohmic contact layer; Forming an active layer by performing a third mask process on the ohmic contact layer and on an area between the source and drain electrodes; Performing a fourth mask process on the entire surface of the active layer to form a protective layer having a contact hole exposing the ohmic contact layer and the pixel electrode on the drain electrode at the same time; Forming a metal layer by applying a liquid metal material onto the protective layer having the contact hole; Dry etching the metal layer to form a metal pattern connecting the drain electrode and the pixel electrode in the contact hole And a plurality of pixel electrodes formed on the substrate. The method of claim 1, The first mask process may be performed to form a gate wiring and a gate electrode having a double layer structure and a pixel electrode in the pixel region. Sequentially depositing a transparent conductive material and a first metal material on the substrate to form a transparent conductive material layer and a first metal layer; Forming a first photoresist pattern of a first thickness and a second photoresist pattern of a second thickness thicker than the first thickness above the first metal layer; Etching the first metal layer and the transparent conductive material layer exposed outside the first and second photoresist patterns to form the gate wiring and the gate electrode having a double layer structure, and forming a pixel pattern having a double layer structure in the pixel region; ; Removing the first photoresist pattern; Etching the first metal layer exposed to the outside of the second photoresist pattern; Removing the second photoresist pattern And a plurality of pixel electrodes formed on the substrate. The method of claim 1, Forming a data line on the gate insulating layer and a source and drain electrode spaced apart from each other on the gate electrode, and simultaneously forming an ohmic contact layer on the source and drain electrodes; And forming a common line overlapping the pixel electrode and spaced apart from the data line by a predetermined interval. The method of claim 1, And the drain electrode is formed such that an end other than an end facing the source electrode is spaced apart from the pixel electrode. 5. The method of claim 4, And wherein the contact hole is formed by exposing a surface of the substrate by removing a gate insulating layer formed between the drain electrode and the pixel electrode. The method of claim 1, The metal layer is a manufacturing method of an array substrate for a liquid crystal display device, characterized in that the silver (Ag) metal based on the liquid nanoparticles (nano particles). delete delete delete delete delete delete delete delete

Images