KR100623977B1 - MANUFACTURING METHOD of THIN FILM TRANSISTOR SUBSTRATE FOR LIQUID CRYSTAL DISPLAY - Google Patents

Abstract

First, aluminum-based metals are stacked, and first, a horizontal gate wiring including a gate line, a gate electrode, and a gate pad and a vertical auxiliary data line are formed on a substrate by patterning using a mask, and a gate insulating film, a semiconductor layer, The photolithography process using a second mask that can sequentially stack resistive contact layers and partially control the light transmission is performed, and a gate insulating layer pattern having a contact hole that exposes the gate pad and the auxiliary data line, and a semiconductor layer pattern on the gate electrode. And a resistive contact layer pattern. Subsequently, the first material is stacked and patterned to cross the gate line, and is connected to the gate pad through a contact hole and a data line including a data line, a source electrode, a drain electrode, and a data pad connected to the auxiliary data line through the contact hole. The auxiliary gate pad is formed. Subsequently, the protective film is stacked and patterned to form contact holes that expose the drain electrode, the gate pad, and the data pad, respectively. Subsequently, ITO is stacked and patterned to form a pixel electrode, a second auxiliary gate pad, and an auxiliary data pad connected to the drain electrode, the first auxiliary gate pad, and the data pad, respectively.

Aluminum, transmittance, photoresist, ITO

Description

The manufacturing method of the thin film transistor substrate for liquid crystal display devices {MANUFACTURING METHOD of THIN FILM TRANSISTOR SUBSTRATE FOR LIQUID CRYSTAL DISPLAY}

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor unit and the pixel unit in which the thin film transistor substrate illustrated in FIG. 1 is cut along the line II-II;

3 is a cross-sectional view of the gate pad part and the data pad part of the thin film transistor substrate illustrated in FIG. 1 taken along a III-III line.

FIG. 4 is a cross-sectional view of the data line part of the thin film transistor substrate of FIG. 1 taken along line IV-IV.

5A, 6A, 8A, and 9A are layout views of thin film transistor substrates sequentially shown according to manufacturing procedures in an intermediate process of manufacturing according to an embodiment of the present invention;

5B, 6B and 7A, 8B and 9B are cross-sectional views taken along the lines Vb-Vb ', VIb-VIb', VIIIb-VIIIb 'and IXb-IXb' in FIGS. 5A, 6A, 8A and 9A, respectively. ,

5C, 6C, 7B, 8C, and 9C are cross-sectional views taken along the lines Vc-Vc ', VIc-VIc', VIIIc-VIIIc ', and IXc-IXc' in FIGS. 5A, 6A, 8A, and 9A, respectively;

5D, 6D, 7C, 8D, and 9D are cross-sectional views taken along the lines Vd-Vd ', VId-VId', VIIId-VIIId ', and IXd and IXd' in FIGS. 5A, 6A, 8A, and 9A, respectively.

The present invention relates to a thin film transistor substrate for a liquid crystal display device and a manufacturing method thereof.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. By controlling the amount of light transmitted.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on each of two substrates and switching a voltage applied to the electrode is generally used. The thin film transistor is generally formed on one of two substrates.

The substrate on which the thin film transistor is formed is generally manufactured through a photolithography process using a mask. At this time, it is preferable to reduce the number of masks in order to reduce the production cost.

On the other hand, in order to prevent signal delay, the wiring is generally made of a material such as aluminum (Al) or aluminum alloy (Al alloy) having a low resistance. However, in the case of using indium tin oxide (ITO) in the pad part to secure the pad part as in a liquid crystal display device, aluminum or aluminum alloy and ITO have poor contact characteristics, so that the aluminum or aluminum alloy is interposed with another metal. Should be removed. At this time, since the interposed metal should not be etched with aluminum or aluminum alloy at one time, there is a problem in that the process is complicated by the addition of a photographic process. If undercut occurs when removing the aluminum or aluminum alloy, corrosion occurs in the pad part. There is a problem that occurs.

In addition, the data line to which the image signal is applied is preferably formed of aluminum or an aluminum alloy, but is directly connected to the pixel electrode made of ITO, so that chromium, molybdenum, or the like having good physical and chemical properties may be obtained even though the resistance is slightly higher than that of aluminum. use. However, it is difficult to apply the large screen liquid crystal display due to signal delay.

An object of the present invention is to simplify the method of manufacturing a thin film transistor substrate for a liquid crystal display device.

In addition, another object of the present invention is to ensure the reliability of the pad portion and to minimize the signal delay of the wiring in the large-screen liquid crystal display.

In order to achieve this problem, in the present invention, an auxiliary data line made of aluminum or aluminum-based metal having low resistance is added, and a gate layer is formed when the semiconductor layer is formed by forming a photoresist film with a different thickness to simplify the manufacturing process. Expose pads and auxiliary data lines.

Specifically, first, the gate line and the auxiliary data line including the gate line in the first direction and the gate electrode connected to the gate line are formed on the insulating substrate. Subsequently, a first contact hole which exposes the auxiliary data line while simultaneously forming a resistive contact layer pattern and a semiconductor layer pattern on the gate electrode by stacking and patterning a gate insulating film, a semiconductor layer, and an ohmic contact layer covering the gate wiring and the auxiliary data line, in turn. A gate insulating film pattern having a structure is formed. Next, a data line extending in a second direction crossing the first direction and connected to the auxiliary data line through the first contact hole, a source electrode connected to the data line and adjacent to the gate electrode, and the source electrode are aligned with each other. A data wiring including a drain electrode positioned on one side is formed. Next, a portion of the resistive contact layer pattern not covered by the data line is removed, and a protective layer is stacked and etched to form a second contact hole exposing the drain electrode, and a pixel electrode connected to the drain electrode is formed on the protective layer.

The gate insulating layer pattern, the semiconductor layer pattern, and the ohmic contact layer pattern may be formed by a photolithography process using a single mask, and the mask may be formed in a first portion, a second portion having a higher transmittance than the first portion, and a second portion. A third portion having a high transmittance. In the photolithography process, the first portion is aligned to correspond to the semiconductor layer pattern, the third portion to correspond to the first contact hole, and the second portion to correspond to the gate insulating layer pattern.

At this time, in order to control the transmittance of the first to third portions differently, a mask-shaped irregularities or transparent and opaque patterns and a slit pattern are formed or at least one coating film having different transmittances is formed.

In addition, the gate insulating layer pattern, the semiconductor layer pattern, and the ohmic contact layer pattern may be formed by a photolithography process using a photosensitive layer. First, a photosensitive film is coated on the upper portion of the resistive contact layer and exposed to light to form a first part, a second part having a first thickness thicker than the first part, and a photosensitive film pattern having a second thickness thicker than the first thickness. Subsequently, the gate insulating film, the semiconductor layer, and the ohmic contact layer under the first portion are etched using the photoresist pattern as an etching mask to complete the gate insulating film pattern having the first contact hole. Next, the semiconductor layer and the ohmic contact layer under the second portion are etched using the photoresist pattern as an etching mask to complete the semiconductor layer pattern and the ohmic contact layer pattern.

Here, the gate wiring further includes a gate pad connected to the gate line to receive a scan signal from the outside, and the gate insulating layer pattern has a third contact hole exposing the gate pad, and in the data wiring forming step, the gate line is formed through the third contact hole. A first auxiliary gate pad may be formed to cover the pad. In addition, the passivation layer may have a fourth contact hole exposing the first auxiliary gate, and may form a second auxiliary gate pad connected to the first auxiliary gate pad through the fourth contact hole in the pixel electrode forming step.

In addition, the data line further includes a data pad connected to the data line to receive an image signal from the outside and transmit the image signal to the data line, wherein the passivation layer has a fifth contact hole for exposing the data pad, and the fifth contact hole in the pixel electrode forming step. An auxiliary data pad connected to the data pad may be formed through the second pad.

In the manufacturing method according to the present invention, the semiconductor layer pattern is preferably formed to extend to a portion where the gate line and the data line cross each other, and the gate line is preferably formed of aluminum or an aluminum alloy and the pixel electrode is formed of ITO.

Then, the liquid crystal display according to an exemplary embodiment of the present invention and a manufacturing method thereof will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

In an embodiment of the present invention, in order to simplify the manufacturing process, the gate pad part is exposed when the semiconductor layer is formed by partially adjusting the light transmittance in the photographic process to leave the photoresist film at a different thickness, and the auxiliary data made of a low resistance metal. Form additional lines.

First, a structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 4.

1 is a thin film transistor substrate for a liquid crystal display device according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of a thin film transistor unit and a pixel unit in which the thin film transistor substrate illustrated in FIG. 1 is cut along a line II-II. 3 is a cross-sectional view of the gate pad portion and the data pad portion of the thin film transistor substrate shown in FIG. 1 taken along line III-III, and FIG. 4 is a cutaway view of the thin film transistor substrate shown in FIG. 1 taken along line IV-IV. One cross section of the data line is shown.

Gate wirings and auxiliary data lines 28 made of aluminum or an aluminum-based alloy are formed on the insulating substrate 10. Of course, they can also be formed from multiple films comprising chromium, molybdenum or molybdenum alloys. The gate line is connected to the gate line 22 and the end of the gate line 22 extending in the horizontal direction, and the branch of the gate pad 26 and the gate line 22 which receive a gate signal from the outside and transmit the gate signal to the gate line 22. A gate electrode 24 of the phosphor thin film transistor, and the auxiliary data line 28 is formed in the vertical direction.

On the substrate 10, a gate insulating layer pattern 30 made of silicon nitride (SiN _x ) covers the gate wirings 22, 24, and 26 and the auxiliary data line 28. The gate insulating layer pattern 30 includes a gate pad ( 26 and contact holes 36 and 38 exposing the auxiliary data line 28 are formed.

A semiconductor layer pattern 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating layer 30 on the gate electrode 24, and a high concentration of silicide or n-type impurities is formed on the semiconductor layer pattern 40. Resistive contact layer patterns 54, 56 made of a material such as n + hydrogenated amorphous silicon, which are doped with N, are formed.

On the ohmic contact layer patterns 54 and 56 and the gate insulating layer pattern 30, data lines 62, 64, 66, and 68 made of chromium (Cr) or molybdenum-tungsten alloy are formed. The data line is formed in a vertical direction to define a pixel by crossing the gate line 22, and is connected to the auxiliary data line 28 through the contact hole 38 to overlap the auxiliary data line 28. ), A data pad 62 which is a branch of the data line 62 and is connected to one end of the source electrode 64 and the data line 62 which extends to the upper portion of the resistance contact layer 54 and receives an image signal from the outside ( 68, a drain electrode 68 that is separate from the source electrode 64 and positioned above the resistive contact layer pattern 56 opposite the source electrode 64 with respect to the gate electrode 24. In addition, the first auxiliary gate pad 65 is connected to the gate pad 26 through the contact hole 36 in the same layer as the data lines 62, 64, 66, and 68 and completely covers the contact hole 36. Is formed.

A passivation layer 90 is formed on the data wires 62, 64, 66, and 68, the first auxiliary gate pad 65, and the semiconductor layer pattern 40 not covered by the data lines 62, 64, 66, and 68. In the passivation layer 90, contact holes 96, 95, and 98 that expose the drain electrode 66, the first auxiliary gate pad 65, and the data pad 68, respectively, are formed.

A pixel electrode 82 connected to the drain electrode 66 is formed on the passivation layer 90 of the pixel portion through the contact hole 96, and the first auxiliary gate pad 65 is formed through the contact holes 95 and 98, respectively. And a second auxiliary gate pad 86 and an auxiliary data pad 88 connected to the data pad 68.

Here, as shown in FIGS. 1 and 2, the pixel electrode 82 overlaps the gate line 22 to form a storage capacitor.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having a structure according to this embodiment will be described in detail with reference to FIGS. 1 to 4 and FIGS. 5A to 9D.

5A, 6A, 8A, and 9A are layout views of a thin film transistor substrate during an intermediate process of manufacturing according to an embodiment of the present invention, and are shown in sequence according to the manufacturing sequence. 5B, 6B and 7A, 8B and 9B are views cut along the lines Vb-Vb ', VIb-VIb', VIIIb-VIIIb 'and IXb-IXb' in FIGS. 5A, 6A, 8A and 9A, respectively. And a TFT section, a pixel section, and a storage capacitor section. 5C, 6C, 7B, 8C, and 9C are views cut along the lines Vc-Vc ', VIc-VIc', VIIIc-VIIIc ', and IXc-IXc' in FIGS. 5A, 6A, 8A, and 9A, and the gate pad part. And cross-sectional views of the data pad section, and FIGS. 5D, 6D and 7C, 8D and 9D are along the lines Vd-Vd ', VId-VId', VIIId-VIIId 'and IXd and IXd' in FIGS. 5A, 6A, 8A and 9A, respectively. A cross-sectional view of the data pad section as shown in the drawings.

First, as shown in FIGS. 5A to 5D, a conductive material is stacked on the substrate 10 and a horizontal process including a gate line 22, a gate electrode 24, and a gate pad 26 in a patterning process using a first mask. Gate wiring in the direction and the auxiliary data line 28 in the vertical direction are formed. Here, the gate wirings 22, 24, 26 and the auxiliary data lines 28 are formed of aluminum or an aluminum-based metal having low resistance, or formed of a multilayer including chromium, molybdenum, or molybdenum alloy.

Next, as shown in FIGS. 6A and 7A to 7C, a three-layer film of the gate insulating film 30, the semiconductor layer 40 made of amorphous silicon, and the doped amorphous silicon layer 50 is sequentially stacked, and the second mask is used. A gate insulating film pattern 30 having contact holes 36 and 38 exposing the gate pad 26 and the auxiliary data line 28 by the patterning process, and an island-shaped semiconductor layer pattern 40 on the gate electrode 24. And the ohmic contact layer pattern 50 is formed. In this case, in order to form the contact holes 36 and 38, all of the gate insulating layer 30, the semiconductor layer 40, and the doped amorphous silicon layer 50 must be etched. Only layer 40 and resistive contact layer 50 should be removed. In order to form this, a photoresist pattern having at least three parts having different thicknesses should be used as an etching mask, and in order to form such a photoresist pattern, a mask having at least three regions having different transmittances should be used. This will be described in detail with reference to FIGS. 6B and 6C.

First, as shown in FIGS. 6B and 6C, the positive photosensitive film 100 is coated on the ohmic contact layer 50, and then the photosensitive film 200 is exposed using the mask 100. In this case, the mask 100 uses a different portion of light transmittance (A, B, C) in order to form the photoresist film remaining after development to have at least three portions having different thicknesses. The mask 100 is about 0 to 3% in the first portion A corresponding to the gate electrode 24, and the third portion C corresponding to the gate pad 26 is 90% or more, and the first portion And the third portion B, except the second portions A and C, has a transmittance of 20 to 60%, preferably about 25 to 40%. 6B and 6C, the thickness of the photoresist pattern 200 remaining after development is indicated by a thick line D. In FIG. At this time, the photosensitive film 200 of the portion corresponding to C may be completely removed as shown in the figure and may be left with a fine thickness, the thickness (t1) of the photosensitive film 200 of the portion corresponding to B is 2,000 ~ 5,000Å, preferably Preferably it is about 3,000-4,000 micrometers, and it is preferable that the thickness t2 of the part corresponding to A is 1 micrometer or more. However, these conditions may vary depending on the etching method and conditions thereof for patterning the three layer films 30, 40, and 50, and may vary depending on the thickness of the three layer films 30, 40, and 50. In this case, in order to form the photoresist pattern 100 as shown in FIGS. 6B and 6C, the transmittance of the mask must be adjusted in a reverse order.

Subsequently, when dry etching is performed using the photoresist pattern 200 having partially different thicknesses t1 and t2 as an etching mask, etching may be selectively performed in order according to the difference in thickness of the photoresist pattern 200. First, using the photoresist pattern 200 of the A and B portions as an etch mask, the three-layer films 30, 40, and 50 of the portion corresponding to C in the screen display portion and the pad portion are etched to form contact holes as shown in FIGS. 7B and 7C. A gate insulating film pattern 30 having (36, 38) is formed. In this case, although the photoresist pattern 200 of the A and B portions is also etched, even when the gate pad 26 and the auxiliary data line 28 of the C portion are etched to be exposed, the photoresist layer of the B portion is not completely removed. It is preferable to leave enough photosensitive film. Next, the photoresist film remaining in the portion B is removed by an ashing process, and the semiconductor layer 40 and the resistance contact layer 50 in the portion B are etched using the photoresist pattern 200 remaining in the portion A as an etching mask. Thus, the semiconductor layer pattern 40 and the ohmic contact layer pattern 50 are left only on the gate electrode 24, and the photoresist film remaining on the gate electrode 24 is removed. Here, the intermediate ashing process may be omitted according to the etching conditions and the thickness of the photoresist pattern 100, and the etching selectivity for each of the semiconductor layer 40, the resistance contact layer 50, and the gate insulating layer 30 is large. You can also choose to proceed with the etching process through several steps. However, when etching is performed under conditions having similar etching rates with respect to the amorphous silicon layers 40 and 50 and the gate insulating layer 30, the semiconductor layer is formed on the gate insulating layer 30 of the gate electrode 24 in one etching process. Contact holes 36 and 38 exposing the gate pad 26 and the auxiliary data line 36 are formed while leaving the pattern 40 and the amorphous silicon layer pattern 50, and the gate insulating layer pattern 30 is formed in the remaining portions. I can leave it.

The gate pad 26 is formed while forming the semiconductor layer pattern 40 and the resistive contact layer pattern 50 even when the photoresist pattern having at least three parts having different thicknesses is formed and patterned in one photolithography process using the same as an etching mask. And the gate insulating film pattern 30 having the contact holes 36 and 38 exposing the auxiliary data line 28, thereby simplifying the manufacturing process.

In this case, the semiconductor layer pattern 40 may be formed sufficiently wide to a portion where the data line 62 (see FIG. 1) to be formed later passes. This is to minimize the disconnection of the data line 62 due to the step.

In addition, in order to partially control the amount of light transmitted differently, the mosaic pattern or the light may be diffracted / dispersed to form mosaic irregularities to reduce the amount of transmitted light, and may also coat a film capable of reducing the amount of transmitted light. In addition, the amount of light transmitted may be adjusted using a slit pattern. Here, the size of the pattern and the section and the spacing of the slit patterns should be smaller than the resolution of the exposure machine used in the photographic process.

Next, as shown in FIGS. 8A to 8D, molybdenum or molybdenum alloy or chromium is laminated, and then patterned by a third process using a mask to intersect with the branched gate line 22, and a plurality of contact holes 38. The data line 62 connected to the auxiliary data line 28 and the source electrode 64 and the data line 62 connected to the data line 62 and extending to the upper portion of the gate electrode 24 through A data wiring and contact hole separated from the data pad 68 and the source electrode 64 connected to one end and including a drain electrode 66 facing the source electrode 66 with respect to the gate electrode 24 ( A first auxiliary gate pad 65 connected to the gate pad 26 is formed through the 36. In this case, the first auxiliary gate pad 65 is formed to completely cover the contact hole 36.

Subsequently, the doped amorphous silicon layer pattern 50, which is not covered by the data lines 62, 64, 66, and 68, is etched and separated on both sides of the gate electrode 24, while both doped amorphous silicon layers ( The semiconductor layer pattern 40 between 54 and 56 is exposed.

Next, as shown in FIGS. 9A to 9D, after the protective film 90 made of the organic insulating film is stacked, the contact hole 96 exposing the drain electrode 66 is exposed by photo etching using a fourth mask. And contact holes 95 and 98 for exposing the first auxiliary gate pad 65 and the data pad 68.

Next, as shown in FIGS. 1 to 4, the ITO film is stacked and patterned using a fifth mask, and the pixel electrode 82 and the contact hole 95 are connected to the drain electrode 66 through the contact hole 96. The second auxiliary gate pad 86 and the auxiliary data pad 88 connected to the first auxiliary gate pad 65 and the data pad 68, respectively, are formed through 98. In this case, the pixel electrode 82 is formed to overlap the gate line 22 of the front end to form a storage capacitor. When the storage capacitor of the storage capacitor is not sufficient, the storage electrode line may be further formed on the same layer as the gate wiring. It may be.

In this embodiment of the present invention, by forming a protective film 90 made of an organic insulating film having a lower dielectric constant than an insulating film made of silicon nitride or silicon oxide, the pixel electrode 82 and the auxiliary data line 28 or as shown in FIG. Even if formed to overlap with the data line 62, interference of the signal can be minimized and the aperture ratio of the sweep can be improved.

In addition, since the gate pad 26 is electrically connected to the second auxiliary gate pad 86 made of ITO through the first auxiliary gate pad 65, the gate pad 26 may be formed of aluminum or an aluminum alloy having low resistance. If the auxiliary gate pad 65 is formed of a metal material having excellent ITO contact characteristics, the contact reliability of the pad portion may be improved.

In addition, by forming an auxiliary data line 28 made of an aluminum-based metal having low resistance, a signal delay may be minimized even when applied to a liquid crystal display having a large screen.

According to the present invention, when the semiconductor layer is formed, a contact hole for exposing the gate pad and the auxiliary data pad is formed to secure the pad part even when using low-resistance aluminum or aluminum alloy, thereby preventing signal delay along the large screen. Can be. In addition, by manufacturing the thin film transistor substrate for a liquid crystal display device by simplifying the manufacturing process, the manufacturing cost may be reduced, and the aperture ratio of the pixel may be improved.

Claims (12)

Forming a gate line and an auxiliary data line including a gate line in a first direction and a gate electrode connected to the gate line on the insulating substrate; Sequentially stacking a gate insulating layer, a semiconductor layer, and an ohmic contact layer covering the gate line and the auxiliary data line; A photolithography process using a mask including a first portion, a second portion having a higher transmittance than the first portion, and a third portion having a higher transmittance than the second portion, wherein the gate insulating layer and the ohmic contact layer are formed. And etching the semiconductor layer to form a resistive contact layer pattern and a semiconductor layer pattern on the gate electrode and to form a gate insulating layer pattern having a first contact hole exposing the auxiliary data line. A data line extending in a second direction crossing the first direction and connected to the auxiliary data line through the first contact hole, a source electrode connected to the data line and adjacent to the gate electrode, and the gate electrode; Forming a data line including a drain electrode located opposite the source electrode, Removing a portion of the resistive contact layer pattern not covered by the data line; Stacking and etching a passivation layer to form a second contact hole exposing the drain electrode; Forming a pixel electrode connected to the drain electrode on the passivation layer Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. delete delete In claim 1, The method of claim 1, wherein in the photolithography process, the first portion is aligned with the semiconductor layer pattern, the third portion is aligned with the first contact hole, and the second portion is aligned with the gate insulating layer pattern. In claim 1, A method of manufacturing a thin film transistor substrate for a liquid crystal display device, in which a mosaic-shaped unevenness or a transparent and opaque pattern and a slit pattern are formed in the mask to differently control the transmittances of the first to third portions. In claim 1, A method of manufacturing a thin film transistor substrate for a liquid crystal display device, in which a coating film is formed on the mask to differently control the transmittances of the first to third portions. In claim 1, The gate insulating layer pattern, the semiconductor layer pattern, and the ohmic contact layer pattern forming step may be performed using a photolithography process using a photosensitive film. Forming the gate insulating layer pattern, the semiconductor layer pattern, and the ohmic contact layer pattern may include: Applying the photosensitive film on top of the ohmic contact layer; Exposing and developing the photoresist film to form a photoresist pattern including a first region having a first thickness, a second region having a second thickness greater than the first thickness, and a third region having a third thickness greater than the second thickness. Forming step, Etching the gate insulating film, the semiconductor layer, and the ohmic contact layer below the first region by using the photoresist pattern as an etching mask to complete the gate insulating film pattern having the first contact hole; Etching the semiconductor layer and the ohmic contact layer under the second region using the photoresist pattern as an etch mask to complete the semiconductor layer pattern and the ohmic contact layer pattern The manufacturing method of the thin film transistor substrate for liquid crystal display devices. In claim 1, The gate line further includes a gate pad connected to the gate line to receive a scan signal from the outside, Forming a third contact hole exposing the gate pad in the gate insulating film pattern forming step, Forming a first auxiliary gate pad covering the gate pad through the third contact hole in the data wire forming step, Forming a fourth contact hole exposing the first auxiliary gate in the protective film forming step, And forming a second auxiliary gate pad connected to the first auxiliary gate pad through the fourth contact hole in the pixel electrode forming step. In claim 1, The data line further includes a data pad connected to the data line to receive an image signal from the outside and transfer the image signal to the data line. Forming a fifth contact hole exposing the data pad in the protective film forming step, And forming an auxiliary data pad connected to the data pad through the fifth contact hole in the pixel electrode forming step. In claim 1, The semiconductor layer pattern extends to a portion where the gate line and the data line cross each other. In claim 1, And the gate wiring is formed of aluminum or an aluminum alloy. In claim 1, And the pixel electrode is formed of ITO.

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