KR100601171B1 - Thin film transistor substrate for liquid crystal display and manufacturing method thereof - Google Patents

Abstract

First, a lower layer of a transparent conductive material, a buffer layer, and an upper layer of a low resistance conductive material are sequentially stacked on the insulating substrate, and a photoresist pattern having at least three different thicknesses is formed and patterned with an etching mask to form a gate line, a gate electrode, and a gate pad. Forming a gate wiring of the three-layer film and a pixel electrode of the lower film. Subsequently, a gate insulating film, a semiconductor layer, and an etching blocking insulating film made of silicon nitride are stacked, and a photoresist pattern having at least three different thicknesses is formed by a photolithography process using a second mask, and patterned with an etching mask to cover the gate wiring. An etch stop layer is formed on the gate electrode while the semiconductor pattern exposing the gate pad and the gate insulating layer pattern are formed. In this case, the process of using the photoresist layer may be omitted by forming the etch stop layer as the photosensitive sustain insulating layer. Subsequently, the contact layer, the data conductor layer, and the protective film are sequentially stacked, and a photoresist pattern having at least three parts having different thicknesses is formed by a photolithography process using a third mask. A protective film pattern is formed. Here again, the process of forming a protective film by the photosensitive insulating film and using a photosensitive film can be skipped. Next, when the semiconductor layer remains on the gate line, the semiconductor layer not covered by the protective layer pattern is removed to prevent leakage current.

Mask, photoresist, transmittance, exposure machine, resolution

Description

Thin film transistor substrate for liquid crystal display device and manufacturing method therefor {THIN FILM TRANSISTOR SUBSTRATE FOR LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD THEREOF}

1 is a layout view illustrating a structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along the line II-II.

FIG. 3 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along line III-III.

4A is a layout view illustrating a structure of a thin film transistor substrate in an intermediate process of manufacturing according to an embodiment of the present invention.

4B and 4C are cross-sectional views taken along lines IVb-IVb 'and IVc-IVc' in FIG. 4A and illustrate structures of a screen display unit and a pad unit.

5A and 5B are cross-sectional views taken along the lines IVb-IVb 'and IVc-IVc' in FIG. 4A, showing the next steps of FIGS. 4B and 4C;

5C and 5D are cross-sectional views each illustrating a pad unit and a screen display unit in a manufacturing process according to another exemplary embodiment of the present invention.

6A is a layout view illustrating a structure of a thin film transistor substrate in an intermediate process of manufacturing according to an embodiment of the present invention.

6B, 7A, 6C, and 7B are cross-sectional views taken along the lines VIb-VIb 'and VIc-VIc' of FIG. 6A, and are cross-sectional views illustrating the following steps of FIGS. 5A and 5B;

8A and 8B are cross-sectional views taken along the lines VIb-VIb 'and VIc-VIc' in FIG. 6A, showing the next steps of FIGS.

9 and 10 are cross-sectional views of a screen display unit and a pad unit showing the next steps of FIGS. 5D and 5C in the manufacturing method according to another exemplary embodiment of the present invention.

The present invention relates to a thin film transistor substrate for a liquid crystal display device and a manufacturing method thereof.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. By controlling the amount of light transmitted.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on each of two substrates and switching a voltage applied to the electrode is generally used. The thin film transistor is generally formed on one of two substrates. to be.

At this time, the substrate on which the thin film transistor is formed is manufactured through a photolithography process using a mask. In order to reduce the production cost, it is required to reduce the number of photolithography processes using a mask.

An object of the present invention is to simplify the method of manufacturing a thin film transistor substrate for a liquid crystal display device.

In order to achieve the above object, the present invention forms a photoresist pattern having at least three different thicknesses in one photolithography process using a mask and uses the same as an etching mask to expose the gate pad while forming an etch stop layer on the gate electrode. The data line and the pixel electrode are formed together.

More specifically, a gate layer including a gate line in a horizontal direction, a gate electrode which is a part or branch of the gate line, and a gate pad connected to the gate line and receiving a scan signal from the outside by stacking and patterning a conductor layer on the insulating substrate. The wiring and the pixel electrode are formed together. Subsequently, the gate insulating film, the semiconductor layer, and the etch stop insulating film covering the gate wiring are sequentially stacked and patterned to have a semiconductor layer pattern having a first contact hole that has a different size from that of the etch stop film and at least the etch stop film and exposes the gate pad; A gate insulating film pattern is formed. Next, the data wiring conductor layer and the protective layer are sequentially stacked and patterned to extend in the vertical direction to intersect the gate line to define a pixel, a source electrode which is a part or branch of the data line, and is positioned opposite to the source electrode with respect to the gate electrode. And a data line and a passivation layer pattern including a drain electrode connected to the pixel electrode and a data pad connected to the data line to receive an image signal from the outside.

In this case, the conductor layer may be formed of a first conductive film made of at least a transparent conductive material and a second conductive film positioned on the first conductive film, and may include a buffer film therebetween.

When the gate wiring and the pixel electrode are formed of the first and second conductive films, it is preferable to form the data wiring and the protective film pattern, and then to remove the second conductive film of the pixel electrode not covered by the protective film pattern and the gate insulating film pattern. When the buffer film is included, the second conductive film is also removed at this time.

In addition, the gate wiring and the pixel electrode may be formed by a photolithography process using a mask having a different transmittance of at least three regions, wherein the mask may include a thin film having a different transmittance or a thin film or an exposure device to partially adjust the transmittance. It is desirable to form a fine pattern smaller than the resolution.

Meanwhile, the gate line and the pixel electrode may form the photosensitive film by a photolithography process. First, the photosensitive film is coated on the second conductive film, exposed and developed to include at least a first portion, a second portion having a first thickness thicker than the first portion, and a third portion having a second thickness thicker than the first thickness. A photosensitive film pattern is formed. Next, the first and second conductive layers under the first portion are etched using the photoresist pattern as an etch mask, and the second conductive film in the second portion is etched using the photoresist pattern of the third portion as an etch mask. The pixel electrode of the conductive film and the gate wirings of the first and second conductive films are completed.

In this case, the auxiliary data pad in contact with the data pad may be further formed on the same layer as the pixel electrode, and the gate pad and the auxiliary data pad may be formed only of the first conductive layer. Here, the data line and the passivation layer pattern have a second contact hole for exposing the auxiliary data pad, and the data line and the passivation layer pattern are preferably formed in the same shape.

Meanwhile, the etch stop layer, the semiconductor layer pattern, and the gate insulating layer pattern may be formed by a photo process using a mask having different transmittances of at least three regions, and the mask may have a thin film having a different transmittance or a different thickness to partially control the transmittance. Alternatively, a fine pattern smaller than the resolution of the exposure machine can be formed.

In addition, after the data line and the passivation layer pattern are formed, it is preferable that the semiconductor layer pattern not covered by the passivation layer pattern is etched to separate the semiconductor layer patterns under the adjacent data lines. In addition, a resistive contact layer made of doped amorphous silicon or silicide may be formed under the data line, and the resistive contact layer may be etched together with the data line.

The etch stop layer, the semiconductor layer pattern, and the gate insulating layer pattern may be formed by the following method. First, a photosensitive film is coated and developed on the etch stop insulating layer to include at least a first portion, a second portion having a first thickness thicker than the first portion, and a photosensitive film including a third portion having a second thickness thicker than the first thickness. Form a pattern. Next, using the photoresist pattern as an etching mask, the etch stop insulating film, the gate insulating film, and the semiconductor layer are etched together with the second portion to complete the gate insulating film pattern and the semiconductor layer pattern. Subsequently, the etch stop layer is etched using the third portion as an etch mask to complete the etch stop layer.

The etch stop insulating film may be formed of a photosensitive organic insulating material, and the etch stop film, the semiconductor layer pattern, and the gate insulating film pattern may be formed by the following method. First, the etching barrier insulating layer is exposed and developed to include at least a first portion, a second portion having a first thickness thicker than the first portion, and an etching barrier insulating layer pattern including a third portion having a second thickness thicker than the first thickness. To form. Next, the gate insulating film and the semiconductor layer of the first portion are etched together with the second portion by using the etch stop insulating film pattern as an etch mask to complete the gate insulating film pattern and the semiconductor layer pattern, leaving the third portion to complete the etch stop layer. .

In addition, the data wiring and the protective film pattern can be formed as follows. The photoresist is coated and exposed to light on the passivation layer to form a photoresist pattern including at least a first part, a second part having a first thickness thicker than the first part, and a third part having a second thickness thicker than the first thickness. . Then, using the photoresist pattern as an etch mask, the protective layer of the first portion and the data wiring conductor layer are etched together with the second portion to complete the data wiring, and the protective layer is etched using the third portion as the etching mask to expose the data pad. Complete the protective pattern.

In addition, the protective film is preferably formed of a photosensitive organic material, and the conductor layer preferably contains ITO or IZO.

Then, the liquid crystal display according to an exemplary embodiment of the present invention and a manufacturing method thereof will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

In the embodiment of the present invention, in order to simplify the manufacturing process, a photo process using a mask that can adjust the intensity of the light partially transmitted to form a photoresist pattern having at least three parts having different thicknesses and using it as an etching mask, The gate line and the pixel electrode are formed together, and the etch stop layer and the semiconductor layer pattern are formed together.

The thin film transistor substrate for a liquid crystal display device completed through such a manufacturing process includes a gate electrode and a gate electrode that is a part of the gate line on the insulating substrate, and a pixel electrode including a gate wiring including a transparent conductive film and a transparent conductive film is formed. have. A gate insulating film pattern covering the gate wiring is formed on the gate wiring, a semiconductor layer pattern is formed on the gate insulating film pattern, and an etch stop layer is formed on the semiconductor layer pattern of the gate electrode. The semiconductor layer pattern and the upper part of the substrate are divided into two parts around the gate electrode, and one part is formed with a contact layer pattern connected to the pixel electrode, and on the contact layer pattern, a branch of the data line and the data line crossing the gate line or A data pad connected to a part of a source electrode and a data line is formed, and a drain electrode is formed on another contact layer pattern.

First, the structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 to 3 are layout views illustrating a structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along a line II-II. 3 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along the line III-III. The structure of the thin film transistor substrate for a liquid crystal display according to this embodiment is manufactured according to the manufacturing method using the three-layer mask described later.

As shown in FIGS. 1 to 3, the gate line 22 and the gate line 22 extending in the horizontal direction on the insulating substrate 10 are connected to the ends of the gate line 22 to receive a scan signal from the outside and transfer the same to the gate line. The gate wiring 26 and the pixel electrode 28 including the gate electrode 24 of the thin film transistor which is a part of the gate pad 26 and the gate line 22 are formed. In this case, the gate wirings 22, 24, and 26 may include the lower layers 221, 241 and 261 made of indium tin oxide (ITO) or indium zinc oxide (IZO), which are transparent conductive materials, and chromium or molybdenum or molybdenum alloys. A buffer film 222, 242, 262, and an upper film 223, 243, 263 made of a low resistance metal, such as aluminum or an aluminum alloy, molybdenum, molybdenum alloy, or the like, and the pixel electrode 28 includes a gate wiring ( It consists of a single film of a transparent conductive film which is the same layer as the lower films 221, 241, and 261 of 22, 24, and 26. The buffer layers 222, 242, and 262 may prevent the upper layers 223, 243, and 263 from directly contacting the lower layers 221, 241, and 261, and the lower layers 221, 241, and 261 may be formed of ITO or ITO. The buffer films 222, 242, and 262 may be omitted when the IZO is not corroded even if it contacts the IZO.

On the substrate 10, a gate insulating layer pattern 32 made of silicon nitride (SiN _x ) is formed along the shape of the gate lines 22, 24, and 26 to cover the gate lines 22, 24, and 26. The gate insulating film pattern 30 has a contact hole 46 exposing a part of the gate pad 26.

The semiconductor layer patterns 42, 44, and 48 are formed on the gate insulating layer pattern 32. In this case, the semiconductor layer pattern is positioned above the gate electrode 24 and is positioned between the portion 42 in which the channel of the thin film transistor is formed and the pixel electrode 28 and the storage capacitor electrode 77 formed thereafter ( 48 and three portions separated from each other by the remaining portion 44 positioned at the overlapping portion of the data line 72 and the gate line 22 formed thereafter. Here, the pixel electrode 28 is formed to overlap with the gate line 22 of the front end positioned above the storage capacitor electrode 77 and has a function of a storage capacitor for forming the storage capacitor. At this time, when the storage capacitance is not sufficient, the storage capacitor electrode line may be added to the same layer as the gate wirings 22, 24, 26.

On the semiconductor layer pattern 42 of the gate electrode 24, an etch stop layer 52 made of silicon nitride or an organic insulating layer is formed in an island shape inside the semiconductor layer pattern 42.

The semiconductor layer patterns 42, 44, 46, and 48, which are not covered by the etch stop layer 52 and the etch stop layer 52, and the substrate 10 are separated into two portions around the gate electrode 24. An ohmic contact layer pattern 62, 64, 66, 68 made of an amorphous silicon layer or silicide is formed. In addition, an ohmic contact layer pattern 67 extending from the pixel electrode 28 to the upper portion of the semiconductor layer pattern 48 is formed.

The upper portions of the resistive contact layer patterns 62, 64, and 68 are formed in the vertical direction and extend to the upper portion of the data line 72 and the gate electrode 24 defining the pixel by crossing the gate line 22. A source pad 74, which is a branch of 72, and a data pad 78 connected to one end of the data line 72 are formed. In addition, a drain electrode 76 is formed on a portion of the other portion 66 of the resistive contact layer pattern, and a storage capacitor electrode 77 is formed on the remaining portion 67 of the resistive contact layer pattern. Here, the resistive contact layer patterns 62, 64, 66, 67, 68 are formed in the same shape as the data wirings 72, 74, 76, 78 and the storage capacitor electrode 77, but the resistive contact layer patterns ( When the 62, 64, 66, 67, and 68 are formed of silicide, the ohmic contact layer patterns 62, 64, 66, 67, and 68 remain only on the semiconductor layer patterns 42, 44, and 48.

On the upper portions of the data lines 72, 74, 76, 78 and the storage capacitor electrode 77, a protective film 90 made of silicon nitride or an organic insulating film is formed. Has a contact hole 98 exposing a portion of data pad 78. Except for the contact hole 98, the protective film 90 has the same shape as the data wirings 72, 74, 76, 78 and the storage capacitor electrode 77.

In the structure according to the exemplary embodiment of the present invention, the semiconductor layer patterns 42, 44, and 48 may be formed only at a portion where the data lines 72, 74, 76, the storage capacitor electrode 77, and the gate insulating layer pattern 30 overlap each other. Formed.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having a structure according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3 and 4A to 10.

4A is a layout view illustrating a structure of a thin film transistor substrate during an intermediate process manufactured according to an exemplary embodiment of the present invention, and FIGS. 4B and 4C are cut along lines IVb-IVb 'and IVc-IVc' in FIG. 4A. 5A and 5B are cross-sectional views taken along the lines IVb-IVb 'and IVc-IVc' in FIG. 4A and show the next steps of FIGS. 4B and 4C. 5C and 5D are cross-sectional views illustrating pads and screen displays respectively in a manufacturing process according to another embodiment of the present invention, and FIG. 6A is a thin film in an intermediate process of manufacturing according to an embodiment of the present invention. 6B, 7A, 6C, and 7B are views taken along the lines VIb-VIb 'and VIc-VIc' in FIG. 6A, and the following steps of FIGS. 5A and 5B are shown. 8A and 8B illustrate VIb-VIb 'in FIG. 6A. 5A and 5B are cross-sectional views of another embodiment showing the next steps of FIGS. 5A and 5B, taken along the line VIc-VIc ', and FIGS. 9 and 10C in a manufacturing method according to another embodiment of the present invention. Is a cross-sectional view of the screen display section and pad section showing the next step.

First, as shown in FIGS. 4A and 5A to 5B, a lower film 201 made of ITO or IZO and an buffer film 202 of chromium, molybdenum or molybdenum alloy film, and aluminum or aluminum alloy are formed on the insulating substrate 10. Alternatively, the upper layer 203 made of a conductive material having a low resistance such as molybdenum or molybdenum alloy is sequentially stacked and patterned by a photolithography process using a mask to form the lower layers 221, 241, and 261 and the buffer layers 222, 242, and the like. 262 and the upper layers 223, 243, and 263, and include only the gate wiring and the lower layer 28 including the gate line 22, the gate electrode 24, and the gate pad 26 in the horizontal direction. A pixel electrode is formed.

In this case, in order to form the pixel electrode 28 as the lower layer only in the pixel region, the upper layer 203 and the buffer layer 202 must be removed, and the gate lines 22 to form the gate lines 22, 24, and 26. In order to do this, the upper layer 203, the buffer layer 202, and the lower layer 201 must be left, and the upper layer 203, the buffer layer 202, and the lower layer 201 must be removed. In order to form this, a photoresist pattern having at least three parts having different thicknesses should be used as an etching mask, and in order to form such a photoresist pattern, a mask having at least three regions having different transmittances should be used. This will be described in detail with reference to FIGS. 4B and 4C.

First, as shown in FIGS. 4B and 4C, the positive photosensitive film 100 is coated on the upper layer 203, and then the photosensitive film 100 is exposed using the first mask 200. In this case, the first mask 200 uses a different portion of light transmittance (A, B, C) in order to form the photoresist film remaining after development to have at least three portions having different thicknesses. The first mask 200 is about 0 to 3% in the first portion A corresponding to the portion where the gate wirings 22, 24, and 26 are formed, and corresponds to the portion where the pixel electrode 28 is formed. The portion B is 20 to 60%, preferably about 25 to 40%, and the remaining portions except for the first and second portions A and B each have a transmittance of 90% or more. 4B and 4C show the thickness of the photoresist pattern 100 remaining after development. At this time, the photoresist film 100 of the portion corresponding to C may be completely removed as shown in the drawing and may be left with a fine thickness, the thickness (t1) of the photosensitive film 100 of the portion corresponding to B is 2,000 ~ 5,000Å, preferably Preferably it is about 3,000-4,000 micrometers, and it is preferable that the thickness t2 of the part corresponding to A is 1 micrometer or more. However, such a condition may vary depending on an etching method and conditions for patterning the lower layers 201, 202, and 203, and may vary depending on the thickness of the lower layers 201, 202, and 203, and the photoresist pattern may be negative. In this case, in order to form the photoresist pattern 100 as shown in FIGS. 4B and 4C, the transmittance of the mask must be adjusted differently.

Subsequently, when dry etching is performed using photoresist patterns 100 having partially different thicknesses t1 and t2 as an etching mask, etching may be selectively performed in order according to the difference in thicknesses of the photoresist patterns 100. First, by using the photoresist pattern 100 of the A and B portions as an etching mask, the three-layer films 201, 202, and 203 of the portion corresponding to C in the screen display portion and the pad portion are etched to form pixel electrodes as shown in FIGS. 5A and 5B. Lower layer patterns 221, 241, 261, and 28 including 28 are formed. In this case, although the photoresist pattern 100 of the A and B portions is also etched, it is preferable to leave the photoresist film sufficiently in the exposure and development processes so that the photoresist of the B portion is not completely removed even when the substrate 10 of the C portion is exposed. Next, the photoresist film remaining in the portion B is removed by an ashing process, and the upper layer 203 and the buffer layer 202 in the portion B are etched using the photoresist pattern 100 remaining in the portion A as an etching mask. Gate wirings 22 and 24 including the pixel electrode 28 formed only of the lower layer, the lower layer patterns 221, 241 and 261, the buffer layer patterns 222, 242 and 262, and the upper layer patterns 223, 243 and 263. , 26) and remove the photoresist remaining on the top. Here, the intermediate ashing process may be omitted depending on the etching conditions and the thickness of the photoresist pattern 100.

At this time, as shown in FIG. 5C, in another embodiment, the gate pad 26 may be formed as a single layer of the lower layer 261 as in the pixel electrode 28 of FIG. 5B, and an auxiliary data pad 268 may be added. It may be.

In another embodiment, the pixel electrode 28 may be formed of a three-layer film including a lower film 281, a buffer film 282, and an upper film 283 using a conventional mask. In this case, the pixel electrode 28 is not in a completed state, and the upper layer 283 and the buffer layer 282 are removed in a process of forming a data line thereafter or a subsequent process to remove the single layer only of the lower layer 283. It is desired to complete the pixel electrode 28.

When the photoresist pattern having at least three parts having different thicknesses is formed and used as an etching mask, the gate wirings 22, 24, and 26 of the three layer film and the pixel electrode 28 of the single layer are formed even when patterned in one photolithography process. can do.

Next, as shown in FIGS. 6A and 7A to 7B, the gate insulating layer 30, the semiconductor layer 40, and the etch stop insulating layer 50 are sequentially stacked and patterned by a photolithography process using a single mask. While forming the etch stop layer 52 in an island shape on the electrode 24, the semiconductor layer pattern 41 and the gate insulating layer pattern 32 covering the gate wirings 22, 24, and 26 are formed, and the gate pad ( Form a contact hole 46 exposing 26).

In this case, the gate insulating film 30, the semiconductor layer 40, and the etch stop insulating film 50 must be removed from the pixel region and the contact hole 46, and the etch stop layer 52 is disposed on the gate electrode 24. ) And only the insulating layer 50 for etching inhibition is to be removed. To do this, as in the foregoing, a photoresist pattern having at least three parts having different thicknesses should be used as an etching mask, and in order to form such a photoresist pattern, a mask having at least three regions having different transmittances should be used. This will be described in detail with reference to FIGS. 6B and 6C.

First, as shown in FIGS. 6B and 6C, the positive photosensitive film 300 is coated on the etch stop insulating film 50, and then the photosensitive film 300 is exposed using the second mask 400. In this case, the second mask 400 uses different portions of light transmittance (A, B, C) in order to form the photoresist film remaining after development to have at least three portions having different thicknesses. 6B and 6C show the photoresist pattern 300 remaining after development, and the photoresist 300 of the portion corresponding to A may be completely removed as shown in the drawing, or may be left with a fine thickness. Here, it is preferable that the thickness t2 of the photosensitive film 300 of the part corresponding to B is 2,000-5,000 kPa, Preferably it is about 3,000-4,000 kPa, and the thickness t1 of the part corresponding to C is 1 micrometer or more. desirable. However, these conditions may vary depending on the etching method and the conditions for patterning the lower layers 30, 40, and 50, and may vary depending on the thicknesses of the lower layers 30, 40, and 50.

Subsequently, when dry etching is performed using the photoresist pattern 300 having partially different thicknesses t1 and t2 as an etching mask, etching may be selectively performed in order according to the difference in thickness of the photoresist pattern 300. First, using the photoresist pattern 300 of the B and C portions as an etching mask, the three-layer films 30, 40, and 50 of the portion corresponding to A in the screen display portion and the pad portion are etched, and then contact holes as shown in FIGS. 7A and 7B. A gate insulating film pattern 32 having a 46 and a semiconductor layer pattern 41 are completed. At this time, the photoresist pattern 300 of portions B and C is also etched, but the photoresist of portion B is not completely removed. Next, the photoresist film remaining in the portion B is removed by an ashing process, and the etch stop insulating layer 50 is etched by using the photoresist pattern 300 remaining in the portion C as an etching mask. An etch stop layer 52 is formed on the semiconductor layer pattern 41, and the photoresist layer remaining in the portion C is removed. Here, the intermediate ashing process may be omitted depending on the etching conditions and the thickness of the photoresist pattern 300.

In the above, the etch stop layer 52, the semiconductor layer pattern 41, the gate insulating layer pattern 32, and the contact hole 46 were formed using the photoresist pattern as an etch mask. 50) may be formed of a photosensitive organic insulating material capable of a photographic process. This will be described in detail with reference to FIGS. 8A and 8B.

When the etch stop insulating film 50 made of a photosensitive organic insulating material capable of performing a photolithography process is stacked on the semiconductor layer 40 and exposed to light using a second mask, the etching process may be partially different from those shown in FIGS. 8A and 8B. An etch stop insulating film pattern 50 having a thickness may be formed.

Next, using the etching mask as an etching mask, the etch stop insulating film 50, the semiconductor layer 40, and the gate insulating film 30 are etched. The semiconductor layer pattern 41 and the gate insulating film pattern ( The etch stop layer 52 may be formed while completing the 32 and the contact holes 46. In this way, the manufacturing process can be simplified simply by removing the formation of a photosensitive film and eliminating the step. In this case, when there is a residue of the etch stopper insulating film 50 in portions except the etch stopper film 52, it is preferable to add an ashing process to remove the residue.

Subsequently, as shown in FIGS. 1 to 3, the doped amorphous silicon layer, the data conductor layer, and the passivation layer 90 are sequentially stacked and a mask capable of differently controlling the transmittance of at least three parts similarly to the method described above. The photoresist pattern is formed by a photolithography process using the photoresist. Next, when the patterning process is performed using this as an etching mask, the protective film pattern 90 having the contact hole 98, the data wirings 72, 74, 76, 78, the storage capacitor electrode 77 and the lower portion thereof are formed. The ohmic contact layer patterns 62, 64, 66, 68, and 67 are formed.

The contact layer patterns 62, 64, 66, 68, and 67 may be formed of silicide. In this case, the metal film may be removed by laminating a metal film capable of forming silicide in combination with silicon to form a silicide on the semiconductor layer pattern 41 that is not covered by the etch stop film 52. In this case, the ohmic contact layer patterns 62, 64, 66, 68, and 68 are formed only on the upper portion of the semiconductor layer pattern 41.

In this case, when the semiconductor layer remains on the gate line 22 between the adjacent data lines 72, a distortion of an image signal applied to the data line 72 may occur due to leakage current, thereby separating the semiconductor layers. It is desirable to. To this end, the semiconductor layer pattern 41 not covered by the protective layer pattern 90 may be etched to separate the semiconductor layer patterns 42, 44, and 48 from each other, as shown in FIGS. 1 to 3.

On the other hand, as shown in FIG. 5D, when the pixel electrode 28 is formed of a three-layer film like the gate wirings 22, 24, and 26, the pixel electrode not covered by the protective film pattern 90, as shown in FIG. 9. The upper film 283 and the buffer film 282 of 28 are removed to expose the lower film 281 which is a transparent conductive film of the pixel electrode 28.

In addition, as shown in FIG. 5C, when the gate pad 26 and the auxiliary data pad 268 are formed as a single lower layer, the data pad 78 is formed through the contact layer pattern 68. The protective layer pattern 90, the data pad 78, and the contact layer pattern 68 thereunder are formed to expose the auxiliary data pad 268 through the contact hole 98. In this case, since a photosensitive film pattern having three portions having different thicknesses does not have to be used as a mask, a conventional mask can be used in the process of forming the data lines 72, 74, 76, and 78.

Here, in the case where the protective film 90 is formed of a photosensitive organic insulating film that can be patterned by a photolithography process, the process of using the photosensitive film is omitted, as in the case of forming the etch stop film 50 of the photosensitive organic insulating film. can do.

In the manufacturing method according to the embodiment of the present invention, the photoresist patterns 100 and 300 having partially different thicknesses are formed by using masks having partially different transmittances, in order to partially control the light transmittance of the masks. A fine pattern smaller than the resolution of the exposure apparatus used in the test, a thin film having a different transmittance, or a thin film having the same transmittance and different thickness may be used.

As described above, in the present invention, the semiconductor layer pattern and the etch stop layer are formed by exposing the gate pads in a single photolithography process using a mask that can partially control the transmittance, while forming pixel electrodes or forming data wirings while forming gate wirings. By forming the protective layer pattern, the manufacturing process may be simplified to manufacture a thin film transistor substrate for a liquid crystal display, thereby reducing manufacturing cost. In addition, when the protective film or the etch stop layer is formed of the photosensitive organic insulating film, the step of using the photosensitive film may be omitted.

Claims (36)

Forming a conductive layer on the insulating substrate and patterning the conductive layer to form a gate line and a pixel electrode including a horizontal gate line, a gate electrode which is a part of the gate line, and a gate pad connected to the gate line to receive a scan signal from the outside; step, Stacking a gate insulating film, a semiconductor layer, and an etch stop insulating film sequentially covering the gate wiring; Patterning the etch stop insulating layer, the semiconductor layer, and the gate insulating layer to form a semiconductor layer pattern and a gate insulating layer pattern having a different size from that of the etch stop layer and at least the etch stop layer and having a first contact hole for exposing the gate pad. Forming step, Stacking the data wiring conductor layer and the protective film in sequence; Patterning the data wiring conductor layer and the passivation layer and extending in a vertical direction to intersect the gate line to define a pixel; a source electrode that is a part of the data line; and a pixel positioned opposite to the source electrode with respect to the gate electrode. Forming a data line and a passivation layer pattern including a drain electrode connected to the electrode and a data pad connected to the data line to receive an image signal from the outside; Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. In claim 1, And the conductor layer is formed of at least a first conductive film made of a transparent conductive material and a second conductive film positioned over the first conductive film. In claim 2, The gate line and the pixel electrode are formed of the first and second conductive layers, And removing the second conductive layer of the pixel electrode not covered by the passivation layer pattern and the gate insulating layer pattern after the data line and the passivation layer pattern are formed. In claim 3, Forming a buffer film between the first and second conductive films; And removing the buffer film together with removing the second conductive film. In claim 2, The gate wiring and the pixel electrode forming step may be formed by a photolithography process using a mask having a different transmittance of at least three regions. In claim 5, And forming a fine pattern on the mask in order to partially adjust the transmittance, and to form a fine pattern smaller than the resolution of a thin film having a different transmittance or a thin film having a different thickness or an exposure machine. In claim 2, The gate wiring and the pixel electrode forming step may be performed by a photolithography process using a photosensitive film. The gate wiring and the pixel electrode forming step may include Applying the photosensitive film on the second conductive film, Exposing and developing the photoresist to form a photoresist pattern including at least a first portion, a second portion having a first thickness thicker than the first portion, and a third portion having a second thickness thicker than the first thickness. , Etching the first and second conductive layers under the first portion using the photoresist pattern as an etching mask; Etching the second conductive layer of the second portion using the photoresist pattern of the third portion as an etching mask to complete the gate electrode of the pixel electrode of the first conductive layer and the first and second conductive layers; The manufacturing method of the thin film transistor substrate for liquid crystal display devices containing. In claim 2, Forming an auxiliary data pad in contact with the data pad on the same layer as the pixel electrode in the gate wiring and the pixel electrode forming step; The gate wiring, the pixel electrode, and the auxiliary data pad forming step may be performed by a photolithography process using a photoresist as an etch mask. The gate wiring and the pixel electrode forming step may include Applying the photosensitive film on the second conductive film, Exposing and developing the photoresist to form a photoresist pattern including at least a first portion, a second portion having a first thickness thicker than the first portion, and a third portion having a second thickness thicker than the first thickness. , Etching the first and second conductive layers under the first portion using the photoresist pattern as an etching mask; The second conductive layer under the second portion is etched using the photoresist pattern of the third portion as an etch mask to form the gate pad, the pixel electrode, the auxiliary data pad, and the first and second portions of the first conductive layer. A method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising the step of completing the gate line and the gate electrode of a conductive film. In claim 8, And the data line and the passivation layer pattern have a second contact hole for exposing the auxiliary data pad. In claim 9, And the data line and the passivation layer pattern are formed in the same shape. In claim 1, After forming the data line and the passivation layer pattern, etching the semiconductor layer pattern not covered by the passivation layer pattern to separate the semiconductor layer pattern under the data line adjacent to each other. Method of manufacturing a substrate. In claim 1, Forming an ohmic contact layer below the data line; Forming the ohmic contact layer, Stacking a metal film capable of forming silicide on the semiconductor layer; Forming a silicide on the semiconductor layer; Removing the metal film; and manufacturing a thin film transistor substrate for a liquid crystal display device. In claim 1, Forming an ohmic contact layer below the data line; And manufacturing the ohmic contact layer together in the data line forming step. In claim 1, The semiconductor pattern and the gate insulating layer pattern is formed in the same shape with each other manufacturing method of a thin film transistor substrate for a liquid crystal display device. In claim 1, And forming the etch stop layer, the semiconductor layer pattern, and the gate insulation layer pattern by a photolithography process using a mask having a transmittance of at least three regions. The method of claim 15, And forming a fine pattern on the mask in order to partially adjust the transmittance, and to form a fine pattern smaller than the resolution of a thin film having a different transmittance or a thin film having a different thickness or an exposure machine. In claim 1, Forming the etch stop layer, the semiconductor layer pattern and the gate insulating layer pattern, Applying a photoresist film on the etch stop insulating film; Exposing and developing the photosensitive film to form a photoresist pattern including at least a first part, a second part having a first thickness thicker than the first part, and a third part having a second thickness thicker than the first thickness; Etching the etch stop insulating film, the gate insulating film, and the semiconductor layer together with the second portion by using the photoresist pattern as an etch mask to complete the gate insulating film pattern and the semiconductor layer pattern; And etching the etch stop insulating layer using the third portion as an etch mask to complete the etch stop layer. In claim 1, The etch stop insulating film is formed of a photosensitive organic insulating material, The etching stop layer, the semiconductor layer pattern, and the gate insulating layer pattern forming step may include An etch stop insulating film including an at least first portion, a second portion having a first thickness thicker than the first portion, and a third portion having a second thickness thicker than the first thickness Forming a pattern, The gate insulating layer and the semiconductor layer of the first portion are etched together with the second portion by using the etch stop insulating layer pattern as an etch mask to complete the gate insulating layer pattern and the semiconductor layer pattern and to form the third portion. A method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising the step of completing the etch stop layer. In claim 1, The data wiring and the protective film pattern forming step may include Applying a photoresist film on the protective film, Exposing and developing the photosensitive film to form a photoresist pattern including at least a first part, a second part having a first thickness thicker than the first part, and a third part having a second thickness thicker than the first thickness; Etching the protective layer and the data wiring conductor layer of the first portion together with the second portion by using the photoresist pattern as an etching mask to complete the data wiring; And etching the passivation layer using the third portion as an etch mask to expose the data pad to complete the passivation pattern. In claim 1, A method of manufacturing a thin film transistor substrate for liquid crystal display device, wherein the protective film is formed of a photosensitive organic insulating film. In claim 1, The conductor layer is a method for manufacturing a thin film transistor substrate for a liquid crystal display device containing ITO or IZO. Stacking a conductive layer including a first conductive film made of at least a transparent conductive material on an insulating substrate and a second conductive film disposed on the first conductive film; The conductor layer is patterned by a photolithography process using a mask having a different transmittance of at least three regions, and is formed of the first and second conductive layers, and is connected to a gate line in a horizontal direction, a gate electrode that is part of the gate line, and the gate line. Forming a pixel electrode including only the first conductive layer and a gate line including a gate pad receiving a scan signal from an external source, Forming a gate insulating layer pattern covering the gate wiring; Forming a semiconductor layer pattern on the gate insulating layer pattern; Forming an etch stop layer on the semiconductor layer pattern; Stacking and patterning a data wiring conductor layer extending in the vertical direction to intersect the gate line to define a pixel, a source electrode that is a part of the data line, and is positioned opposite to the source electrode with respect to the gate electrode; Forming a data line including a drain electrode connected to the data line and a data pad connected to the data line to receive an image signal from the outside; Forming a protective layer pattern covering the data line; Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. The method of claim 22, Forming a buffer film between the first and second conductive films; And in the step of patterning the conductor layer, the buffer film is etched together with the second conductive film. The method of claim 22, The gate wiring and the pixel electrode forming step may be performed by a photolithography process using a photosensitive film. The gate wiring and the pixel electrode forming step may include Applying the photosensitive film on the second conductive film, Exposing and developing the photoresist film to form a photoresist pattern including at least a first portion, a second portion having a first thickness thicker than the first portion, and a third portion having a second thickness thicker than the first thickness. step, Etching the first and second conductive layers under the first portion using the photoresist pattern as an etching mask; Etching the second conductive layer of the second portion using the photoresist pattern of the third portion as an etching mask to complete the gate electrode of the pixel electrode of the first conductive layer and the first and second conductive layers; The manufacturing method of the thin film transistor substrate for liquid crystal display devices containing. The method of claim 22, Forming an auxiliary data pad in contact with the data pad on the same layer as the pixel electrode in the gate wiring and the pixel electrode forming step; The gate wiring, the pixel electrode, and the auxiliary data pad forming step may be performed by a photolithography process using a photoresist as an etch mask. The gate wiring and the pixel electrode forming step may include Applying the photosensitive film on the second conductive film, Exposing and developing the photoresist to form a photoresist pattern including at least a first portion, a second portion having a first thickness thicker than the first portion, and a third portion having a second thickness thicker than the first thickness. , Etching the first and second conductive layers under the first portion using the photoresist pattern as an etching mask; The second conductive layer under the second portion is etched using the photoresist pattern of the third portion as an etch mask to form the gate pad, the pixel electrode, the auxiliary data pad, and the first and second portions of the first conductive layer. A method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising the step of completing the gate line and the gate electrode of a conductive film. The method of claim 25, And the data line and the passivation layer pattern have a contact hole that exposes the auxiliary data pad. The method of claim 26, And the data line and the passivation layer pattern are formed in the same shape. The method of claim 22, After forming the data line and the passivation layer pattern, etching the semiconductor layer pattern not covered by the passivation layer pattern to separate the semiconductor layer pattern under the data line adjacent to each other. Method for producing a transistor substrate. The method of claim 22, Forming an ohmic contact layer made of silicide or doped amorphous silicon under the data line; And manufacturing the ohmic contact layer together in the data wiring forming step. The method of claim 22, The semiconductor pattern and the gate insulating layer pattern is formed in the same shape with each other manufacturing method of a thin film transistor substrate for a liquid crystal display device. The method of claim 22, And forming the etch stop layer, the semiconductor layer pattern, and the gate insulation layer pattern by a photolithography process using a mask having a transmittance of at least three regions. The method of claim 22, Forming the etch stop layer, the semiconductor layer pattern and the gate insulating layer pattern, Applying a photoresist film on the etch stop insulating film; Exposing and developing the photosensitive film to form a photoresist pattern including at least a first part, a second part having a first thickness thicker than the first part, and a third part having a second thickness thicker than the first thickness; The gate insulating layer pattern having the contact hole exposing the gate pad by using the photoresist pattern as an etch mask to etch the etch stop insulating layer of the first portion, the gate insulating layer and the semiconductor layer together with the second portion; Completing the semiconductor layer pattern; And etching the etch stop insulating layer using the third portion as an etch mask to complete the etch stop layer. The method of claim 22, The etch stop insulating film is formed of a photosensitive organic insulating material, Forming the etch stop layer, the semiconductor layer pattern and the gate insulating layer pattern, An etch stop insulating film including an at least first portion, a second portion having a first thickness thicker than the first portion, and a third portion having a second thickness thicker than the first thickness Forming a pattern, The gate insulating layer pattern and the semiconductor layer pattern of the first portion are etched together with the second portion by using the etch stop insulating layer pattern as an etch mask to complete the gate insulating layer pattern and the semiconductor layer pattern to expose the gate pad. A method of manufacturing a thin film transistor substrate for a liquid crystal display device, the method comprising: leaving the third portion to complete the etch stop layer. The method of claim 22, The data wiring and the protective film pattern forming step may include Applying a photoresist film on the protective film, Exposing and developing the photosensitive film to form a photoresist pattern including at least a first part, a second part having a first thickness thicker than the first part, and a third part having a second thickness thicker than the first thickness; Etching the protective layer and the data wiring conductor layer of the first portion together with the second portion by using the photoresist pattern as an etching mask to complete the data wiring; And etching the passivation layer using the third portion as an etch mask to expose the data pad to complete the passivation pattern. The method of claim 22, A method of manufacturing a thin film transistor substrate for a liquid crystal display device, wherein the protective film is formed of a photosensitive organic insulating film. The method of claim 22, The conductor layer is a method for manufacturing a thin film transistor substrate for a liquid crystal display device containing ITO or IZO.

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