KR100580398B1 - Thin film transistor substrate for liquid crystal display and manufacturing method thereof - Google Patents

Abstract

A gate wiring including a gate line, a gate pad, and a gate electrode is formed on the substrate, and a gate insulating film, a semiconductor layer, a contact layer, and a conductor layer are successively deposited, and a reflowable organic film is applied thereon. The organic layer pattern is formed by a patterning process using a mask, and the conductor layer and the contact layer are etched using the mask to form a contact layer pattern on the data line including the source electrode and the drain electrode, the data line and the data pad, and a lower portion thereof. . Next, the organic layer pattern is reflowed to form a protective layer covering the semiconductor layer between the source and drain electrodes and the edge of the data line, and then the semiconductor layer not covered by the protective layer is sequentially etched. Subsequently, the drain electrode, the gate pad, and the data pad are exposed by a photo process using a photoresist film, and then pixel electrodes, auxiliary gate pads, and auxiliary data pads connected thereto are formed.

Step, ITO, organic film, reflow, mask

Description

Thin film transistor substrate for liquid crystal display device and manufacturing method therefor {THIN FILM TRANSISTOR SUBSTRATE FOR LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD THEREOF}

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along the line II-II ′;

3A is a layout view illustrating a method of manufacturing a substrate for a liquid crystal display device according to a first embodiment of the present invention;

3B is a cross-sectional view taken along the line IIIb-IIIb ′ in FIG. 3A,

FIG. 4 is a cross-sectional view taken along line IIIb-IIIb 'in 3a, showing the next step in FIG. 3b;

5A is a layout view showing the next step of FIG. 4;

5B is a cross-sectional view taken along the line Vb to Vb ′ in FIG. 5A.

FIG. 6A is a layout view showing the next step of FIG. 5A;

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ in FIG. 6A;

7A is a layout view illustrating a method of manufacturing a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ in FIG. 7A;

8 is a cross-sectional view shown in the next step of FIG. 7B,

9A is a layout view showing the next step of FIG. 8;

FIG. 9B is a cross-sectional view taken along the line IXb-IXb 'of FIG. 9A;

10A is a layout view showing the next step of FIG. 9A,

FIG. 10B is a cross-sectional view taken along the line Xb-Xb 'in FIG. 10a.

The present invention relates to a thin film transistor substrate for a liquid crystal display device and a manufacturing method thereof.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. By controlling the amount of light transmitted.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on each of two substrates and switching a voltage applied to the electrode is generally used. The thin film transistor is generally formed on one of two substrates.

The substrate on which the thin film transistor is formed is generally manufactured through a photolithography process using a mask. At this time, in order to reduce the production cost, it is desirable to reduce the number of masks.

In one example for reducing the number of masks, a gate wiring is formed on a substrate, and then a gate insulating film, an amorphous silicon layer, an n + amorphous silicon layer, and a metal layer are sequentially stacked on the substrate, and the metal layer is patterned to form a data wiring, The n + amorphous silicon layer and the amorphous silicon layer are patterned in the same pattern as.

However, in this method, a severe step is formed because an undercut occurs and the three-layer film is formed in the same pattern while the n + amorphous silicon layer and the amorphous silicon layer are patterned in the same manner as the metal data wiring. The problem is that the covering film becomes weak.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of manufacturing a thin film transistor substrate for a liquid crystal display device, which reduces the number of masks and improves a weak structure of a protective film.

In order to achieve the above object, the present invention uses an organic film pattern that can be reflowed as an etching mask when forming data wires, reflows the organic film pattern to complete a protective film, and jumps the semiconductor layer out of the data wires. Form to come out.

According to the present invention, first, a gate line including a gate line and a gate electrode connected thereto is formed on an insulating substrate, the gate insulating layer, the semiconductor layer, and the data conductor layer are sequentially stacked and the organic layer pattern reflowable on the data conductor layer. To form. Next, the data conductor layer is etched using the organic layer pattern as a mask, and includes a data line crossing the gate line, a source electrode connected to the data line, and a drain electrode opposite to the source electrode with respect to the gate electrode. A data wiring is formed, and the organic film pattern is reflowed to form a protective film. Next, after etching the semiconductor layer exposed by the protective film as a mask, the protective film is patterned by a photolithography using a photosensitive film to expose the drain electrode to form a pixel electrode connected to the drain electrode.

In another manufacturing method according to the present invention, a gate wiring including a gate line and a gate electrode connected thereto is first formed on an insulating substrate, and the gate insulating film, the semiconductor layer, and the data conductor layer are sequentially stacked and reflowed on the data conductor layer. To form an organic film pattern. Next, the data conductor layer is etched using the organic layer pattern as a mask, and includes a data line crossing the gate line, a source electrode connected to the data line, and a drain electrode opposite to the source electrode with respect to the gate electrode. A data wiring is formed. Next, the organic layer pattern is reflowed to form a passivation layer covering the gate line between the data line and the neighboring data, and the semiconductor layer on the gate line is separated while exposing the drain electrode by the patterning process using the photosensitive layer. The semiconductor pattern not covered by the protective film is etched to complete the semiconductor pattern. Next, the drain electrode is exposed to form a pixel electrode connected to the drain electrode.

In this case, further comprising forming a contact layer therebetween to reduce the resistance between the data conductor layer and the semiconductor layer, after forming the data wiring, by removing the contact layer not covered by the data wiring source and drain Exposing the semiconductor layer between the electrodes.

On the other hand, the gate wiring further includes a gate pad connected to the gate line to receive a signal from the outside, and the data wiring further includes a data pad connected to the data line to receive a signal from the outside, and when the drain electrode is exposed. The method may further include exposing the gate pad and the data pad together. The method may further include forming the auxiliary gate pad and the auxiliary data pad in the same layer as the pixel electrode and connected to the gate pad and the data pad.

Then, the liquid crystal display according to an exemplary embodiment of the present invention and a manufacturing method thereof will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

As described above, in the present invention, an organic film pattern is formed as an etching mask when data wiring is formed, and a protective film is formed by reflowing the organic film pattern, thereby reducing the number of processes and improving the fragile structure due to the step of forming the protective film gently. can do.

A structure of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along the line II-II ′.

First, a gate made of a metal or a conductor such as aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta) or the like on the insulating substrate 10. Wiring is formed. The gate wiring is connected to the scan signal line or the gate line 22 extending in the horizontal direction and the gate line 22, and the gate pad 26 and the gate which receive the scan signal from the outside and transmit the scan signal to the gate line 22. A gate electrode 24 of the thin film transistor, which is a branch of the line 22; Here, the pixel electrode 84 to be described later and the gate line 22 overlap to form a storage capacitor that improves the charge storage capability of the pixel. When the storage capacitor is not sufficient, the storage electrode line to overlap the pixel electrode 82 to be described later. This may be added in the same layer as the gate wiring if necessary.

The gate wirings 22, 24, and 26 may be formed in a single layer, but may also be formed in a double layer or a triple layer. In the case of forming more than two layers, it is preferable that one layer is formed of a material having a low resistance and the other layer is formed of a material having good contact properties with other materials, and a double layer of Cr / Al (or Al alloy) or Al / Mo Bilayers are an example.

A gate insulating film 32 made of silicon nitride (SiN _x ) is formed on the gate wirings 22, 24, and 26 to cover the gate wirings 22, 24, and 26, and a gate pad 26 is formed on the gate insulating film 32. A contact hole 73 is formed which exposes.

A semiconductor pattern 44 made of a semiconductor such as hydrogenated amorphous silicon is formed on the gate insulating layer 32, and is heavily doped with n-type impurities such as phosphorus (P) on the semiconductor pattern 44. An ohmic contact layer pattern or an intermediate layer pattern 52, 54, 56, 58 made of amorphous silicon is formed.

On the contact layer patterns 52, 54, 56, and 58, a data line made of a conductive material such as Mo or MoW alloy, Cr, Al or Al alloy, and Ta is formed. The data line is a thin film transistor which is a branch of the data line 62 formed in the vertical direction, the data pad 68 connected to one end of the data line 62 to receive an image signal from the outside, and the data line 62. And a source electrode 64 of the thin film transistor, which is separated from the data lines 62, 64, and 68, and is located opposite the source electrode 64 with respect to the gate electrode 24 or the channel portion of the thin film transistor. The drain electrode 66 is also included.

The data lines 62, 64, 66, and 68 may be formed in a single layer like the gate lines 22, 24, and 26, but may be formed in a double layer or a triple layer. Of course, when forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials.

The contact layer patterns 52, 54, 56, and 58 lower the contact resistance between the semiconductor pattern 44 at the bottom thereof and the data lines 62, 64, 66, and 68 at the upper portion thereof, and the data lines 62. , 64, 66, 68). Here, the semiconductor pattern 44 is formed to protrude out of the upper data lines 62, 64, 66, and 68, and the contact layer patterns 54, 56 between the source electrode 64 and the drain electrode 66. Unlike), it is connected without disconnection to create a channel of a thin film transistor.

The passivation layer 74 is formed on the data line 62, 64, 66, 68 and the semiconductor layer 44 not covered by the data line in the same shape as the semiconductor layer 44. 66 and contact holes 71, 75 exposing the data pad 68. Here, the protective film 74 is made of an organic material such as acrylic that can be reflowed, and as shown in FIG.

On the passivation layer 74, a pixel electrode 84 that receives an image signal from the thin film transistor and generates an electric field together with the electrodes of the upper plate is formed. The pixel electrode 84 is made of a transparent conductive material such as indium tin oxide (ITO), and is physically and electrically connected to the drain electrode 66 through the contact hole 71 to receive an image signal. On the other hand, an auxiliary data pad 88 is formed on the data pad 68 through the contact hole 75, and an auxiliary gate pad 86 connected through the contact hole 73 is formed on the gate insulating layer 32. It is. These 86 and 88 are made of the same material as the pixel electrode 84 and are not essential to complement the adhesion between the pads 26 and 68 and the external circuit device and to protect the pads. Whether is optional.

Although transparent ITO is mentioned as an example of the material of the pixel electrode 84 here, an opaque conductive material may be used for a reflective liquid crystal display device.

Next, a method of manufacturing the liquid crystal display substrate according to the first embodiment of the present invention will be described in detail with reference to FIGS. 3A to 6B and FIGS. 1 to 2.

First, as illustrated in FIGS. 3A to 3B, a conductive layer such as a metal is deposited to a thickness of 1,000 kPa to 3,000 kPa by a sputtering method, and first, dry or wet etch using a mask to form a gate on the substrate 10. A gate wiring including a line 22, a gate pad 26, and a gate electrode 24 is formed.

Next, as shown in FIG. 4, the gate insulating film 32, the amorphous silicon layer 40 as the semiconductor, and the doped amorphous silicon layer as the contact layer are respectively 1,500 kPa to 5,000 kPa and 500 kPa to the chemical vapor deposition method. Continuous deposition at a thickness of 2,000 kPa, 300 kPa to 600 kPa.

Subsequently, a conductive layer such as a metal is deposited to a thickness of 1,500 Å to 3,000 Å by sputtering or the like, and then a reflowable organic film is applied thereon, followed by a patterning process using a data wiring mask, which is a second mask. The film patterns 72, 76 and 78 are formed. At this time, the organic film is a conventional organic insulating film, it is preferable to use a material that acts as a photosensitive resist that can be developed through exposure in a photographic process. Next, the conductive layer and the doped amorphous silicon layer which are not covered by the organic layer patterns 72, 76, and 78 are sequentially etched to constitute the data line 62, the source and drain electrodes 64, 66, and the data pad 68. The data lines and the contact layer patterns 52, 54, 56, and 58 under them are formed.

Next, as shown in FIGS. 5A and 5B, the organic film patterns 72, 74, and 78 are reflowed so that the organic film patterns are lightly flowed down to the part without the organic film, thereby forming the amorphous silicon between the source and drain electrodes 64 and 66. The semiconductor layer 40 which forms the protective film 74 which covers the layer 40, the data wirings 62, 64, 66, 68, and the contact layer patterns 52, 54, 56, 58, and is not covered by the protective film 74 is formed. Is etched to complete the semiconductor pattern 44.

In this case, the semiconductor pattern 44 is formed to protrude out of the data lines 62, 63, 64, and 66 in the same shape as the passivation layer 74.

6A and 6B, the passivation layer 74 and the gate insulating layer 32 are patterned by a patterning process using a photosensitive layer to expose the drain electrode 66, the gate pad 26, and the data pad 68. Contact holes 71, 73 and 75 are formed, respectively.

Finally, as shown in FIGS. 1 and 2, an ITO layer of 400 500 to 500 Å thickness is deposited and etched using a fourth mask to form the pixel electrode 84, the auxiliary gate pad 86, and the auxiliary data pad. Form 88.

As described above, in the present exemplary embodiment, the data line 62, 64, 66, and 68 and the contact layer patterns 52, 54, 56, and 58, the semiconductor pattern 44, and the passivation layer 74 under the same mask are used as one mask. The number of masks can be minimized by forming. The weak structure of the pixel electrode 84 formed thereon can be improved by forming the semiconductor pattern 44 so as to protrude out of the data lines 62, 64, 66, and 68, and by gently forming the passivation layer 74.

Although the semiconductor pattern 44 is formed by etching the amorphous silicon layer 40 exposed by the protective film 74 in the first embodiment of the present invention, the semiconductor pattern is not formed when the contact holes 71, 73, and 75 are formed. Alternatively, the holding electrode may be added to the same layer as the data line. Detailed description thereof will be described with reference to the second embodiment.

7A, 9A, and 10A are layout views illustrating a method of manufacturing a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIGS. 7B, 9B, and 10B are FIGS. 7A, 9A, and 10B. Are cross-sectional views taken along the lines VIIb-VIIb ', IXb-IXb', and X-Xb ', respectively, and FIG. 8 is a cross-sectional view of the next step of FIG. 7B.

As shown in Figs. 7A and 7B, the process of forming the gate wirings 22, 24 and 26, the data wirings 62, 64, 66 and 68 and the protective film 74 is similar to the first embodiment.

However, a holding electrode 67 is further formed on the same layer as the data lines 62, 64, 66, and 68, and a contact layer 57 is further formed below and the protective film 74 is also held. It is also added to the upper part of the electrode 67. In this case, the protective film 74 formed on the added sustain electrode 67 is newly formed on the gate wires 22 and 24 in the reflow step to cover most of the gate wires 22 and 24.

Subsequently, as shown in FIG. 8, the gate between the drain electrode 66, the data line 62, and the storage electrode 67 is disposed on the passivation layer 74 and the semiconductor layer 40 in a photolithography process using a third mask. A photoresist pattern 1000 is formed to expose the passivation layer 74 on the line 22, the data pad 68, and the storage electrode 67, the gate pad 26, and the semiconductor layer 40 on the pixel.

Next, the photoresist pattern 1000 is patterned with an etch mask, and as shown in FIGS. 9A and 9B, the gate pad 26, the data pad 68, the drain electrode 66, and the sustain electrode 67 are formed. The contact holes 71, 73, 75, and 70 exposing the light emitting holes are formed, and the openings 79 exposing the substrate 10 are formed in the pixel. At this time, when amorphous silicon, which is a semiconductor, remains on top of the gate line 22 and a parasitic channel is formed, data signals applied to neighboring data lines are distorted or leakage currents are generated. An opening 77 is formed between the holding electrode 67 and the data line 62 by separating the semiconductor layer 42 on the gate line 22 therebetween and exposing the gate insulating film 32.

Finally, as shown in Figs. 10A and 10B, similarly to the first embodiment, an ITO layer having a thickness of 400 kHz to 500 kHz is deposited and etched using a fourth mask to etch the pixel electrode 84 and the auxiliary gate pad 86. ) And auxiliary data pad 88. In this case, the pixel electrode 84 is formed to extend to the upper portion of the gate line 22 to be connected to the holding electrode 67 through the contact hole 70.

As described above, according to the present invention, in the method of manufacturing a thin film transistor substrate for a liquid crystal display device, the number of masks is formed by forming a protective film as a reflowed organic film, semiconductor patterning the protective film using a mask, or forming a semiconductor hole at the same time. It is possible to improve the fragile structure of the formed films while effectively reducing the

Claims (10)

Forming a gate wiring including a gate line and a gate electrode connected to the insulating substrate, Stacking a gate insulating film, Stacking a semiconductor layer on the gate insulating film, Stacking a conductor layer on the semiconductor layer; Forming an organic layer pattern reflowable on the conductor layer; Etching the conductor layer using the organic layer pattern as a mask to form a data line including a source electrode and a drain electrode separated from each other, and a data line connected to the source electrode; Reflowing the organic layer pattern to form the passivation layer covering the data line and covering the semiconductor layer between the source and drain electrodes and adjacent to an edge of the data line; Etching the semiconductor layer not covered by the passivation layer; Removing the portion of the passivation layer to expose the drain electrode, Forming a pixel electrode connected to the drain electrode Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. delete In claim 1, And the semiconductor layer is formed to protrude out of the data line. In claim 1, The gate line further includes a gate pad connected to the gate line to receive a signal from the outside, and the data line further includes a data pad connected to the data line to receive a signal from the outside, Etching the passivation layer and the gate insulating layer to expose the drain electrode to expose the gate pad and the data pad, And forming an auxiliary gate pad and an auxiliary data pad on the same layer as the pixel electrode and connected to the gate pad and the data pad. In claim 1, Forming an ohmic contact layer between the semiconductor layer and the conductor layer, And etching the contact layer that is not covered by the data line after the data line forming step. Forming a gate wiring including a gate line and a gate electrode connected to the insulating substrate, Stacking a gate insulating film covering the gate wiring; Stacking a semiconductor layer on the gate insulating film, Stacking a conductor layer on the semiconductor layer; Forming an organic layer pattern reflowable on the conductor layer; Etching the conductor layer using the organic layer pattern as a mask to form a data line including a source electrode and a drain electrode separated from each other by the same layer, and a data line connected to the source electrode; Reflowing the organic layer pattern to cover the data line, and to form a passivation layer covering the gate line between the source and drain electrodes, the semiconductor layer adjacent to the edge of the data line, and the data line adjacent to each other. step, Forming a photoresist pattern exposing the passivation layer on the gate line between the drain electrode and the data line adjacent to each other; Patterning the passivation layer to expose the drain electrode and separating the semiconductor layer over the gate line between the data lines adjacent to each other; Forming a pixel electrode connected to the drain electrode Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. In claim 6, The data line and the passivation layer are formed using a single mask. In claim 7, And the semiconductor layer is formed to protrude out of the data line. In claim 8, A storage electrode formed on the same layer as the data line and separated from the data line and overlapping the gate line; Exposing the holding electrode in the step of exposing the drain electrode; A method of manufacturing a thin film transistor substrate for a liquid crystal display device connecting the pixel electrode and the storage electrode. In claim 9, And patterning the semiconductor layer and the gate insulating layer together with exposing the drain electrode to expose the substrate of a pixel surrounded by the gate line and the data line.

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