KR102131191B1 - Array substrate for fringe field switching mode liquid crystal display device and Method of fabricating the same - Google Patents

Abstract

The present invention, the display area including a plurality of pixel areas each provided with a switching area and a gate wiring spaced a predetermined distance apart from the display area on the substrate having a pad portion defined outside thereof, and the switching area connected to the gate wiring Forming a gate electrode; Forming a gate insulating film on the entire surface of the substrate over the gate wiring and the gate electrode; A data line defining the pixel region crossing the gate wiring and forming a source electrode and a drain electrode spaced apart from the active layer and the ohmic contact layer sequentially stacked corresponding to the gate electrode in the switching region are formed on the gate insulating layer. And simultaneously forming a first protective layer covering the upper and side surfaces of the data wiring and the source and drain electrodes, respectively; Forming a common electrode and a second protective layer sequentially stacked over the first protective layer and the gate insulating layer and having a first hole exposing the first protective layer corresponding to the drain electrode; Removing the first protective layer exposed through the first hole to expose the drain electrode; A method of manufacturing an array substrate for a fringe field switching mode liquid crystal display, comprising forming a pixel electrode having a plurality of bar-shaped openings in contact with the drain electrode in each pixel region over the second protective layer, and An array substrate produced by this is provided.

Description

Array substrate for fringe field switching mode liquid crystal display device and Method of fabricating the same}

The present invention relates to an array substrate for a liquid crystal display device, and more particularly, to an array substrate for a fringe field switching mode liquid crystal display device having a structure capable of reducing the number of mask processes, and a method for manufacturing the same.

A liquid crystal display device (LCD) is a display device using optical anisotropy and polarization properties of liquid crystals, and is widely used in a display portion of a portable electronic device, a computer monitor, or a television.

Since the liquid crystal has an elongated molecular structure, it has orientation in orientation, and when placed in an electric field, the molecular alignment direction changes according to its size and direction.

Therefore, the liquid crystal display device includes a liquid crystal panel in which a liquid crystal layer is positioned between two substrates each having an electric field generating electrode, and artificially adjusts the arrangement direction of liquid crystal molecules through a change in an electric field generated between the two electrodes. Various images are displayed by changing the light transmittance.

In general, a liquid crystal display device includes an array substrate on which a plurality of wires, switching elements, and pixel electrodes are formed, and a color filter substrate on which a color filter and a common electrode are formed, and the liquid crystal molecules between the two substrates are between the pixel electrode and the common electrode. It is driven by an induced electric field, ie, a vertical electric field in a direction perpendicular to the substrate.

However, the method of driving the liquid crystal by the vertical electric field has a problem that the viewing angle characteristics are not excellent.

In order to overcome this problem, a transverse electric field type liquid crystal display device has been proposed.

In a transverse electric field type liquid crystal display, a pixel electrode having a bar shape and a common electrode are alternately formed on the same substrate, and a horizontal electric field in a direction parallel to the substrate is induced between the two electrodes.

Therefore, the liquid crystal molecules are driven by a horizontal electric field and move in a direction parallel to the substrate, and such a transverse electric field type liquid crystal display device has improved viewing angle characteristics.

However, a transverse electric field type liquid crystal display device having such a configuration has a disadvantage of low aperture ratio and low transmittance.

Accordingly, a fringe field switching mode LCD for driving liquid crystal by a fringe field has been proposed in order to improve aperture and transmittance deterioration, which are disadvantages of the transverse electric field type liquid crystal display.

1 is a cross-sectional view of one pixel region in a display area of a conventional fringe field switching mode liquid crystal display device, and FIG. 2 shows a gate pad electrode in a conventional fringe field switching mode liquid crystal display array substrate. It is a cross-sectional view of the pad portion provided.

As illustrated, a gate wiring (not shown) and a gate electrode 5 and a gate pad electrode 6 connected to one end of the gate wiring (not shown) are formed on the substrate 1, and these components A gate insulating film 10 is formed on the entire surface of the gate.

A semiconductor layer 20 is formed on the gate insulating layer 10 corresponding to the gate electrode 5, and source and drain electrodes 33 and 36 spaced apart from each other are formed on the gate insulating layer 10.

In addition, a data line 30 defining a pixel region P by crossing the gate line (not shown) is formed on the gate insulating layer 10 and is connected to one end of the data line electrode (not shown). Is formed.

In addition, a first protective layer 40 made of an inorganic insulating material and a second protective layer 50 made of an organic insulating material and having a flat surface are formed on the data wiring 30 and the source and drain electrodes 33 and 36. Is formed.

A common electrode 60 made of a transparent conductive material is formed on the second protective layer 50 in correspondence to a display area displaying an image. In the pad portion PA, the gate and data pad electrodes 6, A first auxiliary gate and a data pad electrode 62 (not shown) that are in contact with each other are formed.

A third protective layer 65 made of an inorganic insulating material is provided on the common electrode 60, the first auxiliary gate, and the data pad electrode 62 (not shown). At this time, the third protective layer 65, the second protective layer 50 and the first protective layer 40 is provided with a drain contact hole 68 exposing the drain electrode 36 of the thin film transistor Tr. Is becoming.

In addition, the third protective layer 65 is made of a transparent conductive material and is in contact with the drain electrode 36 through the drain contact hole 68, and a pixel electrode 70 is formed for each pixel region P Each of the pixel electrodes 70 is provided with a plurality of openings (op) having a bar shape spaced apart at a predetermined interval within each pixel area (P).

Further, in the pad portion PA, the second auxiliary gate and the data pad electrode 72 (not shown) are formed in contact with the first auxiliary gate and the data pad electrode 62 (not shown), respectively.

In order to form the array substrate 1 for a conventional fringe field switching mode liquid crystal display device having such a configuration, a total of seven mask processes are performed.

Briefly, a method of manufacturing an array substrate for a conventional fringe field switching mode liquid crystal display device having the above-described configuration will be briefly described.

First, a first mask process is performed to form a gate wiring (not shown) and a gate electrode 5 on the substrate 1, and at the same time, a gate pad electrode 6 connected to one end of the gate wiring (not shown) ).

Thereafter, a gate insulating layer 10 is formed over the gate wiring (not shown), the gate electrode 5 and the gate pad electrode 6.

Next, a second mask process is performed to form a data wire 30 and a data pad electrode (not shown) connected to one end of the data line 30 to the upper portion of the gate insulating film 10, and at the same time, a semiconductor corresponding to the gate electrode 5 Source and drain electrodes 33 and 36 spaced apart from each other are formed on the layer 20 and the semiconductor layer 20.

Then, after forming the first protective layer 40 made of an inorganic insulating material on the data wiring 30, the data pad electrode (not shown), and the source and drain electrodes 33 and 36, a third mask process is performed. By patterning the first passivation layer 40 and the gate insulating layer 10, a first pad contact hole ch1 exposing the gate and data pad electrodes 6 (not shown) is formed.

Next, a second protective layer 50 having a flat surface made of an organic insulating material is formed on the first protective layer 40, and a fourth mask process is performed on the second protective layer 50. A first pad layer forming a second pad contact hole (ch2) exposing the gate and data pad electrodes, and simultaneously exposing the first protective layer 40 formed thereon to the drain electrode 36 A hole (not shown) is formed.

Next, after forming a transparent conductive material layer (not shown) on the second protective layer 50, a fifth mask process is performed to pattern the second protective layer 50 for the display area DA. The first auxiliary gate and the data pad electrode 62 (not shown) respectively forming the common electrode 60 and simultaneously contacting the gate and data pad electrode 6 (not shown) through the second pad contact hole ch2. ).

Thereafter, a third protective layer 65 is formed on the front surface of the common electrode 60 and the first auxiliary gate and data pad electrode 62 (not shown), and a sixth mask process is performed to pattern the same. A drain contact hole 68 exposing the drain electrode 36 is formed by removing the first protective layer 40 in a portion corresponding to a first hole (not shown), and at the same time, the first auxiliary gate and data A third pad contact hole ch3 exposing the pad electrode 62 (not shown) is formed.

Next, a seventh mask process is performed to contact the drain electrode 36 through the drain contact hole 68 for each pixel region P over the third protective layer 65, and to be spaced apart at a predetermined interval (bar) ) Form a pixel electrode 70 having a plurality of openings (op), and at the same time, the first auxiliary gate and the data pad electrode 62 (not shown) through the third pad contact hole ch3 in the pad portion ) To form the second auxiliary gate and the data pad electrode 72 (not shown), respectively, to complete the array substrate 1.

On the other hand, the mask process is essential for the manufacture of the array substrate, but includes a unit process such as deposition, exposure, development, etching, etc., and when the mask process is performed once, the material cost is increased. Proceeding one more time, the productivity per unit hour decreases, which is a factor that decreases the price competitiveness of the product.

Therefore, as described above, a conventional fringe field switching mode liquid crystal display array substrate 1 completed by performing seven mask processes is causing a problem that its manufacturing method needs to be improved in order to improve the price competitiveness of the product. .

The present invention has been devised to solve the problems of the array substrate for the conventional fringe field switching mode liquid crystal display device, reducing the number of masking processes and reducing the material cost while improving productivity per unit time to finally improve the price competitiveness of the product. Let's do it for that purpose.

A method of manufacturing an array substrate for a fringe field switching mode liquid crystal display device according to an embodiment of the present invention for achieving the above-described object includes: a display area including a plurality of pixel areas each provided with a switching area and an outer side thereof Forming a gate wiring spaced a predetermined distance from the display area on a substrate on which a pad portion is defined, and a gate electrode connected to the gate wiring in the switching area; Forming a gate insulating film on the entire surface of the substrate over the gate wiring and the gate electrode; A data line defining the pixel region crossing the gate wiring and forming a source electrode and a drain electrode spaced apart from the active layer and the ohmic contact layer sequentially stacked corresponding to the gate electrode in the switching region are formed on the gate insulating layer. And simultaneously forming a first protective layer covering the upper and side surfaces of the data wiring and the source and drain electrodes, respectively; Forming a common electrode and a second protective layer sequentially stacked over the first protective layer and the gate insulating layer and having a first hole exposing the first protective layer corresponding to the drain electrode; Removing the first protective layer exposed through the first hole to expose the drain electrode; And forming a pixel electrode having a plurality of bar-shaped openings in contact with the drain electrode in each pixel region over the second protective layer.

At this time, a source line and a drain electrode spaced apart from an active layer and an ohmic contact layer sequentially stacked corresponding to the gate electrode in the switching area, and a data line defining the pixel area over the gate insulating layer and crossing the gate line. Forming, and simultaneously forming the first protective layer covering each of the top and side surfaces of the data wiring and the source and drain electrodes only, a pure amorphous silicon layer sequentially over the gate insulating film and the impurity amorphous Forming a silicon layer, a first metal layer and a photoacrylic layer; Patterning the photoacrylic layer to form a photoacrylic pattern only on portions where the data wiring and source and drain electrodes are to be formed; The source and drain electrodes spaced apart from the data wiring and the ohmic contact layer below the source and drain electrodes by removing the first metal layer exposed to the outside of the photoacrylic pattern and the impurity amorphous silicon layer positioned under the photoacrylic pattern Forming; The first heat treatment is performed to reflow the photoacrylic pattern to cover the side surfaces of the data wiring and the source and drain electrodes, and at the same time to cover the pure amorphous silicon layer in a spaced area between the source and drain electrodes. Forming the first protective layer having; And forming the active layer by removing the pure amorphous silicon layer exposed outside the first protective layer by dry etching.

The dry etching is characterized in that a side end of the active layer forms an undercut shape with respect to the first protective layer by performing an over-etching.

And after forming the active layer, a second heat treatment is performed on the first protective layer to reflow the first protective layer so that the first protective layer covers a side end of the active layer.

In addition, a side surface of the common electrode exposed to correspond to the first hole by reflowing the second protective layer by performing a third heat treatment before the step of forming the pixel electrode having the bar-shaped opening And covering the second protective layer.

The forming of the gate wiring may include forming a gate pad electrode connected to the gate wiring and a data pad electrode connected to the data wiring on the pad portion, and exposing the first protective layer. The step of forming a common electrode having a hole and a second protective layer is such that a second hole exposing the gate insulating layer corresponding to the gate and data pad electrodes is provided and the first end of the data wiring is provided. A third hole exposing the protective layer is provided, and removing the gate insulating layer corresponding to the second hole to form a pad contact hole exposing the gate and data pad electrodes, the first hole The step of removing the first protective layer exposed through to expose the drain electrode may include removing a first protective layer exposed through the third hole to expose a wire contact hole exposing one end of the data wiring. The forming of the pixel electrode may include forming an auxiliary gate pad electrode contacting the gate pad electrode through the pad contact hole, and simultaneously forming the data through the pad contact hole and the wiring contact hole. And forming an auxiliary data pad electrode in contact with the pad electrode and the data wiring at the same time.

The array substrate for a fringe field switching mode liquid crystal display device according to an embodiment of the present invention has a predetermined distance between the display area including a plurality of pixel areas each having a switching area and the display area on the substrate on which a pad portion is defined outside. A gate electrode formed spaced apart and connected to the gate wire in the switching region; A gate insulating film formed on the entire surface of the substrate over the gate wiring and the gate electrode; A source electrode and a drain electrode spaced apart from the active layer and the ohmic contact layer sequentially stacked corresponding to the gate electrode in the data wiring and the switching region formed by defining the pixel region by intersecting the gate wiring over the gate insulating layer; A drain contact hole that covers the top and side surfaces of the data wiring and the source and drain electrodes, and simultaneously covers the active layer exposed between the source and drain electrodes, and exposes its surface to the central portion of the drain electrode. The first protective layer is provided and formed; A common electrode formed with a first opening for the drain contact hole over the first protective layer and the gate insulating film; A second protective layer formed over the common electrode and covering a side surface of the common electrode corresponding to the first opening; A pixel electrode formed in each pixel region over the second protective layer and contacting the drain electrode through the drain contact hole and having a plurality of bar-shaped second openings, wherein the first protective layer is the It is characterized in that it is formed only in the display area and in the switching area.

At this time, the second protective layer is characterized in that it is made of photoacrylic.

In addition, a gate pad electrode and an island-type data pad electrode connected to one end of the gate wiring are formed on the layer where the gate wiring is formed on the pad portion, and the gate and data pad electrodes are provided on the gate insulating layer and the second protective layer. Each of the pad contact holes is exposed, and the gate insulating layer and the first and second protective layers are provided with wiring contact holes exposing one end of the data wiring corresponding to one end of the data wiring. An auxiliary gate pad electrode contacting the gate pad electrode through the pad contact hole, and an auxiliary data pad electrode contacting the data pad electrode and the data wire through the pad contact hole and the wiring contact hole at the same time over the protective layer. Characterized in that formed, wherein the common electrode is formed to extend to the pad portion, the pad contact hole and the wiring contact hole provided in the second protective layer is removed, a third opening is provided, and the third opening Is larger than the pad contact hole and the wiring contact hole provided in the second protective layer, and a side surface of the common electrode exposed through the third opening is covered by the second protective layer.

The array substrate for the fringe field switching mode liquid crystal display device according to the present invention is manufactured through a total of four mask processes, thereby reducing the material cost by reducing the mask process three times compared to the conventional method for manufacturing the fringe field switching mode liquid crystal display array substrate. At the same time, it has the effect of improving the productivity per unit time and finally improving the price competitiveness of the product.

In addition, the array substrate for the fringe field switching mode liquid crystal display device according to the present invention minimizes parasitic capacitance generated due to the overlapping of the data wiring and the common electrode by forming a first protective layer made of a photoacrylic material for the data wiring. For each pixel area, the first protective layer made of the photoacrylic material is removed, thereby effectively preventing a reduction in transmittance due to the formation of the first protective layer.

1 is a cross-sectional view of one pixel area in a display area of an array substrate for a conventional fringe field switching mode liquid crystal display device.
2 is a cross-sectional view of a pad portion provided with a gate pad electrode in an array substrate for a conventional fringe field switching mode liquid crystal display device.
3A to 3L are cross-sectional views of manufacturing steps for one pixel area in a display area in an array substrate for a fringe field switching mode liquid crystal display device according to an embodiment of the present invention.
4A to 4L are cross-sectional views of manufacturing steps for a gate pad electrode pad in an array substrate for a fringe field switching mode liquid crystal display device according to an embodiment of the present invention.
5A to 5L are cross-sectional views of manufacturing steps for a portion where one end of a data line is located and a pad portion on which a data pad electrode is formed in an array substrate for a fringe field switching mode liquid crystal display device according to an embodiment of the present invention.

Hereinafter, a method of manufacturing an array substrate for a fringe field switching mode liquid crystal display device according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings.

3A to 3L are cross-sectional process steps of one pixel area in a display area in an array substrate for a fringe field switching mode liquid crystal display device according to an embodiment of the present invention, and FIGS. 4A to 4L are embodiments of the present invention A cross-sectional view of a manufacturing step for a pad portion in which a gate pad electrode is formed in an array substrate for a fringe field switching mode liquid crystal display device according to FIGS. 5A to 5L are used for a fringe field switching mode liquid crystal display device It is a manufacturing step-by-step process sectional view of a portion in which one end of the data wiring is formed and a pad portion in which the data pad electrode is formed in the array substrate. In this case, for convenience of description, a portion in which the thin film transistor Tr as a switching element is formed in each pixel area P is defined as a switching area TrA.

First, as shown in FIGS. 3A, 4A, and 5A, a transparent insulating substrate 101, for example, a metal material having low-resistance properties on a glass substrate or a plastic material substrate having flexible properties, for example First having a single or multi-layer structure by depositing one or more materials selected from aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo), and molybdenum alloy (MoTi) A metal layer (not shown) is formed.

Subsequently, the first metal layer (not shown) is patterned by performing a mask process including unit processes such as application of photoresist, exposure using an exposure mask, development of exposed photoresist, etching and stripping, etc. A plurality of gate wires (not shown) extending in a direction and spaced apart at regular intervals are formed, and further, gate electrodes 105 connected to the gate wires (not shown) are formed in each of the switching regions TrA.

At the same time, in the pad portion PA, a gate pad electrode 107 connected to one end of the gate wiring (not shown) is formed, and further, a data pad electrode connected to one end of the data wiring (130 in FIG. 3L). (108) is formed. At this time, the data pad electrode 108 is shown as an example that is formed on the same layer on which the gate pad electrode 107 is formed, but the data pad electrode 108 is a layer on which data wiring (130 of FIG. 3L) is formed later. Directly connected to one end of the data wiring (130 in FIG. 3L) may be formed.

Next, as shown in FIGS. 3B, 4B, and 5B, inorganic insulation is formed on the front surface of the substrate 101 over the gate wiring (not shown), the gate electrode 105, and the gate and data pad electrodes 107, 108. The gate insulating layer 110 is formed by depositing a material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx).

Thereafter, a pure amorphous silicon layer 112 and an impurity amorphous silicon layer 115 are continuously formed on the gate insulating layer 110.

And the impurity amorphous silicon layer 115 on the low resistance metal material, for example, aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo), molybdenum alloy (MoTi) selected one Alternatively, a second metal layer 119 having a single-layer or multi-layer structure is formed by depositing two or more materials.

The photoacrylic layer 139 is formed by coating the photoacrylic on the second metal layer 119 continuously.

Next, next, as shown in FIGS. 3C, 4C, and 5C, the source is spaced apart from the data wiring (130 in FIG. 3L) by patterning by performing a mask process on the photoacrylic layer (139 in FIG. 3C). And drain electrodes (133 and 136 in FIG. 3L) are left only for the portion to be formed, and all other portions are removed.

At this time, the photoacrylic layer (139 in FIG. 3C) remaining without being removed on the second metal layer 119 forms the first protective layer 140.

Next, as illustrated in FIGS. 3D, 4D, and 5D, the second metal layer exposed outside the first protective layer 140 using the first protective layer 140 as an etch-prevention mask (FIG. 3C) In step 119), a wet line using an etchant is removed to form a data line 130 that crosses the gate line (not shown) to define the pixel area P, and at the same time, in the switching area TrA. Source and drain electrodes 133 and 136 having a shape spaced apart from each other are formed on the gate electrode 105.

At this time, in the current state, the first protective layer 140 is formed to be located only above the data wiring 130 and the source and drain electrodes 133 and 136, so that the data wiring 130 and the source and drain electrodes are formed. Each side (133, 136) is exposed.

On the other hand, in the drawing, the data wiring 130 and the source electrode 133 appear to be formed spaced apart, but each of the source electrode 133 and the data wiring 130 forms a state connected to each other.

Thereafter, the impurity amorphous silicon layer (115 in FIG. 3C) exposed outside the data wiring 130 and the source and drain electrodes 133 and 136 is dry-etched to remove the pure amorphous silicon layer 112. Expose.

At this time, the impurity amorphous silicon layer (115 in FIG. 3C) remaining under the source and drain electrodes 133 and 136 in each switching region TrA forms an ohmic contact layer 116. In addition, due to the characteristics of the manufacturing process, the impurity amorphous silicon layer (115 in FIG. 3C) remains in the lower portion of the data wiring 130 to form the first dummy pattern 118.

Next, as shown in FIGS. 3E and 4E and 5E, the first protective layer 140 in the state where the pure amorphous silicon layer 112 is exposed to the outside by forming the ohmic contact layer 116 By performing a first heat treatment process for the reflow (reflowing) to form a form that covers both sides of the data wiring 130, and at the same time, the source and drain electrodes (133, 136) for each Cover both sides completely.

At this time, the first heat treatment process is to ensure that the first protective layer 140 has a sufficient time and reflow, pure amorphous silicon exposed between the source and drain electrodes (133, 136) in each switching region (TrA) It is characterized by covering the layer 112 completely.

That is, the first protective layer 140 is reflowed by the first heat treatment process, so that its height is reduced by a predetermined amount and covers the side surfaces of the source and drain electrodes 133 and 136, and at the same time, the source and drain electrodes ( 133, 136) to correspond to the separation region between the top of the amorphous silicon layer 112 positioned at the top to achieve a state of complete coverage.

At this time, in the portion excluding each of the switching regions TrA, the pure amorphous silicon layer 112 is still exposed.

Next, as shown in FIGS. 3F, 4F, and 5F, dry etching is performed on the pure amorphous silicon layer (112 of FIG. 3E) exposed outside the reflowed first protective layer 140. By removing, the gate insulating layer 110 is exposed.

In this case, the dry etching for removing the pure amorphous silicon layer proceeds with over-etching, so that the portions remaining at the bottom of the first reflowed first protective layer 140 are both ends of the first protective layer 140. Based on the etched a predetermined width further to the inside to form an undercut form below the first protective layer 140.

The over-etching of the pure amorphous silicon layer (112 of FIG. 3E) exposed between the first protective layers 140 to form an undercut shape with respect to the first protective layer 140, in particular, the switching region ( In the case of forming a structure in which the pure amorphous silicon layer (112 in FIG. 3E) is exposed on both side ends of the source and drain electrodes 133 and 136 in TrA), the phenomenon of wave noise increase may occur, so suppress it. It is for sake.

However, since the width of the pure amorphous silicon layer (112 of FIG. 3E) exposed to the outside of both ends of the source and drain electrodes 133 and 136 is substantially small, it is not necessary to perform excessive etching.

In the drawing, as an example, the over-etching is performed when the dry etching of the pure amorphous silicon layer (112 of FIG. 3E) is performed.

On the other hand, the pure amorphous silicon layer (112 in FIG. 3E), which is hidden by the first protective layer 140 reflowed in each switching region TrA and remains below it, forms the active layer 113, and the data The pure amorphous silicon layer (112 in FIG. 3E) positioned under the wiring 130 and more precisely below the first dummy pattern 118 forms the second dummy pattern 115.

At this time, the active layer 113 sequentially stacked in each switching region TrA and the ohmic contact layer 116 spaced apart therefrom form the semiconductor layer 114, and the gate electrode 105 and the gate insulating film ( 110) and the semiconductor layer 114 and the source and drain electrodes 133 and 136 spaced apart from each other form a thin film transistor Tr as a switching element.

Next, as shown in FIGS. 3G and 4G and 5G, the second heat treatment process is performed while the pure amorphous silicon layer (112 of FIG. 3E) exposed outside the first protective layer 140 is removed. By performing the second reflow of the first protective layer 140, the first protective layer 140 completely covers the side surfaces of the active layer 113 and the second dummy pattern 115.

Thus, through the second reflow of the first passivation layer 140 through the second heat treatment process, the first passivation layer 140 forms the side surfaces of the active layer 113 and the second dummy pattern 115. The purpose of forming the completely covered shape is to prevent the common electrode (150 in FIG. 3L) and a side end of the active layer 113 from coming into contact with each other.

Meanwhile, in the second reflow of the first protective layer 140 through the second heat treatment process, the pure amorphous silicon layer (112 in FIG. 3E) is over-etched and the first protective layer 140 is If it forms an undercut, it may be omitted. This is because when the active layer 113 forms an undercut shape with respect to the first protective layer 140, contact with a common electrode (150 in FIG. 3L) formed later may be suppressed.

In the drawing, in order to more stably suppress the contact between the common electrode (150 in FIG. 3L) and the side end of the active layer 113 by the subsequent process progress, in the state in which the pure amorphous silicon layer (112 in FIG. 3E) is overetched It was shown as an example that further proceeded to the second heat treatment process.

Next, as shown in FIGS. 3H and 4H and 5H, a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) is deposited on the first protective layer 140. To form a first transparent conductive material layer (not shown) on the front surface of the substrate 101, and subsequently to an inorganic insulating material such as silicon oxide (SiO ₂ ) or nitride over the first transparent conductive material layer (not shown) An inorganic insulating material layer (not shown) is formed on the entire surface of the substrate 101 by depositing silicon (SiNx).

Subsequently, a photosensitive material is coated on the inorganic insulating material layer (not shown) to form a photosensitive material layer (not shown), and then a process of exposing and developing it is performed to perform photomasking on the inorganic insulating material layer (not shown). The material pattern 191 is formed.

Subsequently, the display area is formed by etching and patterning the inorganic insulating material layer (not shown) exposed outside the photosensitive material pattern 191 and the first transparent conductive material layer (not shown) positioned below the photosensitive material pattern 191. In (DA), a common electrode 150 is formed over the gate insulating layer 110, and at the same time, a second protective layer 160 is formed over the common electrode 150.

At this time, the second protective layer 160 and the common electrode 150 are removed from the portions corresponding to the drain electrode 136 in each of the switching regions TrA, thereby exposing the first protective layer 140. A second hole exposing the gate insulating layer 110 by removing portions corresponding to each of the gate pad electrode 107 and the data pad electrode 108 in the pad portion PA, provided with one hole hl1 (hl2) is provided, and a third hole hl3 exposing the first protective layer 140 is also provided at one end of each data line 130.

In this case, the inorganic insulating material layer (not shown) and the first transparent conductive material layer (not shown) are simultaneously or sequentially etched and patterned by the same mask process to form the common electrode 150 and the second protective layer 160. In the current state, it is characterized by having the same shape in a plane.

Meanwhile, a portion of the common electrode 150 formed on the pad portion PA, more precisely, a portion formed outside the display area DA does not substantially function as the common electrode 150, so the third dummy pattern 151 It becomes.

Next, as shown in FIGS. 3i, 4i, and 5i, dry etching is performed while the photosensitive material pattern 191 remains on the second protective layer 160 to the pad portion PA. Thereby, by removing the gate insulating layer 110 exposed through each of the second holes hl2, a pad contact hole pch1 exposing the gate and data pad electrodes 107 and 108 is formed.

Next, as shown in FIGS. 3J and 4J and 5J, the second protective layer 160 is removed by proceeding with stripping of the photosensitive material pattern (191 in FIG. 3I) remaining on the second protective layer 160. ) Is exposed.

Thereafter, by performing a third heat treatment process to reflow the second protective layer 160, each switching region TrA may include the first transparent conductive material exposed through the first hole hl1 in each switching region TrA. The side surface of the common electrode 150 is covered.

At the same time, in the pad portion PA, the side surface of the third dummy pattern 151 exposed through the first hole hl1 or the pad contact hole pch1 is covered, and the data wiring 130 is In the portion where the end is located, the side surface of the common electrode 150 exposed through the third hole hl3 and the side surface of the third dummy pattern 151 are covered.

In this case, the first protective layer 140 exposed through the first hole hl1 and the third hole hl3 and the gate and data pad electrodes 107 and 108 exposed through the pad contact hole pch1 ) Is characterized in that the exposed state with respect to the first hole hl1 and the third hole hl3 and the pad contact hole pch1 is maintained even when the second protective layer 160 is reflowed.

Next, as shown in FIGS. 3K, 4K, and 5K, the reflowed second protective layer 160 is etch-prevented and masked through the first hole hl1 and the third hole hl3, respectively. By removing the exposed first protective layer 140 by dry etching, a drain contact hole dch exposing the drain electrode 136 in each switching region TrA is formed, and the data wiring is performed. A wiring contact hole lch is formed in a portion where one end of 130 is located.

At this time, the second protective layer 160 made of an inorganic insulating material and the first protective layer 140 made of photoacrylic are completely different materials, and since the reaction gas used for dry etching for patterning them is different, the second protective layer 160 is used. For the dry etching for patterning of the first protective layer 140, the second protective layer 160 is not affected at all.

Next, as shown in FIGS. 3L, 4L, and 5L, the second protective layer 160 on the substrate 101 is provided with a drain contact hole dch overlapping the first hole hl1. A second transparent conductive material layer (not shown) is formed by depositing a conductive material, for example, indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) on the entire surface of the substrate 101.

Thereafter, the second transparent conductive material layer (not shown) is formed by having a plate shape for each pixel region P by patterning by performing a mask process, and the drain electrode 136 is formed through the drain contact hole dch. ), and form a pixel electrode 170 having a plurality of openings (op) in a bar spaced at a predetermined interval within each pixel area (P).

At the same time, in the pad portion PA, the present invention is implemented by forming auxiliary gates and data pad electrodes 172 and 174 respectively contacting the gate and date pad electrodes 107 and 108 through each pad contact hole pch1. The array substrate 101 for a fringe field switching mode liquid crystal display device according to an example is completed.

In this case, the auxiliary data pad electrode 174 in contact with the data pad electrode 108 is formed to extend to a portion where one end of the data wire 130 is formed, so that the data wiring is performed through the wiring contact hole (lcd). It is characterized in that it is formed to contact one end of (130).

On the other hand, although not shown in the drawing, when the data pad electrode 108 is formed directly connected to one end of the data wire 130 on the same layer on which the data wire 130 is formed, the drain electrode 136 is In order to achieve the same configuration as the formed portion, that is, in the step of forming the drain contact hole (dch), the first protective layer covering the data pad electrode is removed to form a pad contact hole exposing the data pad electrode, and the pixel electrode In the step of forming 170, it may be completed by forming an auxiliary data pad electrode contacting the data pad electrode through the pad contact hole.

The array substrate 101 for a fringe field switching mode liquid crystal display device according to an embodiment of the present invention by the above-described method can be manufactured through a total of four mask processes, so that an array substrate for a conventional fringe field switching mode liquid crystal display device ( Three mask processes can be omitted compared to the manufacturing method of 1) in FIG. 1.

Accordingly, the productivity per unit time of the fringe field switching mode liquid crystal display device array substrate 101 is improved, and at the same time, the manufacturing cost is reduced by reducing the material cost.

Furthermore, as the first protective layer 140 made of photoacrylic material is formed on the data wiring 130, the parasitic capacitance generated due to the overlapping of the data wiring 130 and the common electrode 150 is minimized, and at the same time, each pixel area is minimized. For the first protective layer 140 of the photoacrylic material is removed, there is an effect of fundamentally preventing a reduction in transmittance due to the formation of the first protective layer 140.

The present invention is not limited to the above-described embodiment, and various changes and modifications are possible without departing from the spirit of the present invention.

101: (array) substrate
105: gate electrode
110: gate insulating film
112: amorphous silicon layer
116: ohmic contact layer
118: first dummy pattern
130: data wiring
133: source electrode
136: drain electrode
140: first protective layer
DA: Display area
P: Pixel area
TrA: switching area

Claims (13)

Forming a gate wiring connected to the gate wiring in the switching region and a gate wiring spaced apart at a predetermined distance from the display region on the substrate where a pad region is defined outside the display region including a plurality of pixel regions each provided with a switching region. A step of doing;
Forming a gate insulating film on the entire surface of the substrate over the gate wiring and the gate electrode;
Sequentially forming a pure amorphous silicon layer, an impurity amorphous silicon layer, a first metal layer on the front surface of the substrate over the gate insulating film, and forming a first protective layer on the first metal layer;
Etching the impurity amorphous silicon layer and the first metal layer by the first protective layer to form a data wiring, an ohmic contact layer, a source electrode and a drain electrode;
Covering the separation regions of the source and drain electrodes, side surfaces of the data wiring, and side surfaces of the source and drain electrodes by reflowing the first protection layer by performing a first heat treatment on the first protection layer;
Forming an active layer by etching the pure amorphous silicon layer by the reflowed first protective layer;
Performing a second heat treatment on the first protective layer to reflow the first protective layer so that the first protective layer covers a side end of the active layer;
Forming a common electrode and a second protective layer sequentially stacked over the first protective layer and the gate insulating layer and having a first hole exposing the first protective layer corresponding to the drain electrode;
Removing the first protective layer exposed through the first hole to expose the drain electrode;
And forming a pixel electrode having a plurality of bar-shaped openings in contact with the drain electrode in each pixel region over the second passivation layer.
According to claim 1, The step of forming the first protective layer,
Forming a photoacrylic layer on the first metal layer;
A method of manufacturing an array substrate for a fringe field switching mode liquid crystal display device, comprising patterning the photoacrylic layer to form a photoacrylic pattern only on the portion where the data wiring and the source and drain electrodes are to be formed.
According to claim 1,
The method of manufacturing an array substrate for a fringe field switching mode liquid crystal display device, wherein the pure amorphous silicon layer is over-etched so that the side end of the active layer is formed undercut with respect to the first protective layer.
delete According to claim 1,
Before the step of forming the pixel electrode having the bar-shaped opening, a third heat treatment is performed to reflow the second protective layer, and thus the side surface of the common electrode exposed in response to the first hole is A method of manufacturing an array substrate for a fringe field switching mode liquid crystal display comprising the step of covering a second protective layer.
According to claim 1,
The forming of the gate wiring includes forming a gate pad electrode connected to the gate wiring and a data pad electrode connected to the data wiring on the pad portion,
The step of forming a common electrode and a second protective layer having a first hole exposing the first protective layer may include forming a second hole exposing the gate insulating layer corresponding to the gate and data pad electrodes and forming the data. Forming a third hole exposing the first protective layer to one end of the wiring, and forming a pad contact hole exposing the gate and data pad electrodes by removing the gate insulating layer corresponding to the second hole The steps include,
The step of removing the first protective layer exposed through the first hole to expose the drain electrode may remove the first protective layer exposed through the third hole to expose one end of the data wiring. And forming a wiring contact hole,
The forming of the pixel electrode may form an auxiliary gate pad electrode contacting the gate pad electrode through the pad contact hole, and at the same time, simultaneously with the data pad electrode and data wiring through the pad contact hole and the wiring contact hole. A method of manufacturing an array substrate for a fringe field switching mode liquid crystal display, comprising forming an auxiliary data pad electrode in contact.
A display area including a plurality of pixel areas each having a switching area and a substrate on which a pad portion is defined outside;
A gate wiring and a gate electrode formed on the substrate and connected to each other in the display area;
A gate pad electrode and an island-type data pad electrode respectively disposed on the pad portion on the substrate;
A gate insulating layer formed on the entire surface of the substrate on the gate wiring, the gate electrode, the gate pad electrode, and the data pad electrode;
An active layer, an ohmic contact layer sequentially stacked corresponding to the data wiring and the gate electrode disposed on the gate insulating layer, and a source electrode and a drain electrode spaced apart from each other;
A first protective layer covering a top surface and side surfaces of the data wiring and the source and drain electrodes, and the active layer exposed between the source and drain electrodes, and having a drain contact hole exposing the surface of the drain electrode;
A common electrode disposed on the first protective layer and the gate insulating layer and having a first opening formed in a region corresponding to the drain contact hole;
A second protective layer disposed on the common electrode and covering a side surface of the common electrode in the first opening;
A pad contact hole formed on the gate insulating layer and the second protective layer to expose the gate and data pad electrodes, respectively;
A wiring contact hole formed on the gate insulating layer and the first and second protective layers to expose one end of the data wiring;
A pixel electrode formed in each pixel region on the second protective layer and contacting the drain electrode through the drain contact hole and having a plurality of bar-shaped second openings;
An auxiliary data disposed on the second passivation layer to contact the gate pad electrode through the pad contact hole, and auxiliary data simultaneously contacting the data pad electrode and data wiring through the pad contact hole and the wiring contact hole. It includes a pad electrode,
The first protective layer is formed in the display area only for the switching area and data wiring. The array substrate for a fringe field switching mode liquid crystal display device.
The method of claim 7,
The first protective layer is an array substrate for a fringe field switching mode liquid crystal display, characterized in that it is made of photoacrylic.
delete The method of claim 7,
The common electrode,
The pad contact hole and the wiring contact hole provided in the second protective layer are formed to extend to the pad portion, and a third opening is provided, and the third opening is the pad contact provided in the second protective layer. An array substrate for a fringe field switching mode liquid crystal display device characterized in that a side surface of the common electrode exposed through the third opening is covered by the second protective layer, which is larger than a hole and a wiring contact hole.
The array substrate for a fringe field switching mode liquid crystal display device of claim 7, wherein the first protective layer and the second protective layer are each heat treated to have a round shape.
The array substrate for a fringe field switching mode liquid crystal display device of claim 7, wherein the common electrode extends over the first protective layer from the gate insulating layer.
Substrate including multiple pixel areas
A gate electrode disposed on the substrate, a gate electrode, a gate insulating layer formed on the front surface of the substrate on which the gate electrode is formed, an active layer disposed on the gate insulating layer, an ohmic contact layer disposed on the active layer, and disposed on the ohmic contact layer A thin film transistor including a source electrode and a drain electrode;
A first protective layer formed on the thin film transistor and covering side surfaces of the active layer, the ohmic contact layer, the source electrode and the drain electrode;
A common electrode formed over the entire pixel region and extending over a first protective layer above the thin film transistor on the gate insulating film;
A second protective layer formed on the common electrode; And
It is formed of a plurality of bar-shaped pixel electrodes formed on the second protective layer to form the common electrode and the electric field,
A drain contact hole is formed in the gate insulating layer and the second protective layer so that the pixel electrode is electrically connected to the drain electrode through the drain contact hole,
An array substrate for a fringe field switching mode liquid crystal display device, wherein the common electrode is formed with a hole outside the drain contact hole.

Images