KR20130033676A - Fringe field switching mode liquid crystal display device - Google Patents

Abstract

PURPOSE: A fringe field switching mode liquid crystal display is provided to minimize a parasitic capacitance between a data line and a common electrode using a protective layer. CONSTITUTION: A second protection layer is formed on a data line(130). The second protection layer is made of low dielectric constant photoacryl. A pixel electrode(170) has a pixel top structure which is formed on a common electrode. The pixel electrode is used as a shielding layer.

Description

Fringe field switching mode liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, wherein a protective layer of photoacryl is formed to minimize parasitic capacitance between a data line and a common electrode overlapping the same, and the drain contact hole may be omitted to improve aperture ratio. A fringe field switching mode liquid crystal display device.

In general, a liquid crystal display device is driven by using optical anisotropy and polarization properties of a liquid crystal. Since the liquid crystal has a long structure, it has a directionality in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal by optical anisotropy, so that image information can be expressed.

At present, an active matrix liquid crystal display (AM-LCD: hereinafter referred to as liquid crystal display) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has excellent resolution and video realization capability, It is attracting attention.

The liquid crystal display device includes a color filter substrate on which a common electrode is formed, an array substrate on which pixel electrodes are formed, and a liquid crystal interposed between the two substrates. In such a liquid crystal display device, The liquid crystal is driven to have excellent properties such as transmittance and aperture ratio.

However, the liquid crystal drive due to the electric field applied up and down has a disadvantage that the viewing angle characteristics are not excellent.

Accordingly, a transverse field type liquid crystal display device having excellent viewing angle characteristics has been proposed to overcome the above disadvantages.

Hereinafter, a general transverse electric field type liquid crystal display device will be described in detail with reference to FIG.

1 is a cross-sectional view of a general transverse electric field type liquid crystal display device.

As shown in the figure, the upper substrate 9, which is a color filter substrate, and the lower substrate 10, which is an array substrate, are spaced apart from each other and face each other. A liquid crystal layer 11 is interposed between the upper and lower substrates 9, .

The common electrode 17 and the pixel electrode 30 are formed on the lower substrate 10 on the same plane. In this case, the liquid crystal layer 11 is formed by the common electrode 17 and the pixel electrode 30. It is operated by the horizontal electric field (L).

2A and 2B are cross-sectional views respectively showing the on and off states of a general transverse electric field type liquid crystal display device.

2A showing the alignment state of the liquid crystal in the ON state to which the voltage is applied, the phase of the liquid crystal 11a at the position corresponding to the common electrode 17 and the pixel electrode 30 is The liquid crystal 11b located between the common electrode 17 and the pixel electrode 30 is formed by a horizontal electric field L formed by applying a voltage between the common electrode 17 and the pixel electrode 30, And arranged in the same direction as the horizontal electric field (L). That is, since the liquid crystal is moved by the horizontal electric field in the transverse electric field type liquid crystal display device, the viewing angle becomes wide.

Therefore, when viewed from the front, the transverse electric field type liquid crystal display device can be seen in the up / down / left / right directions without inversion phenomenon even in about 80 degrees to 85 degrees direction.

Next, referring to FIG. 2B, a horizontal electric field is not formed between the common electrode and the pixel electrode since the liquid crystal display device is in an off state in which no voltage is applied, so that the alignment state of the liquid crystal layer 11 is not changed.

However, such a transverse field type liquid crystal display device has an advantage of improving the viewing angle, but has a disadvantage of low aperture ratio and low transmittance.

Therefore, in order to characterize the shortcomings of the transverse electric field type liquid crystal display, a fringe field switching mode LCD is characterized in that the liquid crystal is operated by a fringe field.

3 is a plan view of one pixel area in an array substrate of a conventional fringe field switching mode liquid crystal display.

As shown, a plurality of gate lines 43 extend in one direction, and intersect with the plurality of gate lines 43 to define a plurality of pixel regions P, and a plurality of data lines 51 It is composed.

In addition, each of the plurality of pixel regions P is connected to the data line 51 and the gate line 43 defining the gate electrode 45, the gate insulating layer (not shown), the semiconductor layer (not shown), and the source. And a thin film transistor Tr, which is a switching element including drain electrodes 55 and 58, is formed.

In addition, each pixel region P is electrically connected to the drain electrode 58 of the thin film transistor Tr through the drain contact hole 59 and has a plurality of bar-shaped openings op. The pixel electrode 60 of the form is formed.

In addition, a common electrode 75 is formed on the entire display area in which the plurality of pixel areas P is formed, overlapping the plate-shaped pixel electrode 60 corresponding to each pixel area P. FIG. In this case, the common electrode 75 is formed on the entire surface of the display area, but a portion corresponding to one pixel area is indicated by a dotted line.

The array substrate 41 for a fringe field switching mode liquid crystal display device having such a configuration includes a pixel electrode 60 having the plurality of bar-shaped openings op for each pixel region P, and the common electrode. A voltage is applied to the 75 to form a fringe field.

However, in the fringe field switching mode liquid crystal display device 50 having the above-described structure, the common electrode 75 made of a transparent conductive material is formed in a plate shape on the front of the display area to overlap the data line 51. The parasitic capacitance is formed by the common electrode 51 overlapping the data wiring 51 and an insulating layer (not shown) interposed between these two components, thereby delaying a signal voltage transmitted through the data wiring. It is causing.

Each pixel region P has a size at least 10 μm or one side that exposes the drain electrode 59 of the thin film transistor Tr to electrically connect the pixel electrode 60 and the drain electrode 58. The drain contact hole 58 which has is provided, and the opening ratio is reduced by this.

The present invention has been made to solve the problems of the conventional fringe field switching mode liquid crystal display array substrate, it is possible to minimize the parasitic capacitance between the data line and the common electrode overlapping each other, it is possible to improve the aperture ratio It is an object of the present invention to provide a fringe field switching mode liquid crystal display device.

A fringe field switching mode liquid crystal display device according to the present invention for achieving the above object includes: a gate wiring and a data wiring formed on a first substrate on which a display area is defined to define a plurality of pixel regions; A thin film transistor connected to the gate line and the data line and formed in each pixel area; A first passivation layer formed on an entire surface of the display area and having a hole having a first size exposing the thin film transistor and formed of an organic insulating material; A common electrode formed on an entire surface of the display area and having a first opening that exposes the first protective layer corresponding to the hole on the first protective layer; A second protective layer formed of an inorganic insulating material on the common electrode and having a drain contact hole exposing a drain electrode of the thin film transistor inside the hole; A pixel electrode formed on the second passivation layer to be in contact with the drain electrode through the drain contact hole in the hole and patterned for each pixel region, and having a plurality of bar-shaped second openings in each pixel region; and; A second substrate corresponding to the first substrate and facing the first substrate; A patterned spacer formed on an inner side surface of the second substrate; And a liquid crystal layer interposed between the first and second substrates, wherein the patterned spacer has an end inserted into a hole provided in the first substrate.

In this case, the organic insulating material is photoacrylic, and the inorganic insulating material is silicon oxide (SiO ₂ ) or silicon nitride (SiNx).

The first protective layer has a thickness of 1.5 μm to 2.5 μm, and the first size has one side or a diameter of 10 μm to 25 μm.

In addition, the patterned spacer is divided into a patterned spacer for forming gaps having a first height and a patterned spacer for preventing depression having a second height smaller than the first height, and the gap forming spacer is provided in one pixel area. In another pixel area, the pressing preventing patterned spacer is provided.

At this time, one end of the gap-shaped patterned spacer is in contact with a component provided on the uppermost layer of the first substrate in the hole, and the anti-pressing patterned spacer is the uppermost layer of the first substrate in the hole. Characterized by spaced apart from the components provided in.

In addition, a gate insulating film is formed on the first substrate to cover the gate electrode and the gate wiring, and the data wiring is formed on the gate insulating film, and an inorganic material is formed on the entire surface of the display area between the data wiring and the first protective layer. A third protective layer made of an insulating material is formed, and the third protective layer is provided with the drain contact hole exposing the drain electrode of the thin film transistor like the second protective layer.

The drain electrode has a bent portion, and the bent portion includes a first portion and a second portion with reference to the bent portion, and the first portion is positioned to face the source electrode of the thin film transistor, and the second portion is the gate wiring. It is characterized in that it is configured to extend in the longitudinal direction of.

In addition, a color filter layer provided in the display area between the inner surface of the second substrate and the patterned spacer; An overcoat layer formed covering the color filter layer is provided, and the patterned spacer is formed on the overcoat layer.

In the fringe field switching mode liquid crystal display device according to the present invention, a parasitic capacitance between the data line and the common electrode is minimized by forming a protective layer interposed between the data line and the common electrode using photoacryl having a low dielectric constant. There is an effect of suppressing signal delay of data wiring.

In addition, the fringe field switching mode liquid crystal display device according to the present invention has a pixel top structure so that parasitics may occur due to a difference in distance from the data line for each pixel region caused by a formation error of the pixel electrode formed for each pixel region. There is an effect of suppressing the deterioration of image display quality such as the generation of vertical crosstalk due to the change in capacitance.

In addition, when the photoacryl is formed to have a thickness of about 2 μm, the width of the drain contact hole becomes 10 μm or more due to the exposure characteristics of the photoacryl, and in this case, the aperture ratio of the pixel region is reduced. After forming a hole for exposing the thin film transistor corresponding to the thin film transistor, a portion of the drain electrode exposed by the hole formation and an end of the pixel electrode contact each other, and a patterned spacer is formed on the color filter substrate to correspond to the hole. As a result, the aperture ratio is improved, and at the same time, the patterned spacers do not flow when the pressing is caused by external pressure, thereby suppressing light leakage around the spacers caused by the flow of the patterned spacers.

1 is a cross-sectional view schematically showing a part of a general transverse electric field type liquid crystal display device.
FIGS. 2A and 2B are cross-sectional views respectively showing the on and off states of a general transverse electric field liquid crystal display device;
3 is a plan view of one pixel area of a conventional fringe field switching mode liquid crystal display device;
4 is a plan view of one pixel area of a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention.
FIG. 5 is a cross-sectional view of a portion taken along the cutting line VV of FIG. 4. FIG.
6A to 6I are cross-sectional views of manufacturing steps for a portion cut along the cutting line VV of FIG. 4.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

4 is a plan view of one pixel area of a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention. For convenience of description, a portion in which the thin film transistor Tr, which is a switching element, is formed in each pixel region P is defined as a switching region TrA.

As illustrated, the fringe field switching mode liquid crystal display device 100 according to an exemplary embodiment of the present invention may include an array substrate 101 including a thin film transistor Tr, a pixel electrode 150, and a common electrode 150. A color filter substrate (not shown) including the color filter layer 186 and the patterned spacer 190 and a liquid crystal layer (not shown) interposed between the two substrates 101 (not shown) are configured.

Meanwhile, the array substrate 101 extends in a first direction and has a low resistance metal material such as aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo), and molybdenum alloy (MoTi). ) Is formed of a gate wiring 105 made of any one or two or more materials, and is made of the low-resistance metal material and extends in a second direction so as to intersect with each of the plurality of gate wirings 105. A plurality of data wires 130 defining (P) are formed.

Each of the pixel regions P is connected to the gate line 105 and the data line 130, and has a gate electrode 108, a gate insulating layer (not shown), and an active layer of pure amorphous silicon (not shown). ) And a thin film transistor Tr including a source layer and a drain electrode 133 and 136 spaced apart from each other, and a semiconductor layer (not shown) including an ohmic contact layer (not shown) of impurity amorphous silicon.

At this time, in the drawing, the thin film transistor Tr has an 'U' shape in which a region forming a channel is rotated about 45 degrees in a counterclockwise direction with respect to the extension direction of the gate wiring 105. It can be transformed into a form.

In the array substrate 101 for the fringe field switching mode liquid crystal display device 100 according to the exemplary embodiment of the present invention, as described above, the channel rotates about 45 degrees counterclockwise with respect to the longitudinal direction of the gate wiring 105. In the case of the “U” shape, the drain electrode 136 includes a first portion 136a and a first portion 136a extending in a direction rotated by 45 degrees counterclockwise with respect to the gate wiring 105. ) And a second portion 136b that is bent in the longitudinal direction of the gate wiring 105.

On the other hand, the array substrate 101 is provided with a first protective layer (not shown) made of an inorganic insulating material covering the thin film transistor (Tr) on the front surface, the other organic layer over the first protective layer (not shown) A second protective layer (not shown) made of photo acryl having a relatively low dielectric constant value is provided on the front surface of the material.

In this case, the array substrate 101 for the fringe field switching mode liquid crystal display device 100 according to the embodiment of the present invention is the most characteristic, and the thin film transistor (not shown) is formed of the second protective layer (not shown) made of the photoacryl. A hole hl is removed corresponding to Tr to expose the first protective layer (not shown). In this case, the hole hl may include a portion where the first and second portions 136a and 136b of the drain electrode 136 are formed.

In the display area including the plurality of pixel areas P, the common electrode 150 formed of a transparent conductive material on the entire surface of the display area on the second protective layer (not shown) provided with the holes hl. Is being formed. In this case, the common electrode 150 is provided with a first opening op1 having a width larger than that of the hole hl and completely overlapping the hole hl corresponding to the hole hl. It is characteristic.

In addition, a third passivation layer (alehtl) made of an inorganic insulating material is provided on an entire surface of the common electrode 150 having the first opening op1. At this time, in the hole hl, the third protective layer (not shown) and the first protective layer (not shown) below are removed to expose the second portion 136b of the drain electrode 136. The drain contact hole 163 is provided.

In addition, an upper portion of the third passivation layer (not shown) is made of a transparent conductive material and contacts the second portion 136b of the drain electrode 136 of the thin film transistor Tr through the drain contact hole 163. Each pixel region P is formed with a pixel electrode 170 having a plate shape. In this case, each of the pixel electrodes 170 has a bar shape and is provided with a plurality of second openings op2 spaced apart from each other.

On the other hand, in the case of the array substrate 101 for the fringe field switching mode liquid crystal display device 100 according to the embodiment of the present invention having the planar structure described above, each pixel electrode 170 for each pixel region (P) in the drawing Although the bar-shaped second openings op2 are shown to be spaced apart from each other at equal intervals, the third openings are arranged in the pixel areas P for efficient fringe field formation. The two openings op2 may be variously modified and formed in an appropriate number within a range of about 2 to about 15.

A black matrix (not shown) is formed on the color filter substrate (not shown) corresponding to the array substrate 101 having the above-described configuration, corresponding to the boundary of each pixel region P and the thin film transistor Tr. A color filter layer (not shown) covering the black matrix (not shown) and including red, green, and blue color filter patterns (not shown) that are sequentially repeated for each pixel area P is formed.

In addition, an overcoat layer (not shown) covering the color filter layer (not shown) and having a flat surface is formed on the front surface, and the patterned spacer 190 having a pillar shape in contact with the overcoat layer (not shown) is formed. It is being formed.

In this case, as another characteristic configuration of the fringe field switching mode liquid crystal display device 100 according to the exemplary embodiment of the present invention, the patterned spacer 190 may include the thin film transistor Tr provided in the array substrate 101. The end is inserted into the hole (hl) formed corresponding to the feature.

Due to this configuration, the fringe field switching mode liquid crystal display 100 according to the exemplary embodiment of the present invention has a hole (hl) provided in a second protective layer (not shown) made of photoacryl corresponding to the thin film transistor Tr. ) And the pattern spacer 190 are superposed on the black matrix as compared to the array substrate 101 for the conventional fringe field switching mode liquid crystal display 100 which is formed by separating these two components, respectively. Area) can be reduced, thereby improving the aperture ratio.

The patterned spacer 190 has a configuration in which the patterned spacer 190 is inserted into the hole hl, thereby limiting an area where the end of the patterned spacer 190 moves when pressure is applied from the outside. There is an effect of preventing light leakage due to breakage of the alignment film (not shown) generated by the flow of the end of.

In addition, since the pixel electrode 170 has a pixel top structure disposed on the common electrode 150, the common electrode 150 having the first opening op1 and formed on the entire surface of the display area includes the shield layer. It serves to prevent the parasitic capacitance generated between the data line and the pixel electrode 170 at the source.

Therefore, as in the related art, vertical crosstalk is generated due to parasitic capacitance change due to the difference in distance between the data line and the pixel electrode due to the process error of the pixel electrode formed for each pixel region generated in the array substrate having the common electrode on the top. Since it is possible to prevent the source at the source has the effect of improving the display quality.

Hereinafter, a cross-sectional structure of a fringe field switching mode liquid crystal display device according to an exemplary embodiment of the present invention having such a planar configuration will be described.

FIG. 5 is a cross-sectional view of a portion cut along the cutting line VV of FIG. 4. In this case, for convenience of description, the region where the thin film transistor Tr is formed is defined as a switching region TrA.

As shown, the fringe field switching mode liquid crystal display device 100 according to the present invention is interposed between the lower array substrate 101, the upper color filter substrate 181, and the two substrates 101 and 181. The liquid crystal layer 195 is included.

First, the array substrate 101 is a metal material having low resistance properties, such as aluminum (Al) and aluminum, on a first substrate 101 made of a transparent and insulating material serving as a base, for example, glass or plastic. One or more materials selected from among alloys (AlNd), copper (Cu), copper alloys, molybdenum (Mo), and molybdenum alloys (MoTi) are formed, and gate wirings (not shown) extending in the first direction are formed. The gate electrode 108 is connected to the gate line (not shown) in the switching region TrA.

Next, a gate insulating layer 115 is formed over the gate line and the gate electrode 108 as an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), on the entire surface of the substrate 101. have.

In addition, a semiconductor layer including an active layer 120a of pure amorphous silicon and an ohmic contact layer 120b of impurity amorphous silicon in the switching region TrA on the gate insulating layer 115 in correspondence with the gate electrode 108. 120 is formed, and the source and drain electrodes 133 and 136 are spaced apart from each other above the semiconductor layer 120. In this case, the active layer 120a is exposed between the source and drain electrodes 133 and 136 spaced apart from each other.

The gate electrode 108, the gate insulating layer 115, the semiconductor layer 120, and the source and drain electrodes 133 and 136 sequentially stacked in the switching region TrA may form a thin film transistor Tr as a switching element. Achieve.

In addition, a data line 130 defining a pixel region P intersecting the gate line (not shown) may extend in a second direction on the gate insulating layer 115, and a source electrode of the thin film transistor Tr may be formed. 133 is formed and connected.

Meanwhile, a first layer of an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), is formed on the entire surface of the first substrate 101 over the data line 130 and the source and drain electrodes 133 and 136. The protective layer 140 is formed.

The first protective layer 140 made of such an inorganic insulating material may be contaminated when the channel forms the second protective layer 144 made of photo acryl, and thus may be omitted.

 Next, the first protective layer 140 is made of photo acryl having a low resistivity, and has a thickness of about 1.2 μm to 2.5 μm to overcome a step caused by a lower component, thereby having a flat surface. The second protective layer 144 is formed.

In this case, holes hl are formed in the second passivation layer 144 to expose the first passivation layer corresponding to the thin film transistor Tr.

In the case of forming a contact hole exposing a lower component by performing a mask process on the second protective layer 144 having a thickness of about 2 μm with photo acryl, the second protective layer ( 144) It is difficult to realize the current technology so that the diameter or one side of the contact hole becomes 10 µm or less due to the thickness of itself and light diffraction during the exposure process.

Therefore, in the fringe field switching mode liquid crystal display device 100 according to the embodiment of the present invention, the minimum length of one side or diameter is maximized by utilizing the characteristics of the second protective layer 144 made of photo acryl. It is characterized by having a hole (hl) larger than 10 μm and less than or equal to 25 μm. At this time, the one side or the diameter is formed to be about 10 to 25㎛ in order to insert the patterned spacer in the characteristics of the present invention.

At this time, the hole hl exposes only the drain electrode 58 of FIG. 3 as shown in the array substrate 50 of FIG. 3 of a fringe-filled switching mode liquid crystal display. However, since the thin film transistor Tr itself is exposed, the contact hole (59 of FIG. 3) having one side or diameter of about 10 μm is moved left and right by the exposure error in each pixel region P as in the related art. Therefore, it is not necessary to form large so that one side of the drain electrode (58 of FIG. 3) becomes 14 micrometers or more.

That is, since the hole hl is provided corresponding to the entire thin film transistor Tr, the drain electrode 136 only needs to be included in the position where the hole hl is formed. As described above, the contact hole may be formed to be smaller than the size of the contact hole.

Further, in the embodiment of the present invention, since the drain electrode 136 does not need to be large, the area occupied in each pixel region P is relatively small, so that the width thereof can be reduced, so that the width of the drain electrode 136 can be reduced. The opening ratio can be further improved by having a bent shape for placement efficiency.

That is, in the exemplary embodiment of the present invention, the drain electrode 136 has a first angle 136a extending toward the center of the pixel region with an angle of 45 degrees with respect to the longitudinal direction of the gate wiring 105. And a second drain 136b that is bent at the end of the first portion 136a and extends in the longitudinal direction of the gate wiring 105 in FIG. 4, thereby extending toward the center of the pixel region without the bent portion. By reducing the portion covered by the black matrix (not shown) compared to the electrode (58 of FIG. 3) it is possible to improve the aperture ratio.

For this reason, the size of the drain electrode 136 covering the pixel region P can be formed to have a smaller size than the conventional one, so that the aperture ratio of the pixel region P can be improved.

Meanwhile, a transparent conductive material, for example, indium tin oxide (ITO) or indium zinc oxide (IZO), may be formed on the entire surface of the display area on the second passivation layer 144 including the holes hl. The common electrode 150 is formed. In this case, the common electrode 150 is provided with a first opening op1 having a width larger than that of the hole hl and completely overlapping the hole hl corresponding to the hole hl. It is characteristic.

Next, an inorganic insulating material, eg, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), is formed on the entire surface of the first substrate above the common electrode having the first opening op1 corresponding to the hole hl. Three protective layers 160 are formed. In this case, the third protective layer 160 may have the hole hl formed therein, and the first protective layer may be disposed below the corresponding second portion 136b of the drain electrode 136. In addition to the layer 140, a drain contact hole 163 exposing the second portion 136b of the drain electrode 136 is provided.

Since the first and third protective layers 140 and 160 are formed with an inorganic insulating material and have a thickness of about 1000 kPa to 4000 kPa, the minimum and the minimum values are required when the drain electrode 136 is exposed by patterning the first and third protective layers 140 and 160. Since the size of the hole is about 5 to 6 μm on one side or diameter thereof, the size of the drain electrode 136 may be smaller than that of the related art.

Next, an upper portion of the third passivation layer 160 contacts the second portion 136b of the drain electrode 136 exposed through the drain contact hole 163 in the hole hl and each pixel area P. Referring to FIG. ), A plate-shaped pixel electrode 170 made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is formed. At this time, each of the pixel electrodes 170 has a bar shape, and a plurality of second openings op2 spaced apart from each other are provided.

In the color filter substrate 181 formed to be spaced apart from each other via the liquid crystal layer 195 to correspond to the array substrate 101 having such a cross-sectional configuration, the transparent second substrate 181 having insulating properties as a base is formed. On the inner side, a black matrix 183 is formed corresponding to the boundary of each pixel region P and the thin film transistor Tr.

In addition, a color filter layer 186 is formed on the black matrix 183 and includes red, green, and blue color filter patterns R, G, and the like, which are sequentially repeated for each pixel region P. The overcoat layer 188 covering the color filter layer 186 and having a flat surface is formed on the entire surface.

In addition, the patterned spacers 190 (not shown) in contact with the overcoat layer 188 and having a pillar shape are formed at regular intervals.

The patterned spacer 190 includes a gap forming spacer 190 having a first height in the form of a column and a pressing preventing spacer (not shown) having a second height smaller than the first height in the form of a column. Each of the patterned spacers 190 (not shown) has a shape in which an end thereof is inserted into a hole hl provided in the array substrate 101.

In this case, the gap-shaped patterned spacer 190 having the first height is in contact with a component forming the uppermost layer of the array substrate 101 in the hole hl, and the second height is increased. The anti-press patterned spacer (not shown) has a feature that is formed spaced apart from the components forming the uppermost layer of the array substrate 101 in the hole (hl).

Although not shown in the drawings, the liquid crystal layer 195 may be disposed in a non-display area (not shown) outside the display area so that the array substrate 101 and the color filter substrate 181 may be bonded to each other to form a panel. The fringe field switching mode liquid crystal display 100 according to the exemplary embodiment of the present invention is completed by providing a seal pattern (not shown) serving as an adhesive in the form of enclosing ().

In the fringe field switching mode liquid crystal display 100 according to the exemplary embodiment of the present invention, the second protective layer 144 made of photoacryl having low dielectric constant on the data line 130 is 1.5 μm. Since the parasitic capacitance generated by the common electrode 150 overlapping with the data line 130 is formed by having a thickness of about 2.5 μm, the signal delay of the data line 130 is suppressed. .

Also, in a high resolution model having a relatively small size of the pixel region P, a contact hole having a diameter or one side size of 10 μm or more is formed such that a component exposed through the contact hole has a larger area than the contact hole. In order to reduce the aperture ratio, the present invention requires a hole to correspond to the thin film transistor in the second protective layer made of photoacrylic, and has a drain having one side or diameter of about 5 μm to 6 μm in the hole. The contact hole may be provided to be in contact with the pixel electrode 150, thereby reducing the size of the drain electrode 136 and improving the aperture ratio.

Referring to FIG. 3, which is a plan view of a conventional fringe field switching mode liquid crystal display, and FIG. 4, which is a plan view of a fringe field switching mode liquid crystal display according to an embodiment of the present invention, an area that is covered by a black matrix (BM region). It can be seen that the fringe field switching mode liquid crystal display according to the present invention has a smaller area than that of the conventional fringe field switching mode liquid crystal display.

In the case of the substantially high resolution model (300PPI or more), the fringe field switching mode liquid crystal display according to the embodiment of the present invention having the configuration as described above is 3.2 to 3 by model in terms of aperture ratio compared to the conventional fringe field switching mode liquid crystal display. It can be seen that about 8%.

In addition, the gap forming and pressing preventing patterned spacers 190 (not shown) provided in the color filter substrate 181 may be inserted into the ends corresponding to the holes hl provided in the array substrate 101. As a result, even if pressure is applied from the outside, the end of the patterned spacer 190 (not shown) is limited to a flow radius inside the hole, thereby reducing the light leakage generated around the patterned spacer 190 (not shown). have.

In addition, the pixel electrode 170 forms a pixel top structure provided on the common electrode 150 to shield the common electrode 150 having the first opening op1 and formed on the entire display area. By acting as a layer, the parasitic capacitance generated between the data line and the pixel electrode 170 is prevented at the source, thereby suppressing the generation of vertical crosstalk due to the parasitic capacitance change due to the process error, thereby improving display quality.

Hereinafter, a method of manufacturing a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention will be briefly described. At this time, since a characteristic part of the present invention is in the array substrate, the manufacturing method of the array substrate will be mainly described.

6A to 6I are cross-sectional views of manufacturing steps of a portion cut along the cutting line VV of FIG. 4. In this case, for convenience of description, the region where the thin film transistor Tr is formed is defined as a switching region TrA.

First, as shown in FIG. 6A, a metal material having low resistance on the first substrate, for example, aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo), and molybdenum After depositing one or two or more materials selected from the alloy (MoTi) to form a first metal layer, a unit process such as applying a photoresist, exposing with an exposure mask, developing an exposed photoresist, etching and stripping, etc. Forming a gate line (not shown) extending in the first direction by patterning the mask process including a mask process, and simultaneously forming a gate electrode 108 connected to the gate line (not shown) in the switching region TrA. do.

Subsequently, an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), is deposited on the entire surface of the first substrate 101 over the gate wiring (not shown) and the gate electrode 108. ).

Next, pure amorphous silicon and impurity amorphous silicon are successively deposited on the gate insulating layer 115, and the mask process is patterned to form the pure amorphous silicon corresponding to the gate electrode 108 in the switching region TrA. An impurity amorphous silicon pattern 121 is formed on the active layer 120a and the upper portion thereof.

Next, as shown in FIG. 6C, a metal material having low resistance over the impurity amorphous silicon pattern (121 of FIG. 6B), for example, aluminum (Al), aluminum alloy (AlNd), copper (Cu), and copper alloy And depositing one or more materials selected from molybdenum (Mo) and molybdenum alloy (MoTi) to form a second metal layer (not shown), and then patterning the same to form a second metal layer on the gate insulating layer 115. A data line 130 defining the pixel area P is formed to cross the gate line (not shown), and at the same time, the switching area TrA is spaced apart from each other on the impurity amorphous silicon pattern 121 (see FIG. 6B). The source electrode 133 and the drain electrode 136 are formed.

At this time, the source electrode 133 is connected to the data line 130 and at the same time form a "U" shape in a direction rotated 45 degrees counterclockwise with respect to the longitudinal direction of the gate line (not shown). The drain electrode 136 has a shape in which the first portion 136a is inserted into the opening of the “U” shaped source electrode 133 by the first portion 136a, and the first portion 136a. It is characterized in that it is formed to be made of a second portion (136b) is bent in the extending in the longitudinal direction of the gate wiring (not shown).

Thereafter, the impurity amorphous silicon pattern (121 of FIG. 6B) exposed between the source and drain electrodes 133 and 136 spaced apart from each other is etched and removed to remove impurities spaced apart from each other below the source and drain electrodes 133 and 136. An ohmic contact layer 120b made of amorphous silicon is formed. In this case, the active layer 120a and the ohmic contact layer 120b form a semiconductor layer 120, and the gate electrode 108, the gate insulating layer 115, and the semiconductor layer (sequentially stacked in the switching region TrA) are formed. 120 and the source and drain electrodes 133 and 136 form a thin film transistor Tr which is a switching element.

Next, as shown in FIG. 6D, an inorganic insulating material such as silicon oxide (SiO ₂ ) or nitride is formed on the entire surface of the first substrate 101 over the data line 130 and the source and drain electrodes 133 and 136. The first protective layer 140 is formed by depositing silicon (SiNx). The first protective layer 140 made of such an inorganic insulating material is an organic material that is exposed between the source and drain electrodes when the second protective layer 144 made of photo acryl is formed in a later process. Since it may be contaminated by direct contact with the photoacrylic, it may be omitted to form to prevent it.

 Next, as shown in FIG. 6E, a photoacryl having a low resistivity dielectric constant value is formed on the first passivation layer 140 and has a thickness of about 1.2 μm to 2.5 μm. A second protective layer 144 having a flat surface is formed by overcoming a step, and a mask process is performed to form a hole hl exposing the first protective layer in correspondence to the thin film transistor Tr. . In this case, the mask process for forming the hole (hl) is characterized in that the photoacryl itself has a photosensitive characteristic, so that a process of applying a separate photoresist and a strip process are omitted.

That is, the second protective layer 144 having the hole hl is formed by applying photoacryl on the first protective layer 140, then exposing and curing the photoacryl, and proceeding with development. Will be done.

Next, as shown in FIG. 6F, a transparent conductive material, for example, indium tin oxide (ITO), is formed on the entire surface of the second protective layer 144 having holes hl corresponding to the thin film transistor Tr. Or by depositing and patterning indium-zinc oxide (IZO) and patterning it, the first opening op1 completely overlaps the hole hl and has a larger area than the hole hl to expose the hole hl. The common electrode 150 is formed over the entire display area.

Next, as illustrated in FIG. 6G, an inorganic insulating material, for example, an oxide, is oxidized on the entire surface of the first substrate 101 over the common electrode 150 having the first opening op1 corresponding to the hole hl. Silicon (SiO ₂ ) or silicon nitride (SiNx) is deposited on the entire surface to form a third protective layer 160.

Thereafter, the third protective layer 160 and the first protective layer 140 disposed below the hole hl are patterned by performing a mask process to pattern the drain electrode inside the hole hl. A drain contact hole 163 exposing the second portion 136b of 136 is formed. At this time, the drain contact hole 163 is characterized in that one side or diameter is about 5㎛ to 6㎛.

Next, as illustrated in FIG. 6H, a transparent conductive material, for example, indium tin oxide (ITO) or indium zinc oxide (IZO), is deposited on the third protective layer 160. The mask process is performed to pattern the pixels to form a plate shape for each pixel area, and the second portion 136b of the drain electrode 136 exposed through the drain contact hole 163 in the hole hl and For fringe field switching mode liquid crystal display device according to an embodiment of the present invention by forming a pixel electrode having a plurality of second openings (op2) in contact with each other and a bar shape in the pixel region (P) Complete the array substrate.

Thereafter, as shown in FIG. 6I, the color filter layer 186 including the array substrate 101 manufactured as described above, the black matrix 183 manufactured by the general method, and the red, green, and blue color filter patterns. ) And the color filter substrate 181 including the overcoat layer 188 and the patterned spacer 190 (not shown), and then the substrate of either the array substrate 101 or the color filter substrate 181. A liquid crystal layer 195 is interposed between the two substrates 101 and 181 in a state in which a seal pattern (not shown) is formed along the edge of the substrate and the patterned spacer 190 (not shown) is inserted into the hole. The fringe field switching mode liquid crystal display 100 according to the exemplary embodiment of the present invention is completed by hardening the seal pattern (not shown) to maintain the panel state.

The present invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit of the present invention.

100 liquid crystal display device 101 array substrate
108 gate electrode 115 gate insulating film
120: semiconductor layer 120a: active layer
120b: ohmic contact layer 121: dummy pattern
130: data wiring 133: source electrode
136: drain electrode 136a: first portion (of drain electrode)
136b: second portion (of drain electrode) 140: first protective layer
144: second protective layer 150: common electrode
160: third protective layer 163: drain contact hole
170: pixel electrode 181: color filter substrate
183: Black matrix 186: color filter layer
188: overcoat layer 190: patterned spacer (for gap formation)
195: liquid crystal layer hl: hole
op1, op2: first and second openings P: pixel area
Tr: Thin Film Transistor TrA: Switching Area

Claims (9)

Gate lines and data lines formed on the first substrate having the display area defined therebetween to define a plurality of pixel areas;
A thin film transistor connected to the gate line and the data line and formed in each pixel area;
A first passivation layer formed on an entire surface of the display area and having a hole having a first size exposing the thin film transistor and formed of an organic insulating material;
A common electrode formed on an entire surface of the display area and having a first opening that exposes the first protective layer corresponding to the hole on the first protective layer;
A second protective layer formed of an inorganic insulating material on the common electrode and having a drain contact hole exposing a drain electrode of the thin film transistor inside the hole;
A pixel electrode formed on the second passivation layer to be in contact with the drain electrode through the drain contact hole in the hole and patterned for each pixel region, and having a plurality of bar-shaped second openings in each pixel region; and;
A second substrate corresponding to the first substrate and facing the first substrate;
A patterned spacer formed on an inner side surface of the second substrate;
Liquid crystal layer interposed between the first and second substrate
And wherein the patterned spacer has an end inserted into a hole provided in the first substrate.
The method of claim 1,
The organic insulating material is photoacrylic,
And the inorganic insulating material is silicon oxide (SiO ₂ ) or silicon nitride (SiNx).
The method of claim 2,
The first protective layer has a thickness of 1.5㎛ to 2.5㎛ fringe field switching mode liquid crystal display device.
The method of claim 3, wherein
The first size is a fringe field switching mode liquid crystal display, characterized in that one side or 10㎛ 25㎛ diameter.
The method of claim 1,
The patterned spacer is divided into a gap forming patterned spacer having a first height and a depression preventing patterned spacer having a second height smaller than the first height, and the gap forming spacer is provided in one pixel area. A fringe field switching mode liquid crystal display device, characterized in that the depression prevention patterned spacer is provided in one pixel area.
The method of claim 5, wherein
The gap-formed patterned spacer has one end thereof in contact with a component provided in the uppermost layer of the first substrate in the hole, and the pressing preventing patterned spacer is provided in the uppermost layer of the first substrate in the hole. Fringe field switching mode liquid crystal display, characterized in that formed apart from the components.
The method of claim 1,
A gate insulating film is formed on the first substrate to cover the gate electrode and the gate wiring, and the data wiring is formed on the gate insulating film. An inorganic insulating material is formed on the entire surface of the display area between the data wiring and the first passivation layer. A fringe field switching mode liquid crystal display device comprising: a third passivation layer comprising a drain contact hole exposing a drain electrode of the thin film transistor like the second passivation layer.
The method of claim 1,
The drain electrode has a bent portion, and the bent portion includes a first portion and a second portion, the first portion being positioned to face the source electrode of the thin film transistor, and the second portion is the length of the gate wiring. A fringe field switching mode liquid crystal display, characterized in that it is configured to extend in a direction.
The method of claim 1,
Between an inner surface of the second substrate and the patterned spacer
A color filter layer provided in the display area;
And an overcoat layer formed covering the color filter layer, wherein the patterned spacer is formed on the overcoat layer.

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