KR20110054727A - Array substrate for liquid crystal display device and liquid crystal display device including the same - Google Patents

Abstract

PURPOSE: An array substrate for liquid crystal display device and liquid crystal display device including the same are provided to prevent the deterioration of opening ratio by the width of a black matrix and to minimize the increase in manufacturing cost. CONSTITUTION: A gate line and a data line(140) cross with each other on a substrate. The gate line and the data line are connected to a thin film transistor. A pixel electrode(130) is connected to the thin film transistor in the pixel region. A protective layer covers the gate line, the data line, and the thin film transistor. A common electrode(150) is located on a protective layer and laminated with the gate line, the data line, and the pixel electrode. A first light-shield pattern touches while being piled up one with the common electrode.

Description

Array substrate for liquid crystal display device and liquid crystal display device including the same

The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a fringe field switching mode liquid crystal display device and a fringe field switching mode liquid crystal display device including the same.

Generally, the driving principle of a liquid crystal display device utilizes the optical anisotropy and polarization properties of a liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, an active matrix liquid crystal display device (AM-LCD: abbreviated to an active matrix LCD, abbreviated as a liquid crystal display device) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has the best resolution and video performance. It is attracting attention.

The liquid crystal display includes a color filter substrate on which a common electrode is formed, an array substrate on which pixel electrodes are formed, and a liquid crystal interposed between the two substrates. In such a liquid crystal display, the common electrode and the pixel electrode are caused by an electric field applied up and down. It is excellent in the characteristics, such as transmittance | permeability and aperture ratio, by the method of driving a liquid crystal.

However, the liquid crystal drive due to the electric field applied up and down has a disadvantage that the viewing angle characteristics are not excellent.

Accordingly, a transverse field type liquid crystal display device having excellent viewing angle characteristics has been proposed to overcome the above disadvantages.

Hereinafter, a general transverse electric field type liquid crystal display device will be described in detail with reference to FIG. 1.

1 is a cross-sectional view of a general transverse electric field type liquid crystal display device.

As shown, the upper substrate 9, which is a color filter substrate, and the lower substrate 10, which is an array substrate, are spaced apart from each other, and the liquid crystal layer 11 is interposed between the upper and lower substrates 9, 10. It is.

The common electrode 17 and the pixel electrode 30 are formed on the lower substrate 10 on the same plane. In this case, the liquid crystal layer 11 is formed by the common electrode 17 and the pixel electrode 30. It is operated by the horizontal electric field (L).

2A and 2B are cross-sectional views illustrating operations of ON and OFF states of a general transverse electric field type liquid crystal display device, respectively.

First, referring to FIG. 2A, which illustrates an arrangement of liquid crystals in an on state where a voltage is applied, a phase change of a liquid crystal 11a at a position corresponding to the common electrode 17 and the pixel electrode 30 is performed. Although the liquid crystal 11b positioned in the section between the common electrode 17 and the pixel electrode 30 is formed by the horizontal electric field L formed by applying a voltage between the common electrode 17 and the pixel electrode 30, It is arranged in the same direction as the horizontal electric field (L). That is, in the transverse electric field type liquid crystal display device, since the liquid crystal moves by the horizontal electric field, the viewing angle is widened.

Next, referring to FIG. 2B, since no voltage is applied to the liquid crystal display, a horizontal electric field is not formed between the common electrode and the pixel electrode, so that the arrangement state of the liquid crystal layer 11 does not change.

In addition to the advantages of a transverse electric field type liquid crystal display device having a wide viewing angle, a fringe field switching mode LCD which can simultaneously use a horizontal electric field and a vertical electric field has been proposed.

3 is a plan view of one pixel area of an array substrate for a conventional fringe field switching mode liquid crystal display, and FIG. 4 is a cross-sectional view of the liquid crystal display taken along the cutting line IV-IV of FIG. 3.

As shown in FIGS. 3 and 4, the liquid crystal display includes a first substrate 50, a second substrate 80 facing the first substrate 50, and the first and second substrates 50. And 80 between the liquid crystal layer 90.

A plurality of gate wires 52 extend in one direction on the first substrate 50, and intersect the plurality of gate wires 52 to define a pixel region P, and a plurality of data wires 62. This is composed. In other words, the pixel area P is an area surrounded by the gate line 52 and the data line 62.

In addition, each of the plurality of pixel regions P is connected to the data line 62 and the gate line 52 defining the active layer, and an active layer made of a gate electrode 54, a gate insulating layer 56, and pure amorphous silicon (not shown). ) And a thin film transistor (Tr) including a source electrode 64 and a drain electrode 66 are formed, including a semiconductor layer (not shown) including an ohmic contact layer (not shown) made of amorphous silicon and impurity amorphous silicon.

In the pixel region P, a pixel electrode 60 connected to the drain electrode 66 of the thin film transistor Tr and having a plate shape is formed. The pixel electrode 60 is formed to almost cover the area of the pixel region P, and thus is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

A protective layer 68, which is an insulating layer, is formed on the thin film transistor Tr and the pixel electrode 60, and a plurality of slits overlapping the pixel electrode 60 having a plate shape on the protective layer 68. A common electrode 70 having a hole 72 having a shape is formed. The common electrode 70 is formed on the entire surface of the first substrate 50, and thus is made of a transparent conductive material such as ITO and IZO. The first substrate 50 on which the above components are formed is called an array substrate.

When a voltage is applied between the common electrode 70 and the plate-shaped pixel electrode 60, a fringe field is formed to drive the liquid crystal layer 90, thereby improving transmission efficiency to produce a high quality image. It becomes possible to display.

The second substrate 80 includes a black matrix 82 for preventing light leakage in response to the data line 62, the gate line 52, and the thin film transistor Tr. In addition, a color filter layer 84 is formed corresponding to the pixel region P, and an overcoat layer 86 is formed on the black matrix 82 and the color filter layer 84. The second substrate 80 on which the above components are formed is called a color filter substrate.

For example, the black matrix 84 formed to correspond to the data line 62 is configured to cover the area between the data line 62 and the data line 62 and the pixel electrode 60. . In addition, in consideration of the alignment margin of the first and second substrates 50 and 80, the edges of the pixel electrode 60 may be covered.

As such, the black matrix 82 formed on the second substrate 80, which is the upper substrate, may include the pixel electrode 60 as well as the data line 62 in consideration of the bonding margin between the first and second substrates 50 and 80. It should be formed wide so as to cover the edge of the), thereby causing a problem that the aperture ratio is lowered.

In addition, the common electrode 70 formed on the entire surface of the first substrate 50, which is a lower substrate, is made of a transparent conductive material such as ITO and IZO. Since such material has high resistance, signal delay occurs.

In addition, the common electrode 70 is formed to overlap the data line 62, thereby generating cross-talk, thereby increasing the signal delay of the common electrode 70.

The present invention is to solve the problem that the opening ratio is lowered by the width of the black matrix considering the bonding margin as described above.

In addition, the lower the resistance of the common electrode to improve the signal delay caused by its own resistance.

In addition, the signal delay of the common electrode is further improved by reducing cross talk with the data lines.

In order to solve the above problems, the present invention includes a gate wiring and a data wiring to define a pixel area crossing each other on the substrate; A thin film transistor connected to the gate line and the data line; A pixel electrode positioned in the pixel region and connected to the thin film transistor and spaced apart from the gate line and the data line; A protective layer covering the gate wiring, the data wiring, the thin film transistor and the pixel electrode; A common electrode on the passivation layer and overlapping the gate wiring, the data wiring, and the pixel electrode and having a plurality of first holes corresponding to the pixel electrode; An array substrate for a liquid crystal display device includes a first light blocking pattern covering the data line and a spaced area between the data line and the pixel electrode and overlapping and contacting the common electrode.

And a second light blocking pattern covering the gate line and the spaced area between the gate line and the pixel electrode and overlapping and contacting the common electrode.

And a third light blocking pattern covering the thin film transistor and overlapping and contacting the common electrode.

The common electrode may have a second hole corresponding to the thin film transistor.

In another aspect, the present invention provides a semiconductor device comprising: a gate wiring and a data wiring crossing a mutually defined pixel region on a first substrate; A thin film transistor positioned on the first substrate and connected to the gate line and the data line; A pixel electrode on the first substrate, the pixel electrode being connected to the thin film transistor and spaced apart from the gate line and the data line; A protective layer covering the gate wiring, the data wiring, the thin film transistor and the pixel electrode; A common electrode on the passivation layer and overlapping the gate wiring, the data wiring, and the pixel electrode, the common electrode having a plurality of first holes corresponding to the pixel electrode; A first light blocking pattern covering the data line and the spaced area between the data line and the pixel electrode and overlapping and contacting the common electrode; A color filter substrate positioned on a second substrate facing the first substrate, the color filter substrate corresponding to the pixel region; An overcoat layer on the color filter substrate; It provides a liquid crystal display device comprising a liquid crystal layer positioned on the overcoat layer.

And a second light blocking pattern covering the gate line and the spaced area between the gate line and the pixel electrode and overlapping and contacting the common electrode.

And a third light blocking pattern covering the thin film transistor and overlapping and contacting the common electrode.

The common electrode may have a second hole corresponding to the thin film transistor.

An auxiliary color filter layer is positioned between the color filter layer and the overcoat layer to correspond to the second hole, the color filter layer is any one of red, green, and blue color filter patterns, and the auxiliary color filter layer is red, green, and blue. It is characterized by one of the other color filter patterns.

According to the present invention, the black matrix for preventing light leakage in the data wiring and the like is formed on the same substrate as the data wiring, thereby reducing the aperture ratio caused in consideration of the bonding margin.

In addition, the resistance of the common electrode can be lowered by forming the black matrix from a metal material and bringing it into contact with the common electrode.

In addition, as the resistance of the common electrode is lowered, cross-talk with the data line is also minimized, thereby preventing signal delay of the common electrode.

In addition, by forming the black matrix through a common electrode forming process, there is an advantage that the increase in manufacturing process and manufacturing cost can be minimized.

Hereinafter, the present invention will be described in detail with reference to the drawings.

5 is a plan view of a portion of an array substrate for a fringe field switching mode liquid crystal display according to a first embodiment of the present invention.

As illustrated, the array substrate for the fringe field switching mode liquid crystal display device includes a gate wiring 114, a data wiring 140, a thin film transistor Tr, and a pixel electrode formed on the first substrate 110. 130, a common electrode (not shown), and a light blocking pattern 160.

The gate line 114 extends in the first direction, and the data line 140 extends in the second direction to cross the gate line 114 to define the pixel area P. As shown in FIG. In this case, the pixel area P surrounded by the gate line 114 and the data line 140 in the drawing is referred to as a first pixel area P1, and the left and right sides of the first pixel area P1 are referred to. The pixel region P positioned at is referred to as the second and third pixel regions P2 and P3.

The thin film transistor Tr is positioned at an intersection point of the gate line 114 and the data line 140 in each pixel area P. As shown in FIG. The thin film transistor Tr is connected to the gate line 114 and the data line 140.

The thin film transistor Tr includes a gate electrode 112, a gate insulating layer (not shown), an active layer (not shown) made of pure amorphous silicon, and an ohmic contact layer (not shown) made of impurity amorphous silicon. A layer (not shown), and a source electrode 142 and a drain electrode 144.

The pixel electrode 130 is positioned in each of the first to third pixel regions P1, P2, and P3 and is connected to the drain electrode 144 of the thin film transistor Tr and has a plate shape.

The common electrode overlaps the plate-shaped pixel electrode 130 and has a plurality of slit-shaped holes 152. The common electrode is formed on the entire surface of the first to third pixel areas P1, P2, and P3.

In addition, the light blocking pattern 160 is disposed on the common electrode, and blocks light in correspondence to the data line 140, the gate line 114, and the thin film transistor Tr. In addition, the light blocking pattern 160 is in contact with the common electrode.

When voltage is applied between the common electrode and the plate-shaped pixel electrode 130, a fringe field is formed to drive the liquid crystal, thereby improving transmission efficiency and displaying a high quality image.

6 and 7 show a cross section of the liquid crystal display according to the present invention. 6 is a cross-sectional view taken along the line VI-VI of FIG. 5, and FIG. 7 is a cross-sectional view taken along the line VII-VII of FIG. 5.

As illustrated, the liquid crystal display device is interposed between a first substrate 110, a second substrate 170 facing the first substrate 110, and the first and second substrates 110 and 170. The liquid crystal layer 180 is included.

On the first substrate 110, a gate line 114 connected to the gate electrode 112 and the gate electrode 112 and positioned at a boundary between the first to third pixel areas P1, P2, and P3 is positioned. . For example, the gate electrode 112 and the gate wiring 114 are made of any one of aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), copper (Cu), and copper alloy. In addition, a gate insulating layer 118 is disposed to cover the gate electrode 112 and the gate wiring 114. For example, the gate insulating layer 118 is made of an inorganic insulating material such as silicon oxide or silicon nitride.

On the gate insulating layer 118, a semiconductor layer 120 including an active layer 120a made of pure amorphous silicon and an ohmic contact layer 120b made of impurity amorphous silicon is overlapped with the gate electrode 112. In addition, a plate-shaped pixel electrode 130 is positioned on each of the pixel regions P on the gate insulating layer 118. The pixel electrode 130 is spaced apart from the gate line 114 at a predetermined interval. The pixel electrode 130 is made of a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).

The source electrode 142 and the drain electrode 144 are spaced apart from each other on the semiconductor layer 120. A central portion of the active layer 120a is exposed between the source electrode 142 and the drain electrode 144, and the exposed active layer 120a forms a channel. The drain electrode 144 is in contact with the pixel electrode 130. The gate electrode 112, the gate insulating layer 118, the semiconductor layer 120, the source electrode 142, and the drain electrode 144 form a thin film transistor Tr.

Although the pixel electrode 130 and the drain electrode 144 directly contact each other in the drawing, an insulating layer having a contact hole is disposed on the drain electrode, and the pixel electrode is positioned on the insulating layer, and the contact hole is disposed. The contact may be in contact with the drain electrode.

In addition, the data line 140 connected to the source electrode 142 is positioned on the gate insulating layer 118. The data line 140 crosses the gate line 114 to define the first to third pixel areas P1, P2, and P3. That is, the data line 140 is positioned at the boundary between the first to third pixel areas P1, P2, and P3. The data line 140 is spaced apart from the pixel electrode 130 by a predetermined interval.

The passivation layer 146 is positioned to cover the thin film transistor Tr, the data line 140, and the pixel electrode 130. The protective layer 146 may be made of an inorganic insulating material such as silicon oxide or silicon nitride or an organic insulating material such as photoacryl or benzocyclobutene.

The common electrode 150 covering the entire surface of the first to third pixel areas P1, P2, and P3 and having a plurality of holes 152 is disposed on the passivation layer 146. The plurality of holes 152 correspond to the pixel electrode 130. The common electrode 150 is made of a transparent conductive material such as ITO and IZO.

In addition, on the common electrode 150, the first light blocking pattern 160a corresponding to the data line 140, the second light blocking pattern 160b corresponding to the gate line 114, and the thin film transistor Tr. The light blocking pattern 160 including the third light blocking pattern 160c is positioned. The first to third light blocking patterns 160a, 160b, and 160c are connected to each other.

The first light blocking pattern 160a covers the data line 140 and the pixel electrode 130 and the data line 140. That is, when the data line 140 has the first width and the area between the data line 140 and the pixel electrode 130 has the second width, the first light blocking pattern 160a has the first width. And a third width equal to the sum of the second widths. That is, the width of the first light blocking pattern 160a corresponds to the distance between the pixel electrodes 130 positioned in the adjacent pixel region P along the gate line 114. The width of the first light blocking pattern 160a is the distance between the pixel electrode 130 positioned in the first pixel region P and the pixel electrode 130 positioned in the second pixel region P or the first width. The distance between the pixel electrode 130 positioned in the second pixel region P and the pixel electrode 130 positioned in the third pixel region P corresponds to the distance. In contrast, the first light blocking pattern 160a may have a width greater than the sum of the first width and the second width.

Similarly, if the gate wiring 114 has a fourth width and the region between the gate wiring 114 and the pixel electrode 130 has a fifth width, the second light blocking pattern 160b may be formed. And a sixth width equal to the sum of the fourth width and the fifth width. That is, the width of the second light blocking pattern 160b corresponds to the distance between the pixel electrodes 130 positioned in the adjacent pixel region P along the data line 140. In contrast, the second light blocking pattern 160b may have a width greater than the sum of the fourth width and the fifth width.

In addition, the third light blocking pattern 160c may correspond to the size of the thin film transistor Tr and may cover the channel of the active layer 120a to prevent photo-current.

The light blocking pattern 160 is made of an opaque metal material such as aluminum, aluminum alloy, copper, copper alloy, molybdenum, molybdenum alloy, molybdenum-titanium alloy (MoTi). Accordingly, light leakage around the data line 140, the gate line 114, and the thin film transistor Tr can be prevented, and photo-current generated when light enters a channel of the thin film transistor Tr. It is possible to prevent the deterioration of the characteristics of the thin film transistor Tr.

The common electrode 150 and the light blocking pattern 160 may be formed by one mask process by successively stacking a transparent conductive material layer and an opaque metal material layer and then performing a semi-transmissive mask process.

In addition, since the light blocking pattern 160 is in contact with the common electrode 150, the resistance of the common electrode 150 may be lowered. As a result, crosstalk generated between the common electrode 150 and the data line 140 can be minimized, thereby solving the signal delay problem of the common electrode 150.

The color filter layer 172 is positioned on the second substrate 170 to correspond to each of the first to third pixel areas P1, P2, and P3. The color filter layer 172 includes red (R), green (G), and blue (B) color filter patterns. In addition, an overcoat layer 174 is positioned on the color filter 172. The overcoat layer 174 flattens the upper surface of the color filter layer 172 and prevents contamination of the liquid crystal layer 180 by the material of the color filter layer 172.

Unlike the conventional liquid crystal display, the black matrix 82 of FIG. 4 does not exist on the second substrate 170 of the liquid crystal display of the present invention. This is because the light shielding pattern 160 positioned on the first substrate 110 serves as a black matrix. Since the light shielding pattern 160 is positioned on the first substrate 110, it is not necessary to consider the bonding margin, and thus the reduction of the aperture ratio may be minimized. In addition, the light blocking pattern 160 may be in contact with the common electrode 150 to prevent signal delay of the common electrode 150.

8 and 9 are cross-sectional views of a liquid crystal display according to a second exemplary embodiment of the present invention.

As shown, the liquid crystal display device is interposed between a first substrate 210, a second substrate 270 facing the first substrate 210, and the first and second substrates 210 and 270. The liquid crystal layer 280 is included.

A gate line 214 connected to the gate electrode 112 and the gate electrode 112 and positioned at a boundary between the first and third pixel areas P1, P2, and P3 is positioned on the first substrate 210. . For example, the gate electrode 212 and the gate wiring 214 are made of any one of aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), copper (Cu), and copper alloy. In addition, a gate insulating layer 218 is positioned to cover the gate electrode 212 and the gate wiring 214. For example, the gate insulating layer 218 is made of an inorganic insulating material such as silicon oxide or silicon nitride.

On the gate insulating layer 218, a semiconductor layer 220 including an active layer 220a made of pure amorphous silicon and an ohmic contact layer 220b made of impurity amorphous silicon overlaps with the gate electrode 212. In addition, a plate-shaped pixel electrode 230 is positioned on each of the pixel regions P on the gate insulating layer 218. The pixel electrode 230 is spaced apart from the gate line 214 by a predetermined interval. The pixel electrode 230 is made of a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).

The source electrode 242 and the drain electrode 244 are spaced apart from each other on the semiconductor layer 220. A central portion of the active layer 220a is exposed between the source electrode 242 and the drain electrode 244, and the exposed active layer 220a forms a channel. The drain electrode 244 is in contact with the pixel electrode 230. The gate electrode 212, the gate insulating layer 218, the semiconductor layer 220, the source electrode 242, and the drain electrode 244 form a thin film transistor Tr.

In the drawing, the pixel electrode 230 and the drain electrode 244 are in direct contact with each other. However, an insulating layer having a contact hole is disposed on the drain electrode, and the pixel electrode is positioned on the insulating layer. The contact may be in contact with the drain electrode.

In addition, the data line 240 connected to the source electrode 242 is positioned on the gate insulating layer 218. The data line 240 crosses the gate line 214 to define the first to third pixel areas P1, P2, and P3. That is, the data line 240 is located at the boundary between the first to third pixel areas P1, P2, and P3. The data line 240 is spaced apart from the pixel electrode 230 by a predetermined interval.

The passivation layer 246 is disposed to cover the thin film transistor Tr, the data line 240, and the pixel electrode 230. The protective layer 246 may be made of an inorganic insulating material such as silicon oxide or silicon nitride, or an organic insulating material such as photoacryl or benzocyclobutene.

The first blocking pattern 260a corresponding to the data line 240, the second blocking pattern 260b corresponding to the gate line 214, and the thin film transistor Tr may be formed on the passivation layer 246. The light blocking pattern 260 including the corresponding third light blocking pattern 260c is positioned. The first to third light blocking patterns 260a, 260b, and 260c are connected to each other.

The first light blocking pattern 260a covers the data line 240 and the pixel electrode 230 and the data line 240. That is, when the data line 240 has the first width and the area between the data line 240 and the pixel electrode 230 has the second width, the first light blocking pattern 260a is the first width. And a third width equal to the sum of the width and the second width. That is, the width of the first light blocking pattern 260a corresponds to the distance between the pixel electrodes 230 positioned in the adjacent pixel region P along the gate line 214. In contrast, the first light blocking pattern 260a may have a width greater than the sum of the first width and the second width.

Similarly, when the gate wiring 214 has a fourth width and the region between the gate wiring 214 and the pixel electrode 230 has a fifth width, the second light blocking pattern 260b is formed in the second width. And a sixth width equal to the sum of the four widths and the fifth width. That is, the width of the second light blocking pattern 260b corresponds to the distance between the pixel electrodes 230 positioned in the adjacent pixel region P along the data line 240. In contrast, the second light blocking pattern 260b may have a width greater than the sum of the fourth width and the fifth width.

In addition, the third light blocking pattern 260c corresponds to the size of the thin film transistor Tr and may cover the channel of the active layer 220a to prevent photo-current.

The light shielding pattern 260 is made of an opaque metal material such as aluminum, aluminum alloy, copper, copper alloy, molybdenum, molybdenum alloy, molybdenum-titanium alloy (MoTi). Accordingly, light leakage around the data line 240, the gate line 214, and the thin film transistor Tr can be prevented, and photo-current generated when light enters a channel of the thin film transistor Tr. It is possible to prevent the deterioration of the characteristics of the thin film transistor Tr.

In addition, the common electrode 250 is positioned on the light blocking pattern 260 and the protective layer 246 corresponding to an entire surface of the first to third pixel areas P1, P2, and P3. The common electrode 250 has a plurality of holes 252 corresponding to the pixel electrode 230. The common electrode 250 is made of a transparent conductive material such as ITO and IZO.

The common electrode 150 is positioned in contact with the light blocking pattern 260 to lower the resistance of the common electrode 250. As a result, crosstalk generated between the common electrode 250 and the data line 240 can be minimized, thereby solving the signal delay problem of the common electrode 250.

The color filter layer 272 is positioned on the second substrate 270 to correspond to each of the first to third pixel areas P1, P2, and P3. The color filter layer 272 includes red (R), green (G), and blue (B) color filter patterns. In addition, an overcoat layer 274 is positioned on the color filter 272. The overcoat layer 274 flattens the upper surface of the color filter layer 272 and prevents contamination of the liquid crystal layer 280 by the material of the color filter layer 272.

Unlike the conventional liquid crystal display, the black matrix (82 of FIG. 4) does not exist on the second substrate 270 of the liquid crystal display of the present invention. In the present invention, the light blocking pattern 260 positioned on the first substrate 210 serves as a black matrix. Since the light shielding pattern 260 is positioned on the first substrate 210, it is not necessary to consider the bonding margin and thus minimize the decrease in the aperture ratio. In addition, the light blocking pattern 260 may be in contact with the common electrode 250, thereby preventing a signal delay of the common electrode 250.

10 is a plan view of an array substrate for a fringe field switching mode liquid crystal display according to a third embodiment of the present invention.

As illustrated, an array substrate for a fringe field switching mode liquid crystal display device includes a gate wiring 314, a data wiring 340, a thin film transistor Tr, and a pixel electrode formed on the first substrate 310. 330, a common electrode (not shown), and a light blocking pattern 360.

The gate line 314 extends in the first direction, and the data line 340 extends in the second direction to cross the gate line 314 to define the pixel area P. As shown in FIG. In this case, the pixel area P enclosed by the gate line 314 and the data line 340 is referred to as a first pixel area P1, and the left and right sides of the first pixel area P1 are referred to as the first pixel area P1. The pixel region P positioned at is referred to as the second and third pixel regions P2 and P3.

The thin film transistor Tr is positioned at an intersection point of the gate line 314 and the data line 340 in each pixel area P. The thin film transistor Tr is connected to the gate line 314 and the data line 340.

The thin film transistor Tr includes a gate electrode 312, a gate insulating layer (not shown), an active layer (not shown) made of pure amorphous silicon, and an ohmic contact layer (not shown) made of impurity amorphous silicon. A layer (not shown), and a source electrode 342 and a drain electrode 344.

The pixel electrode 330 is positioned in each of the first to third pixel regions P1, P2, and P3 and is connected to the drain electrode 344 of the thin film transistor Tr and has a plate shape.

The common electrode is formed on the entire surface of the first to third pixel areas P1, P2, and P3. The common electrode has a plurality of first holes 352 corresponding to the plate-shaped pixel electrodes 330 and second holes 354 corresponding to the thin film transistor Tr.

In addition, the light blocking pattern 360 is disposed on the common electrode, and blocks light in correspondence to the data line 340, the gate line 314, and the thin film transistor Tr. In addition, the light blocking pattern 360 is in contact with the common electrode.

When a voltage is applied between the common electrode and the plate-shaped pixel electrode 330, a fringe field is formed to drive the liquid crystal, thereby improving transmission efficiency and displaying a high quality image.

11 and 12 show a cross section of a liquid crystal display according to the present invention. FIG. 11 is a cross-sectional view taken along line XI-XI of FIG. 10, and FIG. 12 is a cross-sectional view taken along line XII-XII of FIG. 10.

As illustrated, the liquid crystal display device is interposed between a first substrate 310, a second substrate 370 facing the first substrate 310, and the first and second substrates 310 and 370. The liquid crystal layer 380 is included.

A gate line 314 connected to the gate electrode 312 and the gate electrode 312 and positioned at a boundary between the first to third pixel areas P1, P2, and P3 is positioned on the first substrate 310. . For example, the gate electrode 312 and the gate wiring 314 may be formed of any one of aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), copper (Cu), and copper alloy. In addition, a gate insulating layer 318 is positioned to cover the gate electrode 312 and the gate wiring 314. For example, the gate insulating layer 318 is made of an inorganic insulating material such as silicon oxide or silicon nitride.

On the gate insulating layer 318, a semiconductor layer 320 including an active layer 320a made of pure amorphous silicon and an ohmic contact layer 320b made of impurity amorphous silicon overlaps with the gate electrode 312. In addition, a plate-shaped pixel electrode 330 is positioned on each of the pixel regions P on the gate insulating layer 318. The pixel electrode 330 is spaced apart from the gate line 314 by a predetermined interval. The pixel electrode 330 is made of a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).

The source electrode 342 and the drain electrode 344 are spaced apart from each other on the semiconductor layer 320. A central portion of the active layer 320a is exposed between the source electrode 342 and the drain electrode 344, and the exposed active layer 120a forms a channel. The drain electrode 344 is in contact with the pixel electrode 330. The gate electrode 312, the gate insulating layer 318, the semiconductor layer 320, the source electrode 342, and the drain electrode 344 form a thin film transistor Tr.

Although the pixel electrode 330 and the drain electrode 344 are in direct contact with each other in the drawing, an insulating layer having a contact hole is disposed on the drain electrode, and the pixel electrode is positioned on the insulating layer. The contact may be in contact with the drain electrode.

In addition, a data line 340 connected to the source electrode 342 is positioned on the gate insulating layer 318. The data line 340 crosses the gate line 314 to define the first to third pixel areas P1, P2, and P3. That is, the data line 340 is positioned at the boundary between the first to third pixel areas P1, P2, and P3. The data line 340 is spaced apart from the pixel electrode 330 by a predetermined interval.

The passivation layer 346 is disposed to cover the thin film transistor Tr, the data line 340, and the pixel electrode 330. The protective layer 346 may be made of an inorganic insulating material such as silicon oxide or silicon nitride, or an organic insulating material such as photoacryl or benzocyclobutene.

The common electrode 350 is disposed on the passivation layer 346 to cover the entire surface of the first to third pixel areas P1, P2, and P3. The common electrode 350 includes a plurality of first holes 352 corresponding to the pixel electrode 330 and second holes 354 corresponding to the thin film transistor Tr. Therefore, the protective layer 346 corresponding to the thin film transistor Tr comes into contact with the liquid crystal layer 380. When the common electrode 350 covers the thin film transistor Tr, deterioration of characteristics of the thin film transistor Tr may occur due to off-current. In order to prevent the common electrode 350, the common electrode 350 may be It has a second hole 354 corresponding to the thin film transistor Tr. The common electrode 350 is made of a transparent conductive material such as ITO and IZO.

In addition, the light blocking pattern 160 includes a first light blocking pattern 360a corresponding to the data line 340 and a second light blocking pattern 360b corresponding to the gate line 314 on the common electrode 350. ) Is located. The first and third light blocking patterns 160a and 160b are connected to each other.

The first light blocking pattern 360a covers the data line 340 and the pixel electrode 330 and the data line 340. That is, when the data line 340 has the first width and the area between the data line 340 and the pixel electrode 330 has the second width, the first light blocking pattern 360a has the first width. And a third width equal to the sum of the second widths. That is, the width of the first light blocking pattern 360a corresponds to the distance between the pixel electrodes 330 positioned in the adjacent pixel region P along the gate line 314. The width of the first light blocking pattern 360a is the distance between the pixel electrode 330 in the first pixel region P and the pixel electrode 330 in the second pixel region P or the first width of the first light blocking pattern 360a. The distance corresponds to the distance between the pixel electrode 330 positioned in the two pixel region P and the pixel electrode 330 positioned in the third pixel region P. FIG. In contrast, the first light blocking pattern 360a may have a width greater than the sum of the first width and the second width.

Similarly, when the gate wiring 314 has a fourth width and the region between the gate wiring 314 and the pixel electrode 330 has a fifth width, the second light blocking pattern 360b is formed in the second width. And a sixth width equal to the sum of the four widths and the fifth width. That is, the width of the second light blocking pattern 360b corresponds to the distance between the pixel electrodes 330 positioned in the adjacent pixel region P along the data line 340. In contrast, the second light blocking pattern 360b may have a width greater than the sum of the fourth width and the fifth width.

The light blocking pattern 360 is made of an opaque metal material such as aluminum, aluminum alloy, copper, copper alloy, molybdenum, molybdenum alloy, molybdenum-titanium alloy (MoTi). Therefore, light leakage around the data line 340 and the gate line 314 can be prevented.

The common electrode 350 and the light blocking pattern 360 may be formed by one mask process by successively stacking a transparent conductive material layer and an opaque metal material layer and then performing a semi-transmissive mask process.

In addition, since the light blocking pattern 360 is in contact with the common electrode 350, the resistance of the common electrode 350 may be lowered. As a result, crosstalk generated between the common electrode 350 and the data line 340 can be minimized, thereby solving the signal delay problem of the common electrode 350.

In the third exemplary embodiment, the light blocking pattern 360 may be disposed on the passivation layer 346 and the common electrode 350 may be disposed to cover the light blocking pattern 360, as in the second exemplary embodiment.

On the other hand, the color filter layer 372 is positioned on the second substrate 370 corresponding to each of the first to third pixel areas P1, P2, and P3. The color filter layer 172 includes red (R), green (G), and blue (B) color filter patterns. In addition, an auxiliary color filter layer 373 is disposed on the color filter layer 372 to correspond to the thin film transistor Tr. That is, the auxiliary color filter layer 373 corresponds to the position of the second hole 354. For example, when the color filter layer 372 of the first pixel area P1 is a green color filter pattern, the auxiliary color filter layer 373 may be formed of a red or blue color filter. Although light may be incident on the thin film transistor Tr in the present embodiment, light may be blocked by the color filter layer 372 and the auxiliary color filter layer 373. Therefore, the problem of deterioration of the thin film transistor (Tr) characteristics due to photocurrent does not occur.

In addition, an overcoat layer 374 is positioned on the color filter 372 and the auxiliary color filter layer 373. The overcoat layer 374 flattens the upper surfaces of the color filter layer 372 and the auxiliary color filter layer 373, and the liquid crystal layer 380 by the material of the color filter layer 372 and the auxiliary color filter layer 373. ) To prevent contamination.

Unlike the conventional liquid crystal display, the black matrix (82 of FIG. 4) does not exist on the second substrate 370 of the liquid crystal display of the present invention. This is because the light blocking pattern 360 positioned on the first substrate 310 serves as a black matrix. Since the light shielding pattern 360 is positioned on the first substrate 310, it is not necessary to consider the bonding margin, and thus the reduction of the aperture ratio may be minimized. In addition, the light blocking pattern 360 may contact the common electrode 350 to prevent a signal delay of the common electrode 350.

In addition, since the common electrode 350 has a second hole 354 corresponding to the thin film transistor Tr, deterioration of the thin film transistor Tr characteristic due to off current can be prevented, and the auxiliary color filter layer 373 Is formed corresponding to the thin film transistor (Tr), the photocurrent problem is also prevented.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art various modifications and changes of the present invention without departing from the spirit and scope of the present invention described in the claims below I can understand that you can.

1 is a cross-sectional view of a general transverse electric field type liquid crystal display device.

2A and 2B are cross-sectional views illustrating operations of ON and OFF states of a general transverse electric field type liquid crystal display device, respectively.

3 is a plan view of one pixel area of an array substrate for a conventional fringe field switching mode liquid crystal display device.

FIG. 4 is a cross-sectional view of the liquid crystal display taken along the cutting line IV-IV of FIG. 3.

5 is a plan view of a portion of an array substrate for a fringe field switching mode liquid crystal display according to a first embodiment of the present invention.

6 is a cross-sectional view taken along the line VI-VI of FIG. 5.

FIG. 7 is a cross-sectional view taken along the line VII-VII of FIG. 5.

8 and 9 are cross-sectional views of a liquid crystal display according to a second exemplary embodiment of the present invention.

10 is a plan view of an array substrate for a fringe field switching mode liquid crystal display according to a third embodiment of the present invention.

FIG. 11 is a cross-sectional view taken along the line XI-XI of FIG. 10.

12 is a cross-sectional view taken along line XII-XII of FIG. 10.

Claims (9)

Gate wiring and data wiring crossing the substrate to define pixel regions therebetween; A thin film transistor connected to the gate line and the data line; A pixel electrode positioned in the pixel region and connected to the thin film transistor and spaced apart from the gate line and the data line; A protective layer covering the gate wiring, the data wiring, the thin film transistor and the pixel electrode; A common electrode on the passivation layer and overlapping the gate wiring, the data wiring, and the pixel electrode, the common electrode having a plurality of first holes corresponding to the pixel electrode; A first light blocking pattern covering the data line and a spaced area between the data line and the pixel electrode and overlapping and contacting the common electrode; Array substrate for a liquid crystal display device comprising a. The method of claim 1, And a second light blocking pattern covering the gate line and the spaced area between the gate line and the pixel electrode and overlapping and contacting the common electrode. 3. The method of claim 2, And a third light blocking pattern covering the thin film transistor and overlapping and contacting the common electrode. The method of claim 1, And the common electrode has a second hole corresponding to the thin film transistor. Gate wiring and data wiring intersecting each other on the first substrate to define a pixel region; A thin film transistor positioned on the first substrate and connected to the gate line and the data line; A pixel electrode on the first substrate, the pixel electrode being connected to the thin film transistor and spaced apart from the gate line and the data line; A protective layer covering the gate wiring, the data wiring, the thin film transistor and the pixel electrode; A common electrode on the passivation layer and overlapping the gate wiring, the data wiring, and the pixel electrode, the common electrode having a plurality of first holes corresponding to the pixel electrode; A first light blocking pattern covering the data line and the spaced area between the data line and the pixel electrode and overlapping and contacting the common electrode; A color filter substrate positioned on a second substrate facing the first substrate, the color filter substrate corresponding to the pixel region; An overcoat layer on the color filter substrate; It includes a liquid crystal layer located on the overcoat layer LCD display device. The method of claim 5, And a second light blocking pattern covering the gate line and the spaced area between the gate line and the pixel electrode and overlapping and contacting the common electrode. The method of claim 6, And a third light blocking pattern covering the thin film transistor and overlapping and contacting the common electrode. The method of claim 5, And the common electrode has a second hole corresponding to the thin film transistor. The method of claim 8, An auxiliary color filter layer is positioned between the color filter layer and the overcoat layer to correspond to the second hole, the color filter layer is any one of red, green, and blue color filter patterns, and the auxiliary color filter layer is red, green, and blue. Liquid crystal display device characterized in that the other one of the color filter pattern.

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