KR102438251B1 - Liquid crystal display device and method for fabricating the same - Google Patents

Abstract

The present invention is provided in a dummy color filter provided in each non-display portion of the first, second, and third pixel areas defined on a first substrate and a dummy color filter provided in each of the non-display portions of the first, second, and third pixel areas, The first, second, and third color filter openings asymmetrically configured for each 1, 2, and 3 pixel areas are provided on the first, second, and third color filters and the dummy color filter, and the first, second, and second color filter openings of the first and second pixel areas are provided on the first, second and third color filters and the dummy color filter. a planarization layer having first and second drain electrode contact holes in the color filter opening and having a third drain electrode contact hole and a common wiring contact hole in the third color filter opening of the third pixel region; a liquid crystal display including first, second, and third pixel electrodes connected to the first, second, and third drain electrodes through the third drain electrode contact hole, and a common electrode connected to the common wiring through the common wiring contact hole; to provide.

Description

Liquid crystal display device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a liquid crystal display device for preventing a column spacer (CS) from falling out in a color filter opening in a color on TFT (COT) structure, and a method for manufacturing the same.

Recently, the liquid crystal display device has been spotlighted as a next-generation high-tech display device with low power consumption, good portability, high technology intensive, and high added value.

Among these liquid crystal displays, an active matrix liquid crystal display equipped with a thin film transistor, which is a switching element that can control the on/off of voltage for each pixel, has the most excellent resolution and video realization ability. is attracting attention.

Recently, a color filter on TFT (COT) structure in which a color filter is formed on a lower substrate to prevent a decrease in the aperture ratio as the area of the black matrix is enlarged by the bonding margin between the upper substrate and the lower substrate has been proposed.

1 is a plan view of a conventional COT structure liquid crystal display device.

FIG. 2 is a cross-sectional view of the liquid crystal display taken along line II-II of FIG. 1 .

3 is a plan view schematically illustrating a case in which a column spacer is moved in a conventional COT structure liquid crystal display device.

FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. 3 , and schematically shows a cross-section inside the color filter opening.

In the conventional COT structure liquid crystal display device, as shown in FIGS. 1 and 2 , a plurality of gate wirings 11 are formed on a first substrate 10 , and are vertically intersected with the gate wirings 11 and arranged. The first, second, and third data lines 14a, 14b, and 14c to be used are formed. In this case, first, second, and third pixel regions P1, P2, and P3 constituting one pixel are disposed between the gate wiring 11 and the first, second, and third data lines 14a, 14b, and 14c, which are arranged to cross each other. This is defined

In addition, a common wiring 12 is formed on the first substrate 10 in parallel to the gate wiring 11 .

Thin film transistors T1 , T2 , and T3 are provided at intersections of the gate wiring 11 and the first, second, and third data lines 14a , 14b and 14c of the first substrate 10 . The thin film transistors T1 , T2 , and T3 transmit data signals from the first, second and third data lines 14a , 14b and 14c to the first, second, and third pixels in response to the gate signal from the gate line 11 . It is supplied to the electrodes 25a, 25b, and 25c.

In this case, the thin film transistors T1 , T2 , and T3 have a gate electrode 11a connected to the gate line 11 , and first, second and third sources connected to the first, second, and third data lines 14a , 14b and 14c . Electrodes 15a, 15b, and 15c and first, second, and third drain electrode contact holes 23a, 23b, and 23c connected to first, second, and third pixel electrodes 25a, 25b, and 25c , 3 drain electrodes 16a, 16b, 16c and the first, second, and third source electrodes 15a, 15b, 15c and the first, second, and third drain electrodes ( An active layer (not shown) for forming a conduction channel between 16a, 16b, and 16c is provided. In this case, the first, second, and third source electrodes 15a, 15b, and 15c have the same symmetrical structure, and the first, second, and third drain electrodes 16a, 16b, and 16c have the same symmetrical structure. has

In addition, the active layer (not shown) may be formed by sequentially stacking a semiconductor layer and an ohmic contact layer.

The thin film transistors T1, T2, and T3 are insulated from the gate electrode 11a, the first, second, and third source electrodes 15a, 15b, and 15c, and the first, second, and third drain electrodes 16a, 16b, and 16c. It further includes a gate insulating layer 13 for

In addition, red (R), green (G), and blue (B) color filters 18 , 19 and 20 are formed in each of the pixel regions P1 , P2 , and P3 of the first substrate 10 . In particular, a red (R) color filter 18 is formed in the first pixel region P1 , a green (G) color filter 19 is formed in the second pixel region P, and a third pixel region P ), a blue (B) color filter 20 is formed.

In this case, the non-display portions NP1, NP2, and NP3 in the first, second, and third pixel regions P1, P2, and P3, for example, the thin film transistors T1, T2, T3, the gate wiring 11 and the common A dummy red color filter 18a and a dummy blue color filter 20a are stacked on the wiring 12 and the first, second, and third data lines 14a, 14b, and 14c.

The stacked dummy red color filters 18a and dummy blue color filters 20a in the non-display units NP1, NP2, and NP3 positioned adjacent to each of the pixel regions P1, P2, and P3 include the first, 2 and 3 color filter openings 21a, 21b, and 21c are respectively formed. At this time, the first, second, and third color filter openings 21a, 21b, and 21c are not only the first, second, and third drain electrodes 16a, 16b, and 16c, but also the first, second, and third drain electrodes 16a. , 16b, 16c) overlaps with a portion of the common wiring 12 that does not overlap. In this case, the first, second, and third color filter openings 21a, 21b, and 21c have the same area size.

In addition, the red (R), green (G), and blue (B) color filters 18 , 19 and 20 , as well as the dummy red color filter 18a and the dummy blue color filter 20a , and each non-display unit NP1 , A planarization layer 22 is formed on the entire surface of the first, second, and third color filter openings 21a, 21b, and 21c provided in NP2 and NP3.

The planarization film 22 positioned in the first, second, and third color filter openings 21a, 21b, and 21c in the non-display portions NP1, NP2, NP3 in each of the pixel regions P1, P2, and P3 has its The first, second, and third drain electrode contact holes 23a, 23b, and 23c and the first and second drain electrode contact holes 23a, 23b, and 23c respectively exposing the first, second, and third drain electrodes 16a, 16b, and 16c and a portion of the common wiring 12 below, respectively. , 3 common wiring contact holes 24a, 24b, and 24c are respectively formed. In this case, the first, second, and third drain electrode contact holes 23a, 23b, and 23c and the first, second, and third common wiring contact holes 24a, 24b, and 24c are formed in the non-display portions NP1, NP2, and NP3, respectively. It is positioned in each of the color filter openings 21a, 21b, and 21c.

The first, second, and third drain electrode contact holes 23a, 23b, and 23c are formed on the planarization layer 22 in each of the color filter openings 21a, 21b, and 21c for each of the pixel regions P1, P2, and P3. Together with the first, second, and third pixel electrodes 25a, 25b, and 25c electrically connected to the first, second, and third drain electrodes 16a, 16b, and 16c of the provided thin film transistors T1, T2, and T3, First, second, and third common electrodes 26a, 26b, and 26c electrically connected to the common wiring 12 through the first, second, and third common wiring contact holes 24a, 24b, and 24c are formed.

A column spacer (CS) 33 is formed on the second substrate 30 that is bonded to the first substrate 10 to face it. In this case, the column spacers 33 are formed at positions overlapping the thin film transistors T1 , T2 , and T3 of the non-display portions NP1 , NP2 , and NP3 in each of the pixel regions P1 , P2 , and P3 .

In addition, a liquid crystal layer 40 is formed between the first substrate 10 and the second substrate 30 .

In the conventional liquid crystal display having such a configuration, when a voltage is applied to the pixel electrodes 25a, 25b, and 25c and the common electrodes 26a, 26b, and 26c, the liquid crystal layer 40 is formed by an electric field generated between them. An image is displayed by changing the arrangement state of the liquid crystal molecules.

However, according to the conventional liquid crystal display device, in applying the COT structure, the drain electrode contact hole for connecting the drain electrode and the pixel electrode in the color filter opening formed in the dummy color filter for signal connection, and the common wiring and the common electrode are connected. Since the common wiring contact hole is to be formed, the area of the color filter opening must be increased accordingly. As shown in FIG. 4 , this leads to a lack of a margin for the distance d1 between the color filter opening and the column spacer CS.

Due to the insufficient margin of the distance d1 between the color filter opening and the column spacer, the column spacer CS may fall into the color filter opening when the column spacer is shifted.

Therefore, as the column spacer is removed from the color filter opening according to the movement of the column spacer, a volume change in the cell occurs, resulting in poor touch and gravity.

In order to solve the above problems of the present invention, in a liquid crystal display device having a COT structure, the color filter opening and drain electrode formed in each pixel region are applied in an asymmetric structure to secure a distance margin between the column spacer and the color filter opening to achieve touch and gravity. An object of the present invention is to provide a liquid crystal display device capable of improving defects and a method for manufacturing the same.

In order to solve the above problems, in one aspect, the present invention provides first, second, and third pixel regions and the first and second gate lines defining the non-display portion and the first and second pixel regions arranged to cross each other on a first substrate to form one pixel. , 3 data lines, first, second, and third thin film transistors provided at one side of each of the first, second, and third pixel areas, and first, second, and third colors provided in the first, second, and third pixel areas a filter; a dummy color filter provided in each non-display unit of the first, second, and third pixel areas; The first, second, and third color filter openings are formed, and the first and second drain electrodes are provided on the first, second, and third color filters and the dummy color filter, and are provided in the first and second color filter openings of the first and second pixel regions. A planarization layer having a contact hole and having a third drain electrode contact hole and a common wiring contact hole in a third color filter opening of the third pixel region, and a first first through the first, second and third drain electrode contact holes 1, 2, and 3 pixel electrodes connected to the , 2 and 3 drain electrodes, and the first and second common electrodes spaced apart from the first, 2, and 3 pixel electrodes are connected to the common wiring through a common wiring contact hole. It is possible to provide a liquid crystal display device including a connected third common electrode.

In the liquid crystal display according to the present invention, an area of the first and second color filter openings may be smaller than an area of the third color filter opening.

In the liquid crystal display according to the present invention, the first drain electrode of the first pixel region and the first drain electrode of the second pixel region may have an asymmetrical structure.

In the liquid crystal display according to the present invention, the second drain electrode of the second pixel region may have an asymmetric structure different from that of the first and third drain electrodes of the first and third pixel regions.

In the liquid crystal display according to the present invention, the first color filter opening is located closer to the first data line of the first pixel area than the second data line of the second pixel area, and the second color filter opening is It may be located closer to the third data line of the third pixel area than the second data line of the second pixel area.

In the liquid crystal display according to the present invention, the first and second color filter openings overlap with the first and second drain electrodes and the common wiring arranged upwards and downwards, and the third color filter openings are arranged upwards and downwards. The third drain electrode and the common wiring area may overlap with the area having only the common wiring.

In the liquid crystal display according to the present invention, only the first and second drain electrode contact holes are located in the first and second color filter openings, and the third drain electrode contact hole and the common wiring are located in the third color filter opening. A contact hole may be located.

In the liquid crystal display according to the present invention, the non-display portion of the first, second, and third pixel regions may include a thin film transistor, a gate line, and a data line portion.

In the liquid crystal display device according to the present invention, the dummy color filter may have a stacked structure of a dummy red color filter and a dummy blue color filter.

In the liquid crystal display according to the present invention, a column spacer may be provided in a region corresponding to the thin film transistor of the non-display unit among the second substrates spaced apart from and bonded to the first substrate.

In the liquid crystal display according to the present invention, the column spacer may be provided on the second substrate corresponding to the second thin film transistor in the non-display portion of the second pixel area.

In order to solve the above problems, in another aspect, the present invention provides first, second, and third pixel regions and first and second gate wirings defining a non-display portion and the first and second pixel regions that are arranged to cross each other on a first substrate to form one pixel. , forming three data lines; forming first, second, and third thin film transistors on one side of each of the first, second, and third pixel regions; forming second and third color filters and forming dummy color filters in each non-display portion of the first, second, and third pixel areas; Forming first, second, and third color filter openings asymmetrically configured for each pixel area; First and second drain electrode contact holes are formed in the planarization film in the first and second color filter openings of the first and second pixel regions, and third drain electrode contact holes are formed in the planarization film in the third color filter opening of the third pixel region. forming a common wiring contact hole with the first, second and third pixel electrodes connected to the first, second, and third drain electrodes through the first, second, and third drain electrode contact holes; A method of manufacturing a liquid crystal display may be provided, including forming a third common electrode connected to a common wiring through the common wiring contact hole together with the first and second common electrodes spaced apart from the three pixel electrodes.

In the method of manufacturing a liquid crystal display according to the present invention, the area of the first and second color filter openings may be smaller than the area of the third color filter opening.

In the method of manufacturing a liquid crystal display according to the present invention, the first drain electrode of the first pixel region and the first drain electrode of the second pixel region may have an asymmetrical structure.

In the method of manufacturing a liquid crystal display according to the present invention, the second drain electrode of the second pixel region may have an asymmetric structure different from that of the first and third drain electrodes of the first and third pixel regions.

In the method of manufacturing a liquid crystal display according to the present invention, the first color filter opening is located closer to the first data line of the first pixel area than the second data line of the second pixel area, and the second color The filter opening may be located closer to the third data line of the third pixel area than the second data line of the second pixel area.

The first and second color filter openings overlap the upper and lower first and second drain electrodes and the common wiring, and the third color filter opening overlaps the upper and lower third drain electrodes and the common wiring region and the common wiring. It can overlap with a bay area.

In the method of manufacturing a liquid crystal display according to the present invention, only the first and second drain electrode contact holes are located in the first and second color filter openings, and the third drain electrode contact holes are located in the third color filter opening. and a common wiring contact hole.

In the method of manufacturing a liquid crystal display according to the present invention, the non-display portion of the first, second, and third pixel regions may include a thin film transistor, a gate line, and a data line portion.

In the method of manufacturing the liquid crystal display according to the present invention, the dummy color filter may have a stacked structure of a dummy red color filter and a dummy blue color filter.

In the method of manufacturing a liquid crystal display according to the present invention, a column spacer may be provided in a region corresponding to the thin film transistor of the non-display unit among the second substrates spaced apart from and bonded to the first substrate.

In the method of manufacturing a liquid crystal display according to the present invention, the column spacer may be provided on a second substrate corresponding to the second thin film transistor in the non-display portion of the second pixel region.

The liquid crystal display device and the method for manufacturing the same according to the present invention apply an asymmetric structure to the size of the color filter opening in each pixel region and the drain electrode to ensure sufficient distance margin between the column spacer and the color filter opening, thereby preventing the shift of the column spacer. Accordingly, there is no risk that the column spacer may fall into the color filter opening, so that there is no change in the internal volume of the cell, so touch and gravity defects can be improved.

1 is a plan view of a conventional COT structure liquid crystal display device.
FIG. 2 is a cross-sectional view of the liquid crystal display taken along line II-II of FIG. 1 .
3 is a plan view schematically illustrating a case in which a column spacer is shifted in a conventional COT structure liquid crystal display device.
FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. 3 , and schematically shows a cross-section inside the color filter opening.
5 is a plan view of a COT structure liquid crystal display device according to the present invention.
6 is a cross-sectional view of a COT structure liquid crystal display taken along line VI-VI of FIG. 5 .
7 is a cross-sectional view of a COT structure liquid crystal display taken along line VII-VII of FIG. 5 .
8A to 8H are cross-sectional views illustrating a manufacturing process of a COT structure liquid crystal display device according to the present invention.

Hereinafter, a liquid crystal display having a COT structure according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

5 is a plan view of a COT structure liquid crystal display device according to the present invention.

6 is a cross-sectional view of a COT structure liquid crystal display taken along line VI-VI of FIG. 5 .

7 is a cross-sectional view of a COT structure liquid crystal display taken along line VII-VII of FIG. 5 .

Referring to FIG. 2 , the gate wiring 102 is formed extending in one direction on the first substrate 100 , the common wiring 103 is formed in a direction parallel to the gate wiring 102 , and the gate wiring 102 is formed. ) and a plurality of data lines 112a, 112b, and 113c defining a plurality of first, second, and third pixel regions P1, P2, and P3 are formed. In this case, the first, second, and third pixel areas P1, P2, and P3 form one unit pixel area.

However, the unit pixel area is not limited to the first, second, and third pixel areas P1 , P2 , and P3 , and may include a plurality of pixel areas in some cases. In the present invention, it is assumed that the first, second, and third pixel areas P1, P2, and P3 are one unit pixel area.

In addition, first, second, and third thin film transistors T1 , T2 , and T3 are formed at intersections of the gate line 102 and the data lines 112a, 112b, and 112c. At this time, the thin film transistors T1, T2, and T3 have a gate electrode 102a, an active layer 110, source electrodes 115a, 115b, and 115c, and first, second, and third drain electrodes 116a, 116b, and 116c. may include.

In particular, among the first, second, and third drain electrodes 116a, 116b, and 116c, the second drain electrode 116b of the second thin film transistor T2 in the second pixel region P2 is disposed on left and right sides of the second thin film transistor T2. The first drain electrode 116a of the first thin film transistor T1 in the first pixel region P1 and the third drain electrode of the third thin film transistor T3 in the third pixel region P3 are provided, respectively. It has an asymmetric structure with respect to (116c).

That is, the first and third drain electrodes 116a and 116c of the first and third pixel regions P1 and P3 on the left and right sides of the second pixel region P2 have the same structure, but The drain electrode 116b of the second second pixel region P2 has a different structure. This is to increase the distance between the second color filter opening 124b of the second pixel region P2 and the first color filter opening 124a of the first pixel region P1 as far as possible.

In addition, the gate electrode 102a may be formed to protrude from the gate wiring 102 , and the source electrodes 115a , 115b , and 115c may be formed from the first, second, and third data lines 112a, 112b, and 112c. It may be formed in a protruding shape.

Red (R), green (G), and blue (B) color filters 120 , 121 , and 122 for realizing the color of the liquid crystal display in each of the first, second, and third pixel regions P1 , P2 , and P3 , respectively ) is formed.

A dummy red color filter 120a and a dummy blue color filter 122a are stacked on each non-display portion NP of the first, second, and third pixel areas P1 , P2 , and P3 . In this case, the non-display portion NP may include the thin film transistor T, the gate wiring 102 , the common wiring 103 , and the data wirings 112a , 112b , and 112c regions.

In addition, the first, second, and third colors are provided in the dummy red color filter 121a and the dummy blue color filter 122a in each non-display portion NP of the first, second, and third pixel areas P1, P2, and P3. Filter openings 124a, 124b, 124c are formed.

In this case, the first color filter opening 124a is formed in the dummy red color filter 120a and the dummy blue color filter 122a in the non-display portion NP of the first pixel area P1 . In particular, the first color filter opening 124a is a region overlapping the upper and lower drain electrodes 116a and the common wiring 103 , that is, portions of the dummy red color filter 120a and the dummy blue color filter 122a. is formed in

In addition, the second color filter opening 124b is formed in the dummy red color filter 120a and the dummy blue color filter 122a in the non-display portion NP of the second pixel area P2 . In particular, the second color filter opening 124b has an area overlapping the upper and lower drain electrodes 116b and the common wiring 103 , that is, portions of the dummy red color filter 120a and the dummy blue color filter 122a. is formed in

The third color filter opening 124c is formed in the dummy red color filter 120a and the dummy blue color filter 122a in the non-display portion NP of the third pixel area P3. In particular, the third color filter opening 124c has an overlapping area with the common wiring 103 and the drain electrode 116a as well as a partial overlapping area of the common wiring 103, that is, the dummy red color filter 120a and the dummy blue color filter 120a. It is formed on the color filter 122a.

In this case, the first color filter opening 124a is disposed closer to the first data line 112a of the first pixel area P1 than the second data line 112b of the second pixel area P1. , the second color filter opening 124b is disposed closer to the third data line 112c of the third pixel area P3 than the second data line 112b of the second pixel area P2 .

In particular, the first and second color filter openings 124a and 124b are formed to have the same size, and the third color filter opening 124c is formed to be larger than the first and second color filter openings 124a and 124b. have. In this case, only the first and second drain electrode contact holes 128a and 128b are formed in the first and second color filter openings 124a and 124b, but the third drain electrode contact hole 128c and the third drain electrode contact hole 128c are formed in the third color filter opening 124c. This is because the common wiring contact hole 128d is formed.

In addition, the red (R), green (G), and blue (B) color filters 120, 121, and 1222 including the first, second, and third color filter openings 124a, 124b, and 124c, as well as the dummy red color A planarization layer 126 for planarizing the surfaces of the color filters 120 , 121 , and 122 is formed on the filter 120a and the blue color filter 122a .

First, second, and third drain electrode contact holes 128a, 128b, and 128c are formed in the planarization layer 126 positioned in the first, second, and third color filter openings 124a, 124b, and 124c of the planarization layer 126 . and a common wiring contact hole 128d is formed. In this case, the first drain electrode contact hole 128a is located in the first color filter opening 124a, the second drain electrode contact hole 128b is located in the second color filter opening 124b, and the The third drain electrode 128c and the common wiring contact hole 128d are located in the third color filter opening 124c.

In addition, on the planarization layer 126 in the first color filter opening 124a positioned in the first pixel region P1 , the first drain electrode contact hole 128a is formed in the first pixel region P1 . A first pixel electrode 130a connected to a first drain electrode 116a constituting one thin film transistor T1 and a first common electrode 132a spaced apart from the first pixel electrode 130a are formed. .

A second thin film in the second pixel region P2 is formed on the planarization layer 126 in the second color filter opening 124b positioned in the second pixel region P2 through the second drain electrode contact hole 128b. A second pixel electrode 130b connected to the second drain electrode 116b constituting the transistor T2 and a second common electrode 132b spaced apart from the second pixel electrode 130b are formed.

In addition, on the planarization layer 126 in the third color filter opening 124c positioned in the third pixel region P3 , the third drain electrode contact hole 128c passes through the third pixel region P3 . 3 A third pixel electrode 130c connected to the third drain electrode 116c constituting the thin film transistor T3 is formed, is spaced apart from the third pixel electrode 130c, and the common wiring contact hole 128d is formed. A third common electrode 132c connected to the common wiring 103 is formed. In this case, the first and second common electrodes 132a and 132b are formed in the first and second pixel regions P1 and P2, and they are integrally formed with the third common electrode 132c. In addition, the first, second, and third common electrodes 132a, 132b, and 132c are disposed to be spaced apart from the first pixel electrodes 130a, 130b, and 130c in the first and second pixel regions P1, P2, and P3. has been

Although not shown in the drawings, the first, second, and third pixel electrodes 130a, 130b, 130c and the first, second, and third common electrodes 132a, 132b, and 132c, as well as the lower alignment layer (not shown) on the planarization layer 126 are city) is formed.

Meanwhile, although not shown in the drawings, a black matrix (not shown) is formed on the second substrate 140 spaced apart from the first substrate 100 to prevent light transmission and reflection. In this case, the black matrix (not shown) may be formed in a region corresponding to the non-display portion NP of the first substrate 100 . That is, the non-display unit NP may include thin film transistors T1 , T2 , and T3 , a gate line 102 , a common line 103 , and data lines 112a , 112b , and 113c .

A column spacer (CS) 144 is formed on a region corresponding to the thin film transistor T2 of the first substrate 100 of the second substrate 140 . In this case, the column spacer 144 is not limited to being formed only in the region corresponding to the thin film transistor T2 , and in some cases, a region corresponding to other portions of the non-display portion NP of the first substrate 100 . may be formed in

In particular, the column spacer 144 may perform a function of maintaining a gap between the first substrate 100 and the second substrate 140 bonded thereto. Also, the column spacer 144 may be a black column spacer (BCS) that performs a black matrix function. In this case, a black matrix (not shown) may be omitted on the second substrate 140 .

At this time, since the material of the black column spacer is black resin, it is possible to shield the active layer 110 of the thin film transistor T2 from light, as well as the first and second substrates 100 and 140 . It can simultaneously perform the function of maintaining the gap of Such a black column spacer may have photosensitivity, and in that case, it may be patterned by coating and exposure.

As shown in FIG. 7 , the column spacer 144 is formed on the second substrate 140 corresponding to the thin film transistor T2 , in which case the column spacer 144 and the second color filter opening 124b are formed. A certain distance (d2) margin is secured between each other. This is because the areas of the first and second color filter openings 124a and 124b are smaller than those of the existing openings, and the first and second color filter openings 124a and 124b have asymmetric structures.

Although not shown in the drawings, an upper alignment layer (not shown) is formed on the second substrate 140 .

In addition, the liquid crystal layer 150 is formed between the second substrate 140 having the above configuration and the first substrate 100 bonded thereto to face it, thereby configuring the liquid crystal display device according to the present invention.

Accordingly, the distance d2 between the column spacer 144 formed in the region corresponding to the thin film transistor T2 of the second substrate 140 and the first and second column openings 124a and 124b is the same as the existing distance d1 . Since it is further away, the distance margin between the column spacer 144 and the color filter opening 124b is sufficiently secured, so that the risk of falling into the color filter opening 124b due to the shift of the column spacer 144 is reduced. By disappearing, the volume fluctuation inside the cell is eliminated, and the touch and gravity defects are improved.

As described above, in the liquid crystal display device according to the present invention, the distance margin between the column spacer and the color filter opening is sufficiently secured by applying an asymmetric structure to the size of the color filter opening in each pixel region and the drain electrode, so that the column spacer shifts. Accordingly, there is no risk that the column spacer may fall into the color filter opening and there is no change in the volume inside the cell, so touch and gravity defects can be improved.

Meanwhile, a method for manufacturing a liquid crystal display according to the present invention having such a configuration will be described with reference to FIGS. 8A to 8H.

8A to 8H are cross-sectional views illustrating a manufacturing process of a COT structure liquid crystal display device according to the present invention.

Referring to FIG. 8A , a gate metal layer (not shown) is formed on the first substrate 100, a photoresist is formed on the gate metal layer, and then exposed using an exposure mask (not shown) comprising a transmissive part and a blocking part. and a developing process to form a photoresist pattern (not shown).

Then, the gate metal layer is etched using the photoresist pattern as a mask to etch the gate wiring (not shown, see 102 in FIG. 5 ), the common wiring 103 , and the gate electrode 102a branched from the gate wiring 102 ). to form

In this case, the gate wiring 102 is formed to extend in one direction on the first substrate 100 , and the common wiring 103 is formed in a direction parallel to the gate wiring 102 . The plurality of data lines 112a, 112b, and 112c formed in a subsequent process cross the gate line 102 to define a plurality of first, second, and third pixel regions P1, P2, and P3. The first, second, and third pixel areas P1, P2, and P3 form one unit pixel area.

However, the unit pixel area is not limited to the first, second, and third pixel areas P1 , P2 , and P3 , and may include a plurality of pixel areas in some cases. In the present invention, it is assumed that the first, second, and third pixel areas P1, P2, and P3 are one unit pixel area.

In this case, the substrate 100 may be formed of glass, plastic, polyimide (PI), etc., and the gate metal layer is molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), copper ( Cu), chromium (Cr), aluminum (Al), an alloy formed from a combination thereof, or a transparent conductive material, ITO, IZO, and ITZO may be formed by laminating at least one. In the drawing, the gate electrode 201, the common wiring 202, and the gate line 203 are formed of a single metal layer, but since this is not fixed, it may be formed by stacking two or more metal layers.

Next, a gate insulating layer 106 is formed on the entire surface of the first substrate 100 on which the gate electrode 102a, the gate wiring 102 and the common wiring 103 are formed.

Then, a pure amorphous silicon layer (not shown) and an amorphous silicon layer (not shown) doped with impurities are deposited on the gate insulating layer 106 , and a photoresist is formed on the impurity doped amorphous silicon layer (not shown). A resist is formed, and a photoresist pattern (not shown) is formed by performing exposure and development processes using an exposure mask composed of a transmissive part and a blocking part.

Next, although not shown in the drawings, the pure amorphous silicon layer (not shown) and the impurity-doped amorphous silicon layer (not shown) are sequentially etched using the photoresist pattern as a mask to sequentially etch the semiconductor layer (see 108a in FIG. 5 ). ) and an ohmic contact layer (refer to 109a in FIG. 5 ) and an active layer (refer to 110 in FIG. 5 ) is formed.

Then, source and drain metal layers (not shown) are formed on the entire surface of the first substrate 100 on which the active layer 110 is formed.

Next, as shown in FIG. 8B , photoresist is formed on the source and drain metal layers, and exposure and development processes are performed using an exposure mask comprising a transmissive part and a blocking part to etch the source and drain metal layers for data wiring. The 112a, 112b, and 112c, the source electrodes 115a, 115b, and 115c branched from the data line, and the drain electrodes 116a, 116b, and 116c separated from the source electrode by a predetermined distance are formed.

In this case, first, second, and third thin film transistors T1 , T2 , and T3 are formed at intersections of the gate line 102 and the data lines 112a , 112b , and 112c . The thin film transistors T1, T2, and T3 include a gate electrode 102a, an active layer 110, source electrodes 115a, 115b, and 115c, and first, second, and third drain electrodes 116a, 116b, and 116c. can do.

In particular, among the first, second, and third drain electrodes 116a, 116b, and 116c, the second drain electrode 116b of the second thin film transistor T2 in the second pixel region P2 is disposed on left and right sides of the second thin film transistor T2. The first drain electrode 116a of the first thin film transistor T1 in the first pixel region P1 and the third drain electrode of the third thin film transistor T3 in the third pixel region P3 are provided, respectively. It has an asymmetric structure with respect to (116c).

That is, the first and third drain electrodes 116a and 116c of the first and third pixel regions P1 and P3 on the left and right sides of the second pixel region P2 have the same structure, but The drain electrode 116b of the second second pixel region P2 has a different structure. This is to increase the distance between the second color filter opening 124b of the second pixel region P2 and the first color filter opening 124a of the first pixel region P1 as far as possible.

In addition, the gate electrode 102a may be formed to protrude from the gate wiring 102 , and the source electrodes 115a , 115b , and 115c may be formed from the first, second, and third data lines 112a, 112b, and 112c. It may be formed in a protruding shape.

On the other hand, the source and drain metal layers are molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), chromium (Cr), aluminum (Al), an alloy formed from a combination thereof Either one can be used. In addition, although it is formed as a single metal layer in the drawings, it may be formed by stacking at least two or more metal layers in some cases.

The source electrodes 115a, 115b, and 115c overlap the gate electrode 102a, and the drain electrodes 116a, 116b, and 116c overlap the common wiring 103 and the gate electrode 102a.

In addition, when the source and drain metal layers are etched, a portion of the ohmic contact layer 109a, that is, a portion corresponding to the channel region is also etched and separated.

Then, as shown in FIG. 8C , a passivation layer 118 is formed on the entire surface of the first substrate 100 on which the source electrodes 115a , 115b , and 115c and the drain electrodes 116a , 116b and 116c are formed. In this case, the passivation layer 118 is formed of an inorganic insulating material or an organic insulating material. As the inorganic insulating material, one of the group of inorganic insulating materials including silicon nitride (SiN ₂ ) and silicon oxide (SiO ₂ ) may be used, and as the organic insulating material, a photo-acryl material or other photosensitive material It may be an organic insulating material.

Subsequently, although not shown in the drawings, a process of applying a dye for forming a color filter on the passivation layer 118 and then selectively patterning it is performed for each red (R), green (G) and blue (B) color filter. Red (R), green (G), and blue (B) color filters (see 120 , 121 , and 122 in FIG. 5 ) are formed by repeating the process. In this case, the red (R), green (G), and blue (B) color filters (see 120 , 121 , and 122 in FIG. 5 ) include the gate wiring 102 and the data wiring 112a on the front surface of the first substrate 100 . , 112b, 112c intersect each other, ie, the first, second, and third pixel areas P1, P2, and P3 are formed for each cell.

Then, a dummy red color filter 120a and a dummy blue color filter 122a are formed on the non-display portion NP in the first, second, and third pixel areas P1 , P2 , and P3 . This is because the dummy red color filter 120a is transmissive and can transmit light, but since the dummy green color filter 122a has a light blocking characteristic, it is preferable to form a stacked structure to block light. In this case, a stacked structure of the dummy red color filter 120a and the dummy green color filter (not shown) is formed in the non-display part NP instead of the stacked structure of the dummy red color filter 120a and the dummy blue color filter 122a. You may.

In addition, the non-display portion NP may include the thin film transistor T, the gate wiring 102 , the common wiring 103 , and the data wirings 112a , 112b , and 112c regions.

Then, the first, second, and third color filter openings 124a, 124b, and the dummy red color filter 120a and the dummy blue color filter 122a in the non-display part NP are selectively patterned through exposure and development processes. 124c).

In this case, the first color filter opening 124a is disposed closer to the first data line 112a of the first pixel area P1 than the second data line 112b of the second pixel area P1. , the second color filter opening 124b is disposed closer to the third data line 112c of the third pixel area P3 than the second data line 112b of the second pixel area P2 .

In addition, the first color filter opening 124a is formed in the dummy red color filter 120a and the dummy blue color filter 122a in the non-display portion NP of the first pixel area P1 . In particular, the first color filter opening 124a is a region overlapping the upper and lower drain electrodes 116a and the common wiring 103 , that is, portions of the dummy red color filter 120a and the dummy blue color filter 122a. is formed in

The second color filter opening 124b is formed in the dummy red color filter 120a and the dummy blue color filter 122a in the non-display portion NP of the second pixel area P2 . In particular, the second color filter opening 124b has an area overlapping the upper and lower drain electrodes 116b and the common wiring 103 , that is, portions of the dummy red color filter 120a and the dummy blue color filter 122a. is formed in

The third color filter opening 124c is formed in the dummy red color filter 120a and the dummy blue color filter 122a in the non-display portion NP of the third pixel area P3 . In particular, the third color filter opening 124c has an overlapping area with the common wiring 103 and the drain electrode 116a as well as a partial overlapping area of the common wiring 103, that is, the dummy red color filter 120a and the dummy blue color filter 120a. It is formed on the color filter 122a.

Here, the first and second color filter openings 124a and 124b have the same size, and the third color filter opening 124c has the same area as the first and second color filter openings 124a and 124b. ) is larger than In this case, only the first and second drain electrode contact holes 128a and 128b are formed in the first and second color filter openings 124a and 124b, but the third drain electrode contact hole 128c and the third drain electrode contact hole 128c are formed in the third color filter opening 124c. This is because the common wiring contact hole 128d is formed.

Next, referring to FIG. 8E , red (R), green (G), and blue (B) color filters 120 , 121 and 122 including the first, second, and third color filter openings 124a , 124b and 124c . Of course, a planarization layer 126 for planarizing the surfaces of the color filters 120 , 121 , and 122 is formed on the dummy red color filter 120a and the blue color filter 122a. At this time, the planarization film

(126) may be formed of an organic insulating material such as benzocyclobutene (BCB) and acrylic resin (acryl resin).

Then, referring to FIG. 8F , the planarization layer 126 and the protective layer 118 and the gate insulating layer 106 thereunder are selectively patterned through exposure and development processes to selectively pattern the first planarization layer 126 . , 2, 3 A common wiring contact hole 128d is simultaneously formed together with the first, second, and third drain electrode contact holes 128a, 128b, and 128c in portions positioned within the color filter openings 124a, 124b, and 124c.

In this case, the first drain electrode contact hole 128a is located in the first color filter opening 124a, the second drain electrode contact hole 128b is located in the second color filter opening 124b, and the The third drain electrode 128c and the common wiring contact hole 128d are located in the third color filter opening 124c.

Next, referring to FIG. 8G , after depositing a transparent conductive material on the entire surface of the planarization layer 126 including the first, second, and third drain electrode contact holes 128a, 128b, and 128c and the common wiring contact hole 128d. , the first, second, and third pixel electrodes 130a on the planarization film 126 in the first color filter opening 124a positioned in the first pixel region P1 by selectively patterning through exposure and development processes; 130b and 130c) and first, second, and third common electrodes 132a, 132b, and 132c are formed. In this case, as the transparent conductive material, one selected from a group of transparent conductive metals including indium-tin-oxide (ITO) and indium-zinc-oxide (IZO) is used.

In addition, the first pixel electrode 130a is connected to the first drain electrode 116a constituting the first thin film transistor T1 of the first pixel region P1 through the first drain electrode contact hole 128a. connected

The second pixel electrode 130b is formed on the planarization layer 126 in the second color filter opening 124b positioned in the second pixel region P2 through the second drain electrode contact hole 128b. It is connected to the second drain electrode 116b constituting the first thin film transistor T2 of the second pixel region P2 .

Meanwhile, the third pixel electrode 130c is formed on the planarization layer 126 in the third color filter opening 124c positioned in the third pixel region P3 through the third drain electrode contact hole 128c. It is connected to the third drain electrode 116c constituting the third thin film transistor T3 of the third pixel region P3 . In addition, the third common electrode 132c is connected to the common wiring 103 through the common wiring contact hole 128d. In this case, the third common electrode 132c is integrally formed with the first and second common electrodes 132a and 132b in the first and second pixel regions P1 and P2. In addition, the first, second, and third common electrodes 132a, 132b, and 132c are disposed to be spaced apart from the first pixel electrodes 130a, 130b, and 130c in the first and second pixel regions P1, P2, and P3. has been

Thereafter, although not shown in the drawings, the first, second, and third pixel electrodes 130a, 130b, 130c and the first, second, and third common electrodes 132a, 132b, and 132c, as well as the entire surface of the planarization film 126, are A lower alignment layer (not shown) may be formed.

Next, although not shown in the drawings, a black matrix (not shown) may be formed on the second substrate 140 spaced apart from the first substrate 100 to prevent light transmission and reflection. In this case, the black matrix (not shown) may be formed in a region corresponding to the non-display portion NP of the first substrate 100 . That is, the non-display unit NP may include thin film transistors T1 , T2 , and T3 , a gate line 102 , a common line 103 , and data lines 112a , 112b , and 113c .

Then, referring to FIG. 8H , a column spacer (CS) 144 is formed on a region corresponding to the thin film transistor T2 of the first substrate 100 of the second substrate 140 . In this case, the column spacer 144 is not limited to being formed only in the region corresponding to the thin film transistor T2 , and in some cases, a region corresponding to other portions of the non-display portion NP of the first substrate 100 . may be formed in

Accordingly, the distance d2 between the column spacer 144 formed in the region corresponding to the thin film transistor T2 of the second substrate 140 and the first and second column openings 124a and 124b is the same as the existing distance d1 . Since the distance is greater, the distance margin between the column spacer 144 and the color filter opening 124b is secured, so that the risk of falling into the color filter opening 124b due to the shift of the column spacer 144 is eliminated. As a result, the volume fluctuation inside the cell is eliminated, and the touch and gravity defects are improved.

In particular, the column spacer 144 may perform a function of maintaining a gap between the first substrate 100 and the second substrate 140 bonded thereto. Also, the column spacer 144 may be a black column spacer (BCS) that performs a black matrix function. In this case, a black matrix (not shown) may be omitted on the second substrate 140 .

At this time, since the material of the black column spacer is black resin, it is possible to shield the active layer 110 of the thin film transistor T2 from light, as well as the first and second substrates 100 and 140 . It can simultaneously perform the function of maintaining the gap of Such a black column spacer may have photosensitivity, and in that case, it may be patterned by coating and exposure.

In addition, the column spacer 144 is formed on the second substrate 140 corresponding to the thin film transistor T2, and at this time, a predetermined distance d2 is provided between the column spacer 144 and the second color filter opening 124b. margin is secured. This is because the areas of the first and second color filter openings 124a and 124b are smaller than those of the existing openings, and the structures of the first and second color filter openings 124a and 124b are asymmetric to each other.

Next, although not shown in the drawings, an upper alignment layer (not shown) may be formed on the second substrate 140 .

Then, the liquid crystal display device manufacturing process according to the present invention is completed by forming the liquid crystal layer 150 between the second substrate 140 manufactured in this order and the first substrate 100 bonded thereto to face it. .

As described above, in the liquid crystal display device and the method for manufacturing the same according to the present invention, the distance margin between the column spacer and the color filter opening is sufficiently secured by applying an asymmetric structure to the size of the color filter opening in each pixel region and the drain electrode, thereby reducing the thickness of the column spacer. The risk that the column spacer may fall into the color filter opening according to the shift is eliminated, so that there is no change in the internal volume of the cell, and thus, poor touch and gravity can be improved.

Although many matters are specifically described in the above description, this should be construed as an illustration of a preferred embodiment rather than limiting the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and equivalents to the claims.

102: gate wiring 103: common wiring
112a, 112b, 112c: data wiring 115a, 115b, 115c: source electrode
116a, 116b, 116c: drain electrode 120a: dummy red color filter
122a: dummy blue color filter 124a, 124b, 124c: color filter opening
126: planarization film 128a, 128b, 128c: drain contact hole
128d: common electrode contact holes 130a, 130b, 130c: first to third pixel electrodes
132a, 132b, 132c: first to common electrodes

Claims (22)

a gate line and first, second, and third data lines arranged to cross each other on a first substrate and defining first, second, and third pixel regions constituting one pixel and a non-display unit;
first, second, and third thin film transistors provided at one side of each of the first, second, and third pixel areas, and first, second, and third color filters provided in the first, second, and third pixel areas;
a dummy color filter provided for each non-display portion of the first, second, and third pixel areas;
first, second, and third color filter openings provided in each of the non-display portions of the first, second, and third pixel areas and configured asymmetrically for each of the first, second, and third pixel areas;
It is provided on the first, second, and third color filters and the dummy color filter, and has first and second drain electrode contact holes in openings of the first and second color filters in the first and second pixel areas, a planarization layer having a third drain electrode contact hole and a common wiring contact hole in the 3 color filter openings;
first, second, and third pixel electrodes connected to the first, second, and third drain electrodes through the first, second, and third drain electrode contact holes; and
and a common electrode disposed to be spaced apart from the first, second, and third pixel electrodes and connected to a common wiring through the common wiring contact hole. The liquid crystal display of claim 1 , wherein an area of the first and second color filter openings is smaller than an area of the third color filter opening. The liquid crystal display device of claim 1 , wherein the first drain electrode of the first pixel region and the first drain electrode of the second pixel region have an asymmetric structure. The liquid crystal display of claim 1 , wherein the second drain electrode of the second pixel region has an asymmetric structure different from that of the first and third drain electrodes of the first and third pixel regions. The method of claim 1 , wherein the first color filter opening is located closer to the first data line of the first pixel area than the second data line of the second pixel area, and the second color filter opening is located in the second pixel area. The liquid crystal display device is located closer to the third data line in the third pixel area than the second data line. The method of claim 1 , wherein the first and second color filter openings overlap the first and second drain electrodes and the common wiring arranged upwards and downwards, and the third color filter openings include upwardly and downwardly arranged third drain electrodes and A liquid crystal display that overlaps with a common wiring area and an area with only common wiring. The method of claim 1, wherein first and second drain electrode contact holes are provided in the openings of the first and second color filters, and a third drain electrode contact hole and a common wiring contact hole are provided in the third color filter openings. liquid crystal display. The liquid crystal display device of claim 1 , wherein the non-display portion of the first, second, and third pixel areas includes a thin film transistor, a gate line, and a data line portion. The liquid crystal display device of claim 1 , wherein the dummy color filter has a stacked structure of a dummy red color filter and a dummy blue color filter. The liquid crystal display of claim 1 , wherein a column spacer is provided in a region corresponding to the thin film transistor of the non-display portion of the second substrate spaced apart from the first substrate and bonded to the first substrate. The liquid crystal display device of claim 10 , wherein the column spacers are provided on a second substrate corresponding to a second thin film transistor in a non-display portion of the second pixel area. forming gate wirings and first, second, and third data wirings arranged to cross each other on a first substrate to define first, second, and third pixel regions constituting one pixel and a non-display unit;
forming first, second, and third thin film transistors on one side of each of the first, second, and third pixel regions;
forming first, second, and third color filters in the first, second, and third pixel areas and forming a dummy color filter in each non-display portion of the first, second, and third pixel areas;
forming first, second, and third color filter openings asymmetrically configured for each of the first, second, and third pixel regions in the non-display portion of the first, second, and third pixel regions;
forming a planarization layer on the entire surface of the first substrate including the first, second, and third color filters and the dummy color filter;
First and second drain electrode contact holes are formed in the planarization film in the first and second color filter openings of the first and second pixel regions, and a third drain electrode is formed in the planarization film in the third color filter opening of the third pixel region. forming a contact hole and a common wiring contact hole;
first, second, and third pixel electrodes connected to the first, second, and third drain electrodes through the first, second, and third drain electrode contact holes; and the common wiring contact spaced apart from the first, second, and third pixel electrodes A method of manufacturing a liquid crystal display device comprising the step of forming a common electrode connected to a common wiring through a hole. The method of claim 12 , wherein an area of the first and second color filter openings is smaller than an area of the third color filter opening. The method of claim 12 , wherein the first drain electrode of the first pixel region and the first drain electrode of the second pixel region have an asymmetric structure. The method of claim 12 , wherein the second drain electrode of the second pixel region has an asymmetric structure different from that of the first and third drain electrodes of the first and third pixel regions. 13. The method of claim 12, wherein the first color filter opening is located closer to the first data line of the first pixel area than the second data line of the second pixel area, and the second color filter opening is located closer to the first data line of the second pixel area. A method of manufacturing a liquid crystal display in which the third data line is located closer to the third data line in the third pixel area than the second data line. 13. The method of claim 12, wherein the first and second color filter openings overlap the upper and lower first and second drain electrodes and the common wiring, and the third color filter opening includes upper and lower third drain electrodes and A method of manufacturing a liquid crystal display that overlaps with a common wiring area and an area with only common wiring. 13. The method of claim 12, wherein first and second drain electrode contact holes are provided in the first and second color filter openings, and a third drain electrode contact hole and a common wiring contact hole are provided in the third color filter openings. A method for manufacturing a liquid crystal display device. The method of claim 12 , wherein the non-display portion of the first, second, and third pixel areas includes a thin film transistor, a gate line, and a data line portion. The method of claim 12 , wherein the dummy color filter has a stacked structure of a dummy red color filter and a dummy blue color filter. The method of claim 12 , wherein a column spacer is provided in a region corresponding to the thin film transistor of the non-display portion of the second substrate spaced apart from the first substrate and bonded to the first substrate. The method of claim 21 , wherein the column spacers are provided on a second substrate corresponding to a second thin film transistor in a non-display portion of the second pixel area.

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