KR100729768B1 - Thin film transistor plate and fabricating method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate and a method of manufacturing the same. In order to prevent wiring defects of a molybdenum series, a photoresist pattern for forming data wirings is left without being removed and a subsequent process is performed. In the thin film transistor substrate according to the present invention, a gate wiring including a gate line and a gate electrode is formed on the substrate, and the gate insulating film covers the gate wiring. A semiconductor pattern is formed on the gate insulating film, and data wirings including a data line, a source electrode, and a drain electrode are formed on the gate insulating film. A photosensitive film pattern is formed on the data wiring, and a protective film covers the photosensitive film pattern and the semiconductor pattern. A first contact hole for exposing the drain electrode is formed, and the pixel electrode is in contact with the drain electrode through the first contact hole.

Molybdenum Series, Data Wiring, Wire Open, Low Resistance

Description

Thin film transistor substrate and its manufacturing method {THIN FILM TRANSISTOR PLATE AND FABRICATING METHOD THEREOF}

1 is a layout view of a thin film transistor substrate according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor substrate taken along the cutting line II-II ′ shown in FIG. 1.

3A through 6B are diagrams illustrating a manufacturing process of a thin film transistor substrate according to a first exemplary embodiment of the present invention.

7 is a layout view of a thin film transistor substrate according to a second exemplary embodiment of the present invention.

8 and 9 are cross-sectional views of the thin film transistor substrate taken along the cutting lines VIII 'and VIII' shown in FIG.

10A through 17B are manufacturing process diagrams of a thin film transistor substrate according to a second exemplary embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate and a manufacturing method thereof, and more particularly, to a manufacturing method of a thin film transistor substrate used in a liquid crystal display device.                         

In the liquid crystal display, a liquid crystal material is injected between a lower substrate on which a thin film transistor, a pixel electrode, and the like are formed, and an upper substrate on which an opposite electrode and a color filter are formed. It is an apparatus that forms an electric field by applying an electric potential to change the arrangement of liquid crystal molecules, and thereby controls the light transmittance to express an image.

In a general manufacturing process of a thin film transistor substrate, a gate wiring is formed on the substrate, and an active layer is formed of a three-layer film of a gate insulating film, a semiconductor layer, and an ohmic contact layer on the gate wiring. Subsequently, a data line is formed thereon, a protective film is formed, and then a contact hole for exposing a drain electrode that is part of the data wire is formed in the protective film, and then a pixel electrode contacting the drain electrode is formed through the contact hole.

The data line employed in the thin film transistor substrate is formed of a molybdenum series such as molybdenum (Mo) or molybdenum-tungsten (Mo-W) which has excellent contact characteristics with the semiconductor layer and low resistance.

However, molybdenum-based data wirings have a problem of being etched together while etching insulating films such as silicon nitride films with etching gases such as SF ₆ and CF ₄ .

An object of the present invention is to provide a thin film transistor substrate capable of preventing disconnection of data wirings and a method of manufacturing the same.

In order to solve this problem, in the present invention, the photoresist pattern for forming data wirings is left without being removed, and subsequent steps are performed.

In detail, in the thin film transistor substrate according to the present invention, a gate wiring including a gate line and a gate electrode is formed on the substrate, and the gate insulating film covers the gate wiring. A semiconductor pattern is formed on the gate insulating film, and data wirings including a data line, a source electrode, and a drain electrode are formed on the gate insulating film. A photosensitive film pattern is formed on the data wiring, and a protective film covers the photosensitive film pattern and the semiconductor pattern. A first contact hole for exposing the drain electrode is formed, and the pixel electrode is in contact with the drain electrode through the first contact hole.

In this case, it is advantageous that the data line is formed of a low resistance metal material, and a molybdenum series may be used as the low resistance metal material. The first contact hole may be formed in the photoresist pattern on the passivation layer and the drain electrode.

Here, the gate wiring further includes a gate pad connected to the gate line, and the data wiring further includes a data pad connected to the data line, wherein the data wiring further includes a first contact hole exposing the data pad and a second contact hole exposing the gate pad. It may further include. In this case, the second contact hole may be formed in the photoresist pattern on the passivation layer and the data pad, and the third contact hole may be formed in the passivation layer and the gate insulating layer.

In addition, in order to manufacture the thin film transistor substrate according to the present invention, a gate wiring including a gate line and a gate electrode is formed on the substrate, and a gate insulating film covering the gate wiring is formed. Subsequently, a semiconductor pattern is formed on the gate insulating film, a metal layer for data wiring is deposited on the gate insulating film and the semiconductor pattern, and then a photosensitive film pattern for forming data wiring is formed on the metal layer for data wiring. Subsequently, the metal layer for data wiring is etched using the photosensitive film pattern as a mask to form a data wiring including a data line, a source electrode, and a drain electrode, and a protective film covering the photosensitive film pattern and the semiconductor pattern is formed. In this case, the metal layer for data wiring is preferably formed of a molybdenum series such as molybdenum (Mo) or molybdenum-tungsten (Mo-W).

Subsequently, a first contact hole exposing the drain electrode is formed in the photosensitive film pattern portion on the passivation film and the drain electrode, and the pixel electrode contacting the drain electrode through the first contact hole is formed in the passivation film. At this time, the metal layer for data wiring is preferably formed of molybdenum series.

Here, the gate wiring further includes a gate pad connected to the gate line, the data wiring further includes a data pad connected to the data line, and at the time of forming the first contact hole, a second pad exposing the data pad and the gate pad; The third contact hole can be formed. At this time, the second contact hole may be formed in the photoresist pattern on the protective film and the data pad, and the third contact hole may be formed in the protective film and the gate insulating film.

In addition, in order to manufacture the thin film transistor substrate according to the present invention, a gate wiring including a gate line and a gate electrode is formed on the substrate, and a gate insulating film covering the gate wiring is formed. Subsequently, the semiconductor layer and the data wiring metal layer are successively deposited on the gate insulating film, and then a photosensitive film pattern is formed on the data wiring metal layer. Subsequently, the metal layer for data wiring and the semiconductor layer are etched using the photoresist pattern as a mask, and a data line is formed on the semiconductor pattern and the semiconductor pattern and includes a data line including a data line, a source electrode, and a drain electrode, and then a protective film covering the photoresist pattern and the semiconductor pattern. To form. Next, a first contact hole exposing the drain electrode is formed, and a pixel electrode contacting the drain electrode through the first contact hole is formed on the protective film.

Here, the photoresist pattern may be formed of a first portion having a first thickness on the upper portion of the data line and a second portion having a second thickness thinner than the first thickness on the upper portion between the source electrode and the drain electrode. Can be formed using one mask. The mask may be patterned to include a first region, a second region having a lower transmittance than the first region, and a third region having a higher transmittance than the first region. The metal layer for data wiring may be formed of molybdenum (Mo) or molybdenum-tungsten (Mo-W) molybdenum series, and the first contact hole may be formed in the photoresist pattern on the passivation layer and the drain electrode.

In addition, the gate wiring further includes a gate pad connected to the gate line, the data wiring further includes a data pad connected to the data line, and at the time of forming the first contact hole, a second pad exposing the data pad and the gate pad; A third contact hole may be formed, the second contact hole may be formed in the photoresist pattern on the passivation layer and the data pad, and the third contact hole may be formed in the passivation layer and the gate insulating layer.

Next, the present invention will be described with reference to the drawings.

1 is a layout view of a thin film transistor substrate according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor substrate taken along the cutting line II-II ′ of FIG. 1.

Gate wirings 22, 24, and 26 formed of a low resistance metal material, for example, aluminum, molybdenum, chromium, and titanium, are formed on the insulating substrate 10. The gate wires 22, 24, and 26 are connected to the gate line 22 extending in the horizontal direction, the gate pad 24 connected to the end of the gate line 22 to receive a gate signal from the outside, and to transfer the gate signal to the gate line. And a gate electrode 26 of the thin film transistor connected to the gate line 22.

The gate wirings 22, 24, and 26 may be formed in a double layer or more structure in addition to the single layer structure. When the gate wirings 22, 24, and 26 are formed in a double layer structure, at least one of the two layers may be formed of a metal material having low resistance.

On the insulating substrate 10, a gate insulating film 30 made of an insulating material, for example, silicon nitride, covers the gate wirings 22, 24, and 26.

A semiconductor pattern 42 made of a semiconductor material, for example, amorphous silicon, is formed on the gate insulating layer 30 so as to overlap the gate electrode 26, and a semiconductor material doped with impurities is formed on the semiconductor pattern 42, for example, Ohmic contact layers 55 and 56 made of amorphous silicon doped with a high concentration of n-type impurities are formed.

On the ohmic contact layers 55 and 56 and the gate insulating layer 30, a metal material having excellent contact properties with the semiconductor layer and low resistance, for example, a data line 62 made of molybdenum series such as molybdenum or molybdenum alloy, 64, 65, 66 are formed. The data lines 62, 64, 65, and 66 are connected to the ends of the data line 62 and the data line 62 formed in the vertical direction, and receive data from the outside and transfer the data pads to the gate line ( 64, a source electrode 65 protruding from the data line 62 and contacting the one ohmic contact layer 55 to form a part of the thin film transistor, and the other ohmic contact layer corresponding to the source electrode 65. And a drain electrode 66 in contact with 56 to form part of the thin film transistor.

On the data lines 62, 64, 65, 66, a photosensitive film pattern PR is formed along the data lines 62, 64, 65, 66. Although the photoresist pattern PR will be described later in the manufacturing process, the photoresist pattern PR is left without being removed as an etching mask in the process of etching the data lines 62, 64, 65, and 66.

The exposed front surface of the substrate including the photoresist pattern PR and the gate insulating layer 30 on the data lines 62, 64, 65, and 66 may be formed of an organic insulating material such as acrylic resin or BCB ( BenzoCycloButane) or an inorganic insulating material, for example, silicon nitride, a protective film 70 is formed. In this case, the passivation layer 70 may be formed of an insulating film of a multilayer including an organic insulating material layer and an inorganic insulating material layer.

The first contact hole 72 exposing the drain electrode 66 is formed in the photoresist pattern PR on the passivation layer 70 and the drain electrode 66, and the second contact exposing the data pad 64. Holes 74 are formed in the protective film 70 and the photoresist pattern PR on the data pad 64. A third contact hole 76 exposing the gate pad 24 is formed in the protective film 70 and the gate insulating film 30.                     

The pixel electrode 82, the auxiliary data pad 84, and the auxiliary gate pad 86 made of IZO or ITO are formed on the passivation layer 70. The pixel electrode 82 is electrically connected to the drain electrode 66 through the first contact hole 72 to receive an image signal from the data line 62. In addition, the auxiliary gate pad 84 and the auxiliary data pad 86 are electrically connected to the data pad 24 and the gate pad 64 through the second and third contact holes 74 and 76.

Next, a method of manufacturing the thin film transistor substrate according to the first embodiment of the present invention will be described with reference to FIGS. 1 and 2 and FIGS. 3A to 7B.

First, as illustrated in FIGS. 3A and 3B, a metal material layer having a low resistance characteristic, for example, an aluminum based layer is deposited on the substrate 10 to a thickness of 2500 to 4000 GPa, and patterned by a photolithography process. Gate wirings 22, 24, and 26 including the gate line 22, the gate pad 24, and the gate electrode 26 are formed.

Next, as shown in FIGS. 4A and 4B, the gate insulating film 30 made of an insulating material, for example, silicon nitride, covering the gate wirings 22, 24, and 26 on the substrate 10 may be 1500 to 3500 mm thick. To be deposited.

Subsequently, the semiconductor layer and the semiconductor layer doped with impurities are sequentially stacked on the gate insulating layer 30 to a thickness of 800 to 1500 kV and 500 to 800 kV, respectively, and then the semiconductor layer and the semiconductor layer doped with impurities are formed by a photolithography process. Patterning forms the ohmic contact layer pattern 52 and the semiconductor pattern 42.                     

Next, as illustrated in FIGS. 5A and 5B, after depositing a metal material layer having a low resistance characteristic, for example, a molybdenum-based layer having a thickness of 1500 to 3500 kPa over the entire surface of the substrate, The data lines 62, 64, 65, and 66 including the data line 62, the data pad 64, the source electrode 65, and the drain electrode 66 are formed by patterning by a photolithography process.

As described above, the data wirings 62, 64, 65, and 66 made of molybdenum series having low resistance characteristics can be applied to liquid crystal displays of large-area screens requiring low resistance wiring. Since the wiring can be formed even with a single film, it is not necessary to form a multilayer wiring, which is advantageous in simplifying the process.

Subsequently, the island-like ohmic contact layer 52 integrally formed using the source electrode 65 and the drain electrode 66 as a mask is etched to contact the source electrode 65 with the ohmic contact layer 55 and the drain electrode ( 66 into a resistive contact layer 56 in contact with it.

At this time, as shown in FIG. 5B without removing the photoresist pattern PR used in the photolithography process for forming the data lines 62, 64, 65, 66, the data lines 62, 64, 65, 66. Remain on).

6A and 6B, a protective film 70 made of an insulating material, for example, silicon nitride, is deposited on the exposed front surface of the substrate. At this time, the protective film 70 may be formed of an organic insulating film, a silicon nitride film, or a multilayer film containing the same.                     

Next, the first contact hole 72 exposing the drain electrode 66, the second contact hole 74 exposing the data pad 64, and the third pad exposing the gate pad 24 are exposed by a photolithography process using a mask. The contact hole 76 is formed.

First, the passivation layer 70 is etched to expose the photoresist pattern PR on the drain electrode 66 and the data pad 64, and expose the gate insulating layer 30 on the gate pad 24. Subsequently, the exposed portion of the gate insulating film 30 is etched to form a third contact hole 76 exposing the gate pad 24.

In this case, when the protective film 70 is formed of a silicon nitride film, the protective film 70 and the gate insulating film 30 are made of the same material using only a mixed gas containing CF ₄ , SF _6, or the like. It is preferable to etch by a single etching process.

When the passivation layer 70 is formed of an organic insulating material, in particular, a photosensitive organic insulating material, the passivation layer 70 may be etched by only exposure and development operations. Subsequently, the gate insulating layer 30, which is a lower layer thereof, may be CF ₄ , SF _6, or the like. Etch using a mixed gas comprising a.

On the other hand, the molybdenum-based layer has a characteristic that is easily etched by a mixed etching gas containing CF ₄ , SF ₆ and the like. In the present invention, in order to prevent the molybdenum-based drain electrode 66 and the data pad 64 from being etched by a mixed etching gas, such as CF ₄ or SF ₆ , which etches the protective layer 70 or the gate insulating layer 30. The photoresist pattern PR is left on the drain electrode 66 and the data pad 64. The photoresist pattern PR protects the drain electrode 66 and the data pad 64 from the etching gas for etching the gate insulating layer 30. When the pattern formation is completed, it is common to remove the photoresist pattern for the subsequent process. However, in the present invention, the photoresist pattern PR is left on the data lines 62, 64, 65, and 66 by the etching gas during the subsequent etching process. The data lines 62, 64, 65, and 66 are prevented from being etched.

Subsequently, the exposed portion of the photoresist pattern PR may be removed by ashing by using the etched passivation layer 70 as a mask to expose the drain electrode 66 and the data pad 64 to expose the drain electrode 66 and the data pad 64. The first and second contact holes 72 and 74 exposing the first and second contact holes 72 and 74 are formed.

Next, as shown in FIGS. 1 and 2, the IZO layer or the ITO layer is deposited, and then etched by a photolithography process to contact the drain electrode 66 through the first contact hole 72. The auxiliary data pad 84 and the auxiliary gate pad 86 are formed to contact the data pad 64 and the gate pad 24 through the pixel electrode 82, the second and third contact holes 74 and 76, respectively. do.

Subsequently, a subsequent process is performed to complete the manufacture of the thin film transistor substrate.

FIG. 7 is a layout view of a thin film transistor substrate according to a second exemplary embodiment of the present invention, and FIGS. 8 and 9 are cross-sectional views respectively taken along the cutting lines ′-′ ′ and VII- ′ ′ shown in FIG. 7.

Gate wirings 22, 24, 26, and 28 formed of a low resistance metal material, for example, aluminum, molybdenum, chromium, and titanium, are formed on the insulating substrate 10. The gate lines 22, 24, 26, and 28 are connected to the gate lines 22 and the ends of the gate lines 22 extending in the horizontal direction and receive gate signals from the outside and transfer the gate pads 24 to the gate lines. And the gate line portions 22, 24, and 26 including the gate electrode 26 of the thin film transistor connected to the gate line 22, and the storage electrode 28 for the storage capacitor parallel to the gate line 22. Doing.

The storage electrode 28 overlaps with the conductor pattern 68 for the storage capacitor connected to the pixel electrode 82 to be described later to form a storage capacitor which improves the charge retention capability of the pixel. The pixel electrode 82 and the gate line to be described later will be described. If the holding capacity generated by the overlap of (22) is sufficient, it may not be formed.

The gate wirings 22, 24, 26, and 28 may be formed in a double layer or more structure in addition to the single layer structure. When the gate wirings 22, 24, 26, and 28 are formed in a double layer structure, at least one of the two layers is advantageously formed of a metal material having low resistance.

On the insulating substrate 10, a gate insulating film 30 made of an insulating material, for example, silicon nitride, covers the gate wirings 22, 24, 26, and 28.

Semiconductor patterns 42 and 48 made of a semiconductor material, for example, amorphous silicon, are formed on the gate insulating layer 30, and semiconductor materials, for example, doped with impurities, are doped on the semiconductor patterns 42 and 48. Resistive contact layer patterns 55, 56 and 58 made of amorphous silicon are formed.

On the ohmic contact layer patterns 55, 56, and 58, a metal material having excellent contact properties with the semiconductor layer and low resistance, for example, molybdenum series such as molybdenum (Mo) or molybdenum-tungsten (Mo-W) The data wirings 62, 64, 65, 66, and 68 made of furnaces are formed.

The data lines 62, 64, 65, 66, and 68 are formed in the vertical direction and connected to the data line 62 and the data line 62 crossing the gate line 22 to apply a gate signal from the outside. The data pad 64 and the data line 62 which receive and transfer the gate line to the source line 65 and protrude from the data line 62 to contact the one ohmic contact layer 55 to form a part of the thin film transistor. A sustain positioned over the data line portions 62, 64, 65, 66 and the sustain electrode 28, including the drain electrode 66 correspondingly contacting the other ohmic contact layer 56 to form part of the thin film transistor. The conductor pattern 68 for capacitors is included.

The semiconductor patterns 42 and 48 include a semiconductor pattern 42 for a thin film transistor and a semiconductor pattern 48 for a storage capacitor, which are regions between the source electrode 65 and the drain electrode 66, that is, the channel region of the thin film transistor. Except for the above, the data lines 62, 64, 65, 66, 68 and the ohmic contact layer patterns 55, 56, 58 have the same shape. That is, the semiconductor capacitor pattern 48 for the storage capacitor is the same as the conductor pattern 68 for the storage capacitor and the contact layer pattern 58 for the storage capacitor, whereas the semiconductor pattern 42 for the thin film transistor has the data line 62 described later. ), The same as the data line portions 62, 64, 65, 66 formed by the data pad 64, the source electrode 65, and the drain electrode 66, but between the source electrode 65 and the drain electrode 66. It further includes a region defined as a channel of the thin film transistor located.

Here, the ohmic contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. And the same shape as that of the data wirings 62, 64, 65, 66, and 68. At this time, one ohmic contact layer pattern 55 is in contact with the integral data line 62, the data pad 64 and the source electrode 65, and the other ohmic contact layer pattern 56 is connected to the drain electrode ( 66, and another contact layer pattern 58 is in contact with the conductor pattern 68 for the storage capacitor.

On the data lines 62, 64, 65, 66, 68, a photosensitive film pattern PR is formed along the data lines 62, 64, 65, 66, 68. Although the photoresist pattern PR will be described later in the manufacturing process, the data lines 62, 64, 65, 66, and 68 are left without being removed as an etch mask during the etching process.

The exposed front surface of the substrate including the photoresist pattern PR and the gate insulating layer 30 on the data lines 62, 64, 65, 66, and 68 may be formed of an organic insulating material, for example, acrylic resin. A protective film 70 made of BCB (BenzoCycloButane) or an inorganic insulating material, for example, silicon nitride, is formed. In this case, the passivation layer 70 may be formed of an insulating film of a multilayer including an organic insulating material layer and an inorganic insulating material layer.

The first, second and fourth contact holes 72, 74, and 78 that expose the drain electrode 66, the data pad 64, and the conductive pattern 68 for the storage capacitor are provided with the protective film 70 and the drain electrode. (66) Photoresist pattern (PR) on, protective film 70 and photoresist pattern (PR) on data pad 64, photoresist pattern (PR) on protective film (70) and conductor pattern 68 for storage capacitor It is formed in each. In addition, a third contact hole 76 exposing the gate pad 24 is formed in the protective film 70 and the gate insulating film 30.

The pixel electrode 82, the auxiliary gate pad 84, and the auxiliary data pad 86 made of IZO or ITO are formed on the passivation layer 70. The pixel electrode 82 contacts the drain electrode 66 and the conductive pattern 68 for a storage capacitor through the first and fourth contact holes 72 and 78. The auxiliary data pad 84 and the auxiliary gate pad 86 are in contact with the data pad 24 and the gate pad 64 through the second and third contact holes 74 and 76.

Next, a method of manufacturing the thin film transistor substrate according to the second exemplary embodiment of the present invention will be described with reference to FIGS. 10A through 17C and FIGS. 7, 8, and 9.

First, as shown in FIGS. 10A, 10B, and 10C, a metal material layer having a low resistance characteristic, for example, an aluminum based layer is deposited on the substrate 10, and patterned by a photolithography process to form a gate line ( 22, the gate wirings 22, 24, 26, 28 including the gate pad 24, the gate electrode 26, and the conductor pattern 28 for a storage capacitor are formed.

Next, a gate insulating film 30 made of an insulating material, for example, silicon nitride, which covers the gate wirings 22, 24, 26, and 28 is deposited on the substrate 10.

11A, 11B, and 11C, a semiconductor layer, a semiconductor layer doped with impurities, and a metal layer for data wiring are successively deposited on the gate insulating layer 30, and the multilayer is patterned by a photolithography process. Semiconductor pattern 42, 48, ohmic contact layer patterns 55, 56, and 58, and data pad 64, source electrode 65, drain electrode 66, and storage electrode 68 for a storage capacitor. Data wirings 62, 64, 65, 66, 68 are formed. The metal layer for data wiring is preferably formed of a metal material layer having excellent contact characteristics with the semiconductor layer and having low resistance, for example, molybdenum series.

At this time, the photoresist pattern PR used in the photolithography process is not removed and is left on the data lines 62, 64, 65, and 66 as shown in FIGS. 11B and 11C.

The ohmic contact layer patterns 55, 56, and 58 having the same pattern are in contact with the lower end of the data wires 62, 64, 65, 66, and 68, and the ohmic contact layer patterns 55, 56, and 58 are in contact with the bottom of the data line 62, 64, 65, 66, and 68. The semiconductor patterns 42 and 48 including the thin film transistor semiconductor pattern 42 and the storage capacitor semiconductor pattern 48 are in contact with each other. The thin film transistor semiconductor pattern 42 is the same as the data line portions 62, 64, 65, and 66, and further includes a region defined as a channel of the thin film transistor positioned between the source electrode 65 and the drain electrode 66. Include.

The data lines 62, 64, 65, 66, and 68, the ohmic contact layers 55, 56, and 58, and the semiconductor patterns 42 and 48 may be formed using only one mask. This will be described with reference to FIGS. 12A through 16B.

First, as shown in FIGS. 12A and 12B, the semiconductor layer 40 and the semiconductor layer 50 doped with impurities are continuously deposited on the gate insulating film 30 by chemical vapor deposition. Subsequently, the molybdenum-based metal layer 60 is deposited.

Next, as shown in FIGS. 13A and 13B, a photoresist film is coated on the molybdenum-based metal layer 60, and then irradiated with light through a mask (not shown), followed by development to develop photoresist patterns 112 and 114. To form. In this case, the photoresist patterns 112 and 114 may have a first portion 112 of the photoresist layer positioned at the data line portion A between the channel portion C of the thin film transistor, that is, between the source electrode 65 and the drain electrode 66. It is formed to be thicker than the second portion 114 of the positioned photosensitive film, and the other portion (B) is formed so as not to remain. The ratio of the thickness of the first portion 112 of the photosensitive film of the second portion 114 of the photosensitive film should be different depending on the process conditions in the etching process, which will be described later, but the thickness of the second portion 114 is determined by the first portion 112. It is preferable to set it as 1/2 or less of thickness.

As such, photoresist patterns having partially different thicknesses are formed using one mask having partially different transmittance. In order to control the light transmission, a slit or lattice pattern or a mask with a translucent film is used. In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

When the photosensitive film is irradiated with light through such a mask, the polymers are completely decomposed at the portion (C) directly exposed to the light, and the polymers are completely decomposed because the amount of light is less at the portion (B) corresponding to the slit pattern or translucent film. The polymer is hardly decomposed in the part A covered by the light shielding film. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.                     

When the selective exposed photoresist is developed, only portions where polymer molecules are not decomposed remain, and a photoresist having a thickness thinner than a portion that is not irradiated with light is left in the central portion irradiated with little light.

Next, as shown in FIGS. 14A and 14B, the metal layer 60 made of molybdenum-based exposed portion of the other portion B is etched using the photoresist patterns 112 and 114 as a mask, and impurities below The doped semiconductor layer 50 is exposed.

In this way, only the conductor patterns 67 and 68 in the channel portion C and the data wiring portion A remain, and the conductive layer in the other portion B is removed, and the semiconductor layer doped with impurities located thereunder. 50 is revealed. The conductor pattern 68 is a conductor pattern for the storage capacitor, and the conductor pattern 67 is a data wiring metal layer in which the source electrode 65 and the drain electrode 66 are not separated yet and exist in an integrated state.

Next, as shown in FIGS. 15A and 15B, the semiconductor layer 50 doped with the exposed impurities of the other portion B and the semiconductor layer 40 thereunder together with the second portion 114 of the photoresist film. Simultaneously removed by dry etching. The etching is performed under the condition that the photoresist patterns 112 and 114, the semiconductor layer 50 and the semiconductor layer 40 doped with impurities are simultaneously etched and the gate insulating film 30 is not etched. At this time, it is preferable to etch under the condition that the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness.

When the etch ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the second portion 114 of the photoresist layer is the sum of the thicknesses of the semiconductor layer 40 and the semiconductor layer 50 doped with impurities. It must be less than or equal to

In this case, the second portion 114 of the photoresist film positioned in the channel portion C is removed to expose the conductor pattern 67 of the channel portion C, and the semiconductor layer 50 doped with impurities in the other portion B. ) And the semiconductor layer 40 are removed to reveal the gate insulating film 30 thereunder. On the other hand, since the first portion 112 of the photosensitive film of the data wiring portion A is also etched, the thickness becomes thin.

In this step, the semiconductor patterns 42 and 48 including the thin film transistor semiconductor pattern 42 and the storage capacitor semiconductor pattern 48 are completed.

The ohmic contact layer 57 is formed on the thin film transistor semiconductor pattern 42 in the same pattern as the semiconductor pattern 42. The ohmic contact layer 58 is also formed on the semiconductor capacitor 48 for the storage capacitor. It is formed in the same pattern as 48).

Subsequently, residues of the second portion of the photoresist film remaining on the surface of the conductor pattern 67 of the channel portion C are removed by ashing.

Next, as shown in FIGS. 16A and 16B, the conductor pattern 67 located in the channel portion C and the resistive contact layer pattern thereunder (using the first portion 112 of the remaining photoresist pattern as a mask) 57) Etch the part.

In this case, a portion of the semiconductor pattern 42 may be removed to reduce the thickness, and the first portion 112 of the photoresist pattern may also be etched to a certain thickness. At this time, the etching must be performed under the condition that the gate insulating layer 30 is not etched, and the first portion 112 of the photoresist pattern is etched to expose the lower data lines 62, 64, 65, 66, and 68. It is preferable to thicken the photosensitive film pattern so that there is no.

In this way, the source electrode 65 and the drain electrode 66 are separated from the conductor pattern 67 to complete the data line 62, the source electrode 65, and the drain electrode 68, and the resistive contact thereunder. The layer patterns 55, 56, 58 are completed.

At this time, the first portion 112 of the photosensitive film pattern is not removed, and is left on the data lines 62, 64, 65, 66, and 68 as shown in FIGS. 16A and 16B. When the pattern formation is completed, the photoresist pattern is generally removed for the subsequent process. However, in the present invention, the photoresist pattern PR is left on the data lines 62, 64, 65, 66, and 68 to etch gas during the subsequent etching process. This prevents the data wires 62, 64, 65, 66, and 68 from being etched.

Next, as shown in FIGS. 17A, 17B, and 17C, a protective film 70 made of an insulating material, for example, silicon nitride, is deposited on the exposed entire surface of the substrate. At this time, the protective film 70 may be formed of an organic insulating film, a silicon nitride film, or a multilayer film containing the same.

Next, the first contact hole 72 exposing the drain electrode 66, the second contact hole 74 exposing the data pad 64, and the third gate exposing the gate pad 24 are formed by a photolithography process using a mask. A fourth contact hole 78 is formed which exposes the contact hole 76 and the conductor pattern 68 for the storage capacitor.                     

First, the protective film 70 is etched to expose the photoresist pattern PR on the drain electrode 66, the data pad 64, and the conductive capacitor pattern 68 for the storage capacitor, and the gate insulating film on the gate pad 24. 30). Subsequently, the exposed portion of the gate insulating film 30 is etched to form a third contact hole 76 exposing the gate pad 24.

In this case, when the protective film 70 is formed of a silicon nitride film, the protective film 70 and the gate insulating film 30 are made of the same material using only a mixed gas containing CF ₄ , SF _6, or the like. It is preferable to etch by a single etching process.

When the passivation layer 70 is formed of an organic insulating material, in particular, a photosensitive organic insulating material, the passivation layer 70 may be etched by only exposure and development operations. Subsequently, the gate insulating layer 30, which is a lower layer thereof, may be CF ₄ , SF _6, or the like. Etch using a mixed gas comprising a.

On the other hand, the molybdenum-based layer has a characteristic that is easily etched by a mixed etching gas containing CF ₄ , SF ₆ and the like. In the present invention, a molybdenum-based drain electrode 66, a data pad 64, and a conductive pattern for a storage capacitor are formed by a mixed etching gas such as CF ₄ or SF ₆ for etching the protective film 70 or the gate insulating film 30. In order to prevent the 68 from being etched, the photosensitive film pattern PR is left on the drain electrode 66, the data pad 64, and the conductive pattern 68 for the storage capacitor. The photoresist pattern PR blocks the drain electrode 66, the data pad 64, and the conductor pattern 68 for the storage capacitor from the etching gas for etching the gate insulating layer 30. When the pattern formation is completed, the photoresist pattern is generally removed for the subsequent process. However, in the present invention, the photoresist pattern PR is left on the data lines 62, 64, 65, 66, and 68 to etch gas during the subsequent etching process. This prevents the data wires 62, 64, 65, 66, and 68 from being etched.

Subsequently, the exposed portion of the photoresist pattern PR may be removed by ashing using the etched passivation layer 70 as a mask to expose the drain electrode 66, the data pad 64, and the conductive pattern 68 for the storage capacitor. , Second and third contact holes 72, 74, 78.

Next, as shown in FIGS. 7, 8, and 9, the IZO layer or the ITO layer is deposited, and then patterned by a photolithography process through the first and fourth contact holes 72 and 78. The data pad 64 and the gate pad 24 through the pixel electrode 82 and the second and third contact holes 74 and 76 in contact with the drain electrode 66 and the conductor pattern 68 for the storage capacitor. Auxiliary data pads 84 and auxiliary gate pads 86 that contact each are formed.

According to the present invention, the photoresist pattern used in the process of forming the data line is left on the data line, thereby preventing the data line from being etched by the etching gas used to etch the tapping etching layer during the subsequent etching process.

Claims (17)

Board, A gate wiring formed on the substrate, the gate wiring including a gate line and a gate electrode; A gate insulating film covering the gate wiring, A semiconductor pattern formed on the gate insulating layer, A data line formed on the gate insulating layer and including a data line, a source electrode, and a drain electrode; A photoresist pattern formed on the data line; A protective film covering the photosensitive film pattern and the semiconductor pattern; A first contact hole exposing the drain electrode, A pixel electrode contacting the drain electrode through the first contact hole Thin film transistor substrate comprising a. In claim 1, The data wiring line is formed of a molybdenum-based low resistance metal material. In claim 1, The first contact hole is formed in the photoresist pattern on the passivation layer and the drain electrode. In claim 1, The gate line further includes a gate pad connected to the gate line, The data line further includes a data pad connected to the data line, A second contact hole exposing the data pad, And a third contact hole exposing the gate pad. In claim 4, The second contact hole is formed in the photoresist pattern on the passivation layer and the data pad, and the third contact hole is formed in the passivation layer and the gate insulating layer. Forming a gate wiring including a gate line and a gate electrode on the substrate, Forming a gate insulating film covering the gate wiring; Forming a semiconductor pattern on the gate insulating layer; Depositing a metal layer for data wiring on the gate insulating layer and the semiconductor pattern; Forming a photosensitive film pattern for forming a data wiring on the data wiring metal layer; Etching the metal layer for data wiring using the photoresist pattern as a mask to form a data line including a data line, a source electrode, and a drain electrode; Forming a protective film covering the photoresist pattern and the semiconductor pattern; Forming a first contact hole in the photoresist pattern portion on the passivation layer and the drain electrode to expose the drain electrode; Forming a pixel electrode contacting the drain electrode through the first contact hole in the passivation layer. In claim 6, The metal layer for data wiring is formed of molybdenum-based thin film transistor substrate manufacturing method. In claim 6, The gate line further includes a gate pad connected to the gate line, The data line further includes a data pad connected to the data line, And forming second and third contact holes exposing the data pad and the gate pad when the first contact hole is formed. In claim 8, And forming the second contact hole in the photoresist pattern on the passivation film and the data pad, and the third contact hole in the passivation film and the gate insulating film. Forming a gate wiring including a gate line and a gate electrode on the substrate, Forming a gate insulating film covering the gate wiring; Continuously depositing a semiconductor layer and a metal layer for data wiring on the gate insulating layer; Forming a photoresist pattern on the data wiring metal layer; Etching the data wire metal layer and the semiconductor layer by using the photoresist pattern as a mask to form a data wire on the semiconductor pattern and the semiconductor pattern and including a data line, a source electrode, and a drain electrode; Forming a protective film covering the photoresist pattern and the semiconductor pattern; Forming a first contact hole exposing the drain electrode, Forming a pixel electrode contacting the drain electrode through the first contact hole on the passivation layer. In claim 10, The photoresist pattern may include a first portion having a first thickness on the upper portion of the data line and a second portion having a second thickness thinner than the first thickness on the upper portion between the source electrode and the drain electrode. Manufacturing method. In claim 11, The photosensitive film pattern is a method of manufacturing a thin film transistor substrate using a mask. In claim 12, And the mask is patterned to include a first region, a second region having a lower transmittance than the first region, and a third region having a higher transmittance than the first region. In claim 10, The metal layer for data wiring is formed of molybdenum-based thin film transistor substrate manufacturing method. In claim 10, And forming the first contact hole in the photoresist pattern on the passivation layer and the drain electrode. In claim 10, The gate line further includes a gate pad connected to the gate line, The data line further includes a data pad connected to the data line, And forming second and third contact holes exposing the data pad and the gate pad when the first contact hole is formed. The method of claim 16, And forming the second contact hole in the photoresist pattern on the passivation film and the data pad, and the third contact hole in the passivation film and the gate insulating film.

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