KR20070073276A - Manufacturing method of substrate for display device - Google Patents

Abstract

A manufacturing method of a substrate for a display device is provided to smoothly form a profile of an organic layer contact hole by means of a half tone mask. Signal lines including gate lines and data lines are formed. Thereafter, a photosensitive organic coating layer is formed on the signal line. The organic coating layer is developed and exposed by means of a mask with a half-tone pattern. Thereafter, an organic layer(75) having an organic layer contact hole corresponding to the half tone pattern is formed on the signal line. The organic coating layer is a negative type and the light transmittance of the half-tone pattern is reduced gradually from the center to the edge. A passivation layer is formed on the signal line. The passivation layer is etched by the organic layer as a mask so that the signal lines are exposed. The exposed signal lines are at least one of a drain electrode, a data pad(24) and a gate pad(68).

Description

Manufacturing Method of Substrate for Display Device {MANUFACTURING METHOD OF SUBSTRATE FOR DISPLAY DEVICE}

1 is a plan view of a thin film transistor substrate according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view taken along II-II of FIG. 1;

3 to 8 are cross-sectional views illustrating a manufacturing process of a thin film transistor substrate according to a first embodiment of the present invention;

9 is a plan view of a thin film transistor substrate according to a second embodiment of the present invention;

10 is a cross-sectional view taken along the line VII-VII of FIG. 9,

FIG. 11 is a cross-sectional view taken along the line XXXI-XI of FIG. 9;

12A to 20B are cross-sectional views illustrating a manufacturing process of a thin film transistor substrate according to a second embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

22 gate line 26 gate electrode

62: data line 65: source electrode

66: drain electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a substrate for a display device, and more particularly, to a method for manufacturing a substrate for a display device using a halftone mask to gently form a profile of an organic film contact hole.

The liquid crystal display is largely comprised of a liquid crystal panel, a backlight unit, a driver, a chassis, and the like. The liquid crystal panel includes a thin film transistor substrate on which a thin film transistor is formed, a color filter substrate on which a color filter is formed, and a liquid crystal layer positioned between both substrates.

Signal lines, such as gate lines and data lines, are formed on the thin film transistor substrate, and pixel electrodes are formed thereon. The signal line is connected to each pad provided in the non-display area for connection with an external circuit, and a protective film is formed between the signal line and the pixel electrode for insulation.

The protective film is usually made of silicon nitride (SiNx), and is deposited on the signal wiring by chemical vapor deposition (CVD). When the signal wiring and the pixel electrode are close to each other, cross talk occurs because silicon nitride located at the signal wiring and the pixel electrode becomes a dielectric to form a capacitance.

The capacitance C is represented by C = εA / d, where ε is the dielectric constant of the dielectric, A is the overlapping area between the signal wiring and the pixel electrode layer, and d is the distance between the signal wiring and the pixel electrode. In order to prevent crosstalk of dielectrics, the thickness of silicon nitride (distance between signal line and pixel electrode) should be increased to reduce the capacity. However, it is easy to take silicon nitride deposited by chemical vapor deposition to a desired thickness. Not. Accordingly, when only silicon nitride is used as the protective film, the aperture ratio is lowered because a constant distance must be maintained between the pixel electrode and the signal line in order to reduce cross talk.

An organic film was introduced to solve this problem. Since the organic film is formed on the signal wiring by a spin coating method or a slit coating method rather than chemical vapor deposition, the thickness can be increased. Therefore, the pixel electrode can be formed close to or overlapping the signal line, thereby improving the aperture ratio.

Drain electrodes, gate pads, and data pads of the signal wirings are covered with a transparent conductive material. For this purpose, the upper organic layers are removed to form contact holes. However, since the thickness of the organic layer is large, there is a problem in that the profile of the contact hole is inclined so that the step coverage of the transparent conductive material is poor. In order to solve this problem, a contact hole is formed using a mask in which a slit pattern is formed.

Accordingly, it is an object of the present invention to provide a method for manufacturing a substrate for a display device with a gentle profile of a contact opening exposing signal wiring.

The above object is to form a signal wiring line comprising a gate wiring line and a data wiring line; Forming a photosensitive organic coating layer on the signal line; Exposing and developing the organic coating layer using a mask having a halftone pattern to form an organic layer having an organic film contact hole corresponding to the halftone pattern on the signal line. By the method.

The organic coating layer is of a negative type, the light transmittance is preferably reduced as the halftone pattern is farther from the center.

The organic coating layer is a positive type, the light transmittance is preferably increased as the halftone pattern is farther from the center.

Forming a passivation layer on the signal line; The method may further include exposing the signal line by etching the passivation layer on the contact layer of the organic layer using the organic layer as a mask.

The exposed signal line may be at least one of a drain electrode, a data pad, and a gate pad.

The method may further include forming a contact member covering the exposed signal line by forming and patterning a transparent conductive layer on the organic layer.

The organic layer is preferably made of any one of a benzocyclobutene (BCB) series, an olefin series, an acrylic resin series, a polyimide series, a teflon series, a cytotop, and a PFCB (perfluorocyclobutane).

The organic coating layer preferably has a thickness of 1 μm to 5 μm.

Forming the signal wiring comprises: forming the gate wiring; It is preferable to include the step of continuously forming a gate insulating film, a semiconductor layer, an ohmic contact layer, a data metal layer on the gate semiconductor layer.

Preferably, the semiconductor layer, the ohmic contact layer, and the data metal layer are patterned using a single mask.

The method may further include forming a photoresist film on the data metal layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness.

The second portion is preferably provided in pairs with the first portion therebetween.

The ohmic contact layer and the data wiring layer below the first portion may be removed by etching.

The ohmic contact layer and the data line layer may be patterned to overlap each other.

Hereinafter, a display device substrate manufactured according to the present invention and a method of manufacturing the same will be described. A thin film transistor is formed on the substrate for a display device described below, and the substrate for the display device may be used in various display devices such as a liquid crystal display, an organic light emitting display (OLED), and an electrophoretic display (EPD).

In the description, 'on' or 'on' means that another layer (membrane) is interposed or not interposed between two layers (membrane), and 'just on' indicates that two layers (membrane) are in contact with each other.

1 is a plan view of a thin film transistor substrate according to a first embodiment of the present invention, Figure 2 is a cross-sectional view taken along the line II-II of the thin film transistor substrate shown in FIG. 3 to 8 are cross-sectional views illustrating a process of manufacturing the thin film transistor substrate according to the first embodiment of the present invention.

Gate wirings 22, 24, and 26 are formed on the insulating substrate 10. The gate lines 22 and 26 include a gate line 22 extending in the horizontal direction and a gate electrode 26 of the thin film transistor connected to the gate line 22. Here, the gate pad 24, which is one end of the gate line 22, is extended in width for connection with an external circuit.

On the insulating substrate 10, a gate insulating film 30 made of silicon nitride (SiNx) covers the gate wirings 22, 24, and 26.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30 of the gate electrode 24, and n + having a high concentration of silicide or n-type impurity is formed on the semiconductor layer 40. Resistive contact layers 55 and 56 made of a material such as hydrogenated amorphous silicon are formed, respectively.

Data lines 65, 66, and 68 are formed on the ohmic contacts 55 and 56 and the gate insulating layer 30. The data lines 62, 65, and 66 are formed in the vertical direction and intersect the gate line 22 to define the pixel, the branch of the data line 62, the data line 62, and the upper portion of the ohmic contact layer 55. A drain electrode 66 which is separated from the extending source electrode 65 and the source electrode 65 and is formed on the ohmic contact layer 56 opposite to the source electrode 65 with respect to the gate electrode 26. It includes. At this time, the data pad 68, which is one end of the data line 62, is extended in width for connection with an external circuit.

A-Si: C: O film or a deposited on the data lines 62, 65, 66, 68 and on the semiconductor layer 40 which is not covered by silicon nitride (SiNx) or plasma enhanced chemical vapor deposition (PECVD) A protective film 71 made of a -Si: O: F film (low dielectric constant CVD film) or the like is formed. The a-Si: C: O film and a-Si: O: F film (low dielectric constant CVD film) deposited by the PECVD method have a dielectric constant of 4 or less (the dielectric constant has a value between 2 and 4). The dielectric constant is very low. Excellent adhesion to another film and step coverage. Moreover, since it is an inorganic CVD film, heat resistance is excellent compared with an organic insulating film. In addition, the a-Si: C: O film and a-Si: O: F film (low dielectric constant CVD film) deposited by the PECVD method have a 4 to 10 times faster process time than the silicon nitride film in terms of deposition rate and etching rate. It is also very advantageous in terms of.

The organic layer 75 is formed on the passivation layer 71. The organic layer 75 may be formed of any one of a benzocyclobutene (BCB) series, an olefin series, an acrylic resin series, a polyimide series, a teflon series, a cytotop, and a PFCB (perfluorocyclobutane). The thickness may be 1 μm to 5 μm.

In the organic layer 75, contact holes 76 and 78 exposing the drain electrode 66 and the data pad 68 are formed together with the passivation layer 71, and together with the gate insulating layer 30 and the passivation layer 71. The contact hole 74 which exposes the gate pad 24 is formed. The profile of each contact hole 74, 76, 78 is formed very smoothly here.

The pixel electrode 82, which is electrically connected to the drain electrode 66 and positioned in the pixel region, is formed on the organic layer 75 through the contact hole 76. In addition, contact auxiliary members 86 and 88 are formed on the organic layer 75 to be connected to the gate pad 24 and the data pad 68 through the contact holes 74 and 78, respectively. Here, the pixel electrode 82 and the contact auxiliary members 86 and 88 are made of a transparent conductive film such as indium tin oxide (ITO) or indium zinc oxide (IZO).

1 and 2, the pixel electrode 82 overlaps with the gate line 22 to form a storage capacitor. When the storage capacitor is insufficient, the pixel electrode 82 is disposed on the same layer as the gate lines 22, 24, and 26. It is also possible to add a storage capacitor wiring.

In addition, the pixel electrode 82 may also be formed to overlap the data line 62 to maximize the aperture ratio. Even if the pixel electrode 82 is formed to overlap the data line 62 in order to maximize the aperture ratio, the parasitic capacitance formed between them by the use of the low dielectric constant and the large thickness of the organic film 75 is not a problem. Kept small.

Referring to the method of manufacturing the thin film transistor substrate according to the first embodiment, first, as shown in FIG. 3, a gate metal layer is deposited on the insulating substrate 10, and patterned by a photolithography process using a mask. ) And gate electrodes 26 including the gate electrode 26 and extending in the horizontal direction.

Next, as shown in FIG. 4, the three-layer film of the gate insulating film 30 made of silicon nitride, the semiconductor layer 40 made of amorphous silicon, and the doped amorphous silicon layer 50 is successively laminated, and the semiconductor layer 40 ) And the doped amorphous silicon layer 50 are photo-etched to form an island-like semiconductor layer 40 and an ohmic contact layer 50 on the gate insulating layer 30 on the gate electrode 24.

Next, as shown in FIG. 5, the data metal layer is deposited and patterned by a photolithography process using a mask to be connected to the data line 62 and the data line 62 crossing the gate line 22 to be connected to the gate electrode 26. A data line including a source electrode 65 extending to an upper portion and a drain electrode 66 separated from the source electrode 65 and facing the source electrode 65 with respect to the gate electrode 26. do.

Subsequently, the doped amorphous silicon layer pattern 50, which is not covered by the data lines 62, 65, 66, and 68, is etched and separated on both sides of the gate electrode 26, while both doped amorphous silicon layers ( The semiconductor layer pattern 40 between 55 and 56 is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 40, it is preferable to perform oxygen plasma.

Next, as shown in FIG. 6, the protective film 70 and the organic coating layer 750 are sequentially formed, and then the organic coating layer 750 is exposed using the mask 100. The organic coating layer 750 is a negative type in which the exposed portion is decomposed.

The mask 100 includes a base substrate 101 made of quartz or the like, a chromium layer 102 formed on the base substrate 101, and a half tone pattern 103.

The chromium layer 102 blocks 100% of the incident ultraviolet rays, while the halftone pattern 103 may adjust the amount of incident ultraviolet rays according to the material and the thickness. The halftone pattern 103 may be made of MoSi or CrN.

The mask 100 is arranged such that the half tone patterns 103 correspond to the drain electrode 66, the gate pad 24, and the data pad 68, respectively. Each half-tone pattern 103 is provided to pass the most ultraviolet light in the center portion and to pass an increasing amount of ultraviolet light away from the center.

On the other hand, unlike the embodiment, when the organic coating layer 750 is a positive type in which an unexposed portion is decomposed, the halftone pattern 103 does not allow ultraviolet rays to pass through the central portion, but passes more ultraviolet rays away from the central portion. Can be prepared.

7 illustrates a state in which the exposed organic coating layer 750 is developed to form an organic layer 75. The organic film contact holes 76a, 74a, and 78a corresponding to the drain electrode 66, the gate pad 24, and the data pad 68 are formed in the organic film 75, respectively.

Here, the organic film contact holes 76a, 74a, and 78a have a gentle profile because the organic film contact holes 76a, 74a, and 78a are formed by using the halftone pattern 103.

Subsequently, as shown in FIG. 8, the protective layer 71 and / or the gate insulating layer 30 under the organic layer contact holes 76a, 74a, and 78a are etched using the organic layer 75 as a mask to etch the contact holes 76, 74, and the like. 78). The contact holes 76, 74 and 78 also have a gentle profile like the organic film contact holes 76a, 74a and 78a.

Next, as shown in FIGS. 1 and 2, the ITO or IZO film is deposited and photo-etched to connect the pixel electrode 82 and the contact holes 74 and 78 connected to the drain electrode 66 through the contact hole 76. Contact auxiliary members 86 and 88 are formed to be connected to the gate pad 24 and the end portion 68 of the data line, respectively. It is preferable to use nitrogen as the gas used in the pre-heating process before laminating ITO or IZO.

Here, since the contact holes 76, 74, 78 have a gentle profile, the step coverage of the pixel electrode 82 and the contact auxiliary members 86, 88 is improved.

The first embodiment described above uses five masks in the manufacture of a thin film transistor substrate, and the second embodiment described below uses four masts.

9 is a plan view of a thin film transistor substrate according to a second embodiment of the present invention, FIG. 10 is a cross-sectional view taken along the line VII-VII of FIG. 9, and FIG. 11 is a sectional view taken along the line VII-XI of FIG. 9. to be. 12A to 20B are cross-sectional views illustrating a manufacturing process of a thin film transistor substrate according to a second embodiment of the present invention.

Gate wirings 22, 24, and 26 are formed on the insulating substrate 10 as in the first embodiment.

The storage electrode line 28 is formed on the substrate material 10 in parallel with the gate line 22. The storage electrode line 28 overlaps with the conductor 64 for the storage capacitor connected to the pixel electrode 82 to be described later to form a storage capacitor which improves charge storage capability of the pixel. The pixel electrode 82 and the gate line (to be described later) It may not be formed if the holding capacity resulting from the overlap of 22) is sufficient. The same voltage as that of the common electrode of the upper substrate is usually applied to the storage electrode line 28.

A gate insulating film 30 made of silicon nitride (SiNx) is formed on the gate wirings 22, 24, 26 and the storage electrode line 28 to cover the gate wirings 22, 24, 26 and the storage electrode line 28. .

On the gate insulating layer 30, semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed, and on the semiconductor patterns 42 and 48, n-type impurities such as phosphorus (P) have a high concentration. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon doped with is formed.

The data lines 62, 64, 65, 66, and 68 are formed on the ohmic contact layer patterns 55, 56, and 58. The data lines 62, 64, 65, 66, 68 are formed in the vertical direction and have a data line 62 connected to one end of the data line 62 to receive image signals from the outside. And data line portions 62, 68, and 65 made up of a source electrode 65 of the thin film transistor, which is a branch of the data line 62, and is separated from the data line portions 62, 68, and 65, and is a gate electrode. Or the storage capacitor conductor 64 positioned on the drain electrode 66 and the storage electrode line 28 of the thin film transistor, which is located opposite to the source electrode 65 with respect to the channel portion E of the thin film transistor. . When the storage electrode line 28 is not formed, the storage capacitor conductor 64 is also not formed.

The contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has exactly the same form as (62, 64, 65, 66, 68). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 68, and 65, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor 64 for holding power storage machines.

The semiconductor patterns 42 and 48 have the same shape as the data lines 62, 64, 65, 66, and 68 and the ohmic contact layer patterns 55, 56, and 58 except for the channel portion C of the thin film transistor. Doing. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor 64 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the semiconductor pattern 42 for the thin film transistor has a data wiring and a contact layer. Slightly different from the rest of the pattern. That is, in the channel portion C of the thin film transistor, the data line portions 62, 68, and 65, in particular, the source electrode 65 and the drain electrode 66 are separated, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor.

On the data lines 62, 64, 65, 66 and 68, an a-Si: C: O film or a-Si: O: F film (low dielectric constant CVD) deposited by silicon nitride or plasma enhanced chemical vapor deposition (PECVD) method Film) is formed.

The organic layer 75 is formed on the passivation layer 71. The organic layer 75 may be formed of any one of a benzocyclobutene (BCB) series, an olefin series, an acrylic resin series, a polyimide series, a teflon series, a cytotop, and a PFCB (perfluorocyclobutane). The thickness may be 1 μm to 5 μm.

The organic film 75 has, together with the protective film 71, contact holes 76, 78, 72 exposing the drain electrode 66, the data pad 68 and the conductor 64 for the storage capacitor. The contact hole 74 which exposes the gate line pad 24 is provided with the insulating film 30 and the protective film 71. Here, the profiles of the contact holes 72, 74, 76, and 78 are formed very smoothly.

On the organic layer 75, a pixel electrode 82 is formed which receives an image signal from a thin film transistor and generates an electric field together with the electrodes of the upper plate. The pixel electrode 82 is made of a transparent conductive material such as ITO or indium tin oxide (IZO), and is physically and electrically connected to the drain electrode 66 through the contact hole 76 to receive an image signal. The pixel electrode 82 also overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. The pixel electrode 82 is also connected to the storage capacitor conductor 64 through the contact hole 72 to transmit an image signal to the conductor pattern 64. On the other hand, contact auxiliary members 86 and 88 are formed on the gate line pad 24 and the data pad 68 through the contact holes 74 and 78, respectively. The contact auxiliary members 86 and 88 complement the adhesion between the pads 24 and 68 and the external circuit device and protect the pads 24 and 68, and are also formed of a transparent conductive film.

Looking at the manufacturing method of the thin film transistor substrate according to the second embodiment, as shown in Figure 12a and 12b, the gate metal layer is deposited and patterned in the same manner as the first embodiment to include a gate line 22, the gate electrode 26 The gate wiring and the storage electrode line 28 are formed. In this case, the width of the gate pad 24 connected to the external circuit is extended.

Next, as shown in FIGS. 13A and 13B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 made of silicon nitride are respectively 1,500 kV to 5,000 kPa and 500 kPa to 2,000 kPa using chemical vapor deposition. Then, the film is continuously deposited to a thickness of 300 이어 to 600 Å, and then the conductor layer 60 is formed to form a data line, and then the photosensitive film 110 is applied thereon to a thickness of 1 μm to 2 μm.

Thereafter, the photosensitive film 110 is irradiated with light through a mask and then developed to form photosensitive film patterns 112 and 114 as shown in FIGS. 14A and 14B. At this time, the channel portion C of the photosensitive film patterns 112 and 114, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, is the data wiring portion A, that is, the data. The thickness of the wirings 62, 64, 65, 66, and 68 is smaller than that of the second portion 112 positioned at the portion where the wirings 62, 64, 65, 66, and 68 are to be formed. At this time, the ratio of the thickness of the photoresist film 114 remaining in the channel portion C to the thickness of the photoresist film 112 remaining in the data wiring portion A should be different depending on the process conditions in the etching process described later. It is preferable that the thickness of the first portion 114 is 1/2 or less of the thickness of the second portion 112, for example, 4,000 kPa or less.

As such, there may be various methods of varying the thickness of the photoresist film according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure machine used for exposure, and in the case of using a translucent film, the transmittance is different in order to control the transmittance when fabricating a mask. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all the polymer molecules are decomposed, so it should not be so.

This thin photoresist film 114 is developed using a photoresist film made of a reflowable material and exposed with a conventional mask that is divided into a part that can completely transmit light and a part that can not completely transmit light. It may be formed by reflowing a portion of the photosensitive film to a portion where the photosensitive film does not remain.

Subsequently, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40. In this case, the data line and the lower layer of the data line remain in the data wiring portion A, and only the semiconductor layer should remain in the channel portion C, and the upper three layers 60, 50, 40 must be removed to expose the gate insulating film 30.

First, as shown in FIGS. 15A and 15B, the conductor layer 60 exposed to the other portion B is removed to expose the lower intermediate layer 50. In this process, either a dry etching method or a wet etching method may be used. In this case, the conductor layer 60 may be etched and the photoresist patterns 112 and 114 may be hardly etched. However, in the case of dry etching, it is difficult to find a condition in which only the conductor layer 60 is etched and the photoresist patterns 112 and 114 are not etched, and thus the photoresist patterns 112 and 114 may be etched together. In this case, the thickness of the first portion 114 is thicker than that of the wet etching so that the first portion 114 is removed in this process so that the lower conductive layer 60 is not exposed.

This leaves only the conductor layer of the channel portion C and the data wiring portion A, that is, the source / drain conductor pattern 67 and the storage capacitor conductor 64, as shown in Figs. 15A and 15B. The conductor layer 60 of the other portion B is all removed to reveal the underlying intermediate layer 50. The remaining conductor patterns 67 and 64 are the same as those of the data lines 62, 64, 65, 66 and 68 except that the source and drain electrodes 65 and 66 are connected without being separated. . In addition, when dry etching is used, the photoresist patterns 112 and 114 are also etched to a certain thickness.

Subsequently, as shown in FIGS. 16A and 16B, the exposed intermediate layer 50 of the other portion B and the semiconductor layer 40 below it are simultaneously removed together with the first portion 114 of the photosensitive film by a dry etching method. do. At this time, etching is performed under the condition that the photoresist patterns 112 and 114, the intermediate layer 50, and the semiconductor layer 40 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched, and the gate insulating layer 30 is not etched. In particular, it is preferable to etch under conditions where the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etch ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first portion 114 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50.

This removes the first portion 114 of the channel portion C, revealing the source / drain conductor pattern 67, as shown in FIGS. 16A and 16B, and the intermediate layer 50 of the other portion B. And the semiconductor layer 40 is removed to expose the gate insulating layer 30 thereunder. On the other hand, since the second portion 112 of the data line portion C is also etched, the thickness becomes thin. In this step, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 denote intermediate layer patterns under the source / drain conductor patterns 67 and intermediate layer patterns under the storage capacitor conductors 64, respectively.

Subsequently, ashing removes photoresist residue remaining on the surface of the source / drain conductor pattern 67 of the channel portion C.

Next, as illustrated in FIGS. 17A and 17B, the source / drain conductor pattern 67 of the channel portion C and the source / drain interlayer pattern 57 below are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 67 and the intermediate layer pattern 57. The etching may be performed by wet etching on the source / drain conductor pattern 67. 57 may be performed by dry etching. In the former case, it is preferable to perform etching under a condition where the etching selectivity of the source / drain conductor pattern 67 and the interlayer pattern 57 is large, which is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 42 remaining in (C). In the latter case of alternating between wet etching and dry etching, the side surface of the conductive pattern 67 for wet etching of the source / drain is etched, but the intermediate layer pattern 57 which is dry etched is hardly etched, and thus is formed in a step shape. Examples of the etching gas used to etch the intermediate layer pattern 57 and the semiconductor pattern 42 include a mixture gas of CF ₄ and HCl or a mixture gas of CF ₄ and O ₂ , and CF ₄ and O ₂ . The semiconductor pattern 42 may be left at a uniform thickness. In this case, as shown in FIG. 16B, a portion of the semiconductor pattern 42 may be removed to reduce the thickness, and the second portion 112 of the photoresist pattern may also be etched to some extent. At this time, the etching should be performed under the condition that the gate insulating film 30 is not etched, and the photoresist film is not exposed so that the second portion 112 is etched so that the data lines 62, 64, 65, 66, and 68 underneath are not exposed. It is a matter of course that the pattern is thick.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 under the data lines.

Finally, the second photoresist layer 112 remaining in the data wiring portion A is removed. However, the removal of the second portion 112 may be performed after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 57 thereunder.

As mentioned earlier, wet and dry etching can be alternately used, or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

Next, as shown in FIGS. 18A and 18B, the protective layer 70 and the organic coating layer 750 are sequentially formed, and then the organic coating layer 750 is exposed using the mask 100. The organic coating layer 750 is a negative type in which the exposed portion is decomposed.

The mask 100 includes a base substrate 101 made of quartz or the like, a chromium layer 102 formed on the base substrate 101, and a half tone pattern 103.

The chromium layer 102 blocks 100% of the incident ultraviolet rays, while the halftone pattern 103 may adjust the amount of incident ultraviolet rays according to the material and the thickness. The halftone pattern 103 may be made of MoSi or CrN.

The mask 100 is arranged such that the half tone patterns 103 correspond to the drain electrode 66, the gate pad 24, the data pad 68, and the storage capacitor conductor 64, respectively. Each half-tone pattern 103 is provided to pass the most ultraviolet light in the center portion and to pass an increasing amount of ultraviolet light away from the center.

19A and 19B illustrate a state in which the exposed organic coating layer 750 is developed to form an organic layer 75. The organic film contact holes 76a, 74a, 78a, and 72a corresponding to the drain electrode 66, the gate pad 24, and the storage capacitor conductor 64 are formed in the organic film 75, respectively.

Here, the organic film contact holes 76a, 74a, 78a, and 72a have a gentle profile, since the organic film contact holes 76a, 74a, 78a, and 72a are formed using the halftone pattern 103. to be.

Next, as shown in FIGS. 20A and 20B, the protective layer 71 and / or the gate insulating layer 30 under the organic layer contact holes 76a, 74a, and 78a are etched using the organic layer 75 as a mask to form the contact hole 76. , 74, 78, 72). The contact holes 76, 74, 78, 72 also have a gentle profile like the organic film contact holes 76a, 74a, 78a, 72a.

Lastly, as shown in FIGS. 10 and 11, a pixel electrode connected to the drain electrode 66 and the storage capacitor conductor 64 by depositing and photolithography an ITO layer or an IZO layer having a thickness of 400 kV to 500 kV. 82, a gate contact auxiliary member 86 connected to the gate line pad 24, and a data contact auxiliary member 88 connected to the data pad 68 are formed.

Here, since the contact holes 76, 74, 78, 72 have a gentle profile, the step coverage of the pixel electrode 82 and the contact auxiliary members 86, 88 is improved.

On the other hand, as a gas used in the pre-heating process before laminating ITO or IZO, it is preferable to use nitrogen, which is the metal film 24 exposed through the contact holes 72, 74, 76, 78. This is to prevent the metal oxide film from being formed on the upper portions of 64, 66 and 68.

In the second embodiment of the present invention, the data wirings 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, 58 and the semiconductor pattern 42 below the data wirings 62, 64, 65, 66, and 68, as well as the effects of the first embodiment. , 48 may be formed using a single mask, and the manufacturing process may be simplified by separating the source electrode 65 and the drain electrode 66 in this process.

The thin film transistor substrate according to the present invention may be used in a display device such as a liquid crystal display, an organic light emitting diode, an electrophoretic display, and the like.

The organic electroluminescent device is a self-luminous device using an organic material that emits light upon receiving an electrical signal. In the organic electroluminescent device, a cathode layer (pixel electrode), a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer, and an anode layer (counter electrode) are stacked. The drain electrode of the TFT substrate according to the present invention may be electrically connected to the cathode layer to apply a data signal.

As described above, according to the present invention, a method of manufacturing a substrate for a display device with a gentle profile of a contact hole exposing signal wirings is provided.

Claims (14)

Forming a signal wiring including a gate wiring and a data wiring; Forming a photosensitive organic coating layer on the signal line; And exposing and developing the organic coating layer using a mask having a halftone pattern to form an organic layer having an organic layer contact hole corresponding to the halftone pattern on the signal line. Method for producing a substrate for use. The method of claim 1, The organic coating layer is of a negative type, The light transmittance decreases as the halftone pattern moves away from the center. The method of claim 1, The organic coating layer is of a positive type, And the light transmittance increases as the halftone pattern moves away from the center. The method according to claim 2 or 3, Forming a passivation layer on the signal line; And etching the passivation layer on the contact layer of the organic layer using the organic layer as a mask to expose the signal line. The method of claim 4, wherein The exposed signal line is at least one of a drain electrode, a data pad, and a gate pad. The method of claim 4, wherein Forming a contact member covering the exposed signal line by forming and patterning a transparent conductive layer on the organic layer. The method of claim 4, wherein The organic layer is characterized in that it is made of any one of BCB (benzocyclobutene) series, olefin series, acrylic resin series, polyimide series, Teflon series, cytotopes, PFCB (perfluorocyclobutane) Method for manufacturing a substrate for an apparatus. The method of claim 4, wherein The organic coating layer has a thickness of 1 μm to 5 μm. The method according to claim 2 or 3, The signal wiring is formed, Forming the gate wiring; And continuously forming a gate insulating film, a semiconductor layer, an ohmic contact layer, and a data metal layer on the gate semiconductor layer. The method of claim 9, The semiconductor layer, the ohmic contact layer, and the data metal layer are patterned using a single mask. The method of claim 10, And forming a photoresist film on the data metal layer, the photosensitive film including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness. Way. The method of claim 11, And the second portion is provided in pairs with the first portion interposed therebetween. The method of claim 12, And the resistive contact layer and the data wiring layer under the first portion are removed by etching. The method of claim 13, And the resistive contact layer and the data wiring layer are patterned to overlap each other.

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