CN107275343B - Manufacturing method of bottom gate type TFT substrate - Google Patents
Manufacturing method of bottom gate type TFT substrate Download PDFInfo
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- CN107275343B CN107275343B CN201710454064.2A CN201710454064A CN107275343B CN 107275343 B CN107275343 B CN 107275343B CN 201710454064 A CN201710454064 A CN 201710454064A CN 107275343 B CN107275343 B CN 107275343B
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- 239000000758 substrate Substances 0.000 title claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 129
- 229910052751 metal Inorganic materials 0.000 claims abstract description 122
- 239000002184 metal Substances 0.000 claims abstract description 122
- 238000000034 method Methods 0.000 claims abstract description 64
- 230000004888 barrier function Effects 0.000 claims abstract description 51
- 239000000463 material Substances 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 321
- 238000002161 passivation Methods 0.000 claims description 44
- 229920002120 photoresistant polymer Polymers 0.000 claims description 24
- 238000000151 deposition Methods 0.000 claims description 20
- 238000000059 patterning Methods 0.000 claims description 18
- 239000011241 protective layer Substances 0.000 claims description 16
- 238000001312 dry etching Methods 0.000 claims description 14
- 230000002093 peripheral effect Effects 0.000 claims description 12
- 238000005240 physical vapour deposition Methods 0.000 claims description 10
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 229910052733 gallium Inorganic materials 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 239000011733 molybdenum Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052593 corundum Inorganic materials 0.000 claims description 3
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 3
- KYKLWYKWCAYAJY-UHFFFAOYSA-N oxotin;zinc Chemical compound [Zn].[Sn]=O KYKLWYKWCAYAJY-UHFFFAOYSA-N 0.000 claims description 2
- 239000011787 zinc oxide Substances 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims 3
- 239000010408 film Substances 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 239000011521 glass Substances 0.000 description 3
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- 238000010292 electrical insulation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 239000002253 acid Substances 0.000 description 1
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- 238000007796 conventional method Methods 0.000 description 1
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- 239000011159 matrix material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
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- 230000001681 protective effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Thin Film Transistor (AREA)
Abstract
The invention provides a method for manufacturing a bottom gate type TFT substrate, which comprises the steps of forming a first etching barrier layer on a gate metal layer, forming a second etching barrier layer on a source drain metal layer, etching the first etching barrier layer and the second etching barrier layer by using first etching gas when via holes are respectively formed above the gate metal layer and the source drain metal layer, respectively forming a first primary via hole and a second primary via hole above the gate metal layer and above the source drain metal layer, simultaneously etching the first etching barrier layer below the first primary via hole and the second etching barrier layer below the second primary via hole by using second etching gas, and simultaneously etching the first etching barrier layer and the second etching barrier layer by using the same material and thickness so as to simultaneously form a first via hole above the gate metal layer and a second via hole above the source drain metal layer, the source and drain contact resistance and the circuit connection are prevented from being influenced by serious over-etching of the source and drain metal layer.
Description
Technical Field
The invention relates to the technical field of display, in particular to a manufacturing method of a bottom gate type TFT substrate.
Background
Thin Film Transistors (TFTs) are the main driving elements in Liquid Crystal Displays (LCDs) and Active Matrix Organic electroluminescent displays (AMOLEDs), and are directly related to the development of high performance flat panel displays. Therefore, both the display panel of the LCD and the display panel of the AMOLED generally have a TFT substrate. Taking the LCD display panel as an example, the LCD display panel mainly comprises a TFT substrate, a Color Filter (CF) substrate, and a Liquid Crystal Layer (Liquid Crystal Layer) disposed between the two substrates, and the operating principle is to apply driving voltages to the TFT substrate and the CF substrate to control the rotation of Liquid Crystal molecules in the Liquid Crystal Layer, so as to refract the light of the backlight module to generate a picture.
Fig. 1 is a schematic structural diagram of a bottom gate TFT substrate in the prior art, and as shown in fig. 1, the bottom gate TFT substrate includes a glass substrate 100, a gate metal layer 200 disposed on the glass substrate 100, a gate insulating layer (GI)300 disposed on the gate metal layer 200 and the glass substrate 100, an active layer 400 disposed on the gate insulating layer 300, a source/drain metal layer 500 disposed on the active layer 400 and the gate insulating layer 300, and a passivation layer (PV)600 disposed on the source/drain metal layer 500 and the gate insulating layer 300; the gate metal layer 200 and the source/drain metal layer 500 are formed by patterning, wherein the gate metal layer 200 includes a gate 210 and a gate terminal 220; the source-drain metal layer 500 includes a source 510, a drain 520, and a source-drain terminal 530.
In addition, after the passivation layer 600 is formed, a through hole is formed on the source/drain metal layer 500 and the electrical insulating layer above the gate metal layer 200 by one etching, and then a light-transmitting conductive film is plated to connect the gate terminal 220, the source/drain terminal 530 and the peripheral circuit, and connect the drain 520 and the pixel electrode, i.e. a through hole is formed on the passivation layer 600 above the source/drain metal layer 500 by etching, and a through hole is formed on the gate insulating layer 300 above the gate metal layer 200 and the passivation layer 600 by etching, however, in the etching process, the thickness of the electrical insulating layer formed above the source/drain metal layer 500 is the thickness h1 of the passivation layer 600, and the thickness of the electrical insulating layer formed above the gate metal layer 200 is the thicknesses h1+ h2 of the passivation layer 600 and the gate insulating layer 300, and to ensure that the gate insulating layer 300 above the gate metal layer 200 is etched through, often, over-etching is required to be performed by more than 30% on the basis of the thickness (h1+ h2) of the electrical insulation layer above the gate metal layer 200, so that the electrical insulation layer above the source/drain metal layer 500 is etched through first in the etching process, so that the source/drain is seriously over-etched, and the contact resistance and the line connection of the source/drain are further influenced.
Disclosure of Invention
The invention aims to provide a manufacturing method of a bottom gate type TFT substrate, which is characterized in that etching barrier layers are formed on a gate metal layer and a source drain metal layer, so that through holes are synchronously formed above the gate metal layer and the source drain metal layer, and the source drain metal layer is prevented from being seriously overetched to influence the contact resistance and the line connection of a source drain.
In order to achieve the above object, the present invention provides a method for manufacturing a bottom gate TFT substrate, comprising the steps of:
step S1, providing a substrate, sequentially depositing a first metal layer and a first insulating oxide layer on the substrate, patterning the first insulating oxide layer and the first metal layer, obtaining a gate metal layer from the first metal layer, and obtaining a first etching stop layer having the same pattern shape as the gate metal layer from the first insulating oxide layer;
step S2, depositing a gate insulating layer on the first etching stop layer and the substrate, and depositing and patterning an active layer on the gate insulating layer;
step S3, sequentially depositing a second metal layer and a second insulating oxide layer with the same material and thickness as the first insulating oxide layer on the active layer and the gate insulating layer, patterning the second insulating oxide layer and the second metal layer, obtaining a source/drain metal layer from the second metal layer, and obtaining a second etching stop layer with the same pattern shape as the source/drain metal layer from the second insulating oxide layer;
step S4, depositing a passivation protective layer on the second etching barrier layer and the gate insulating layer, forming a photoresist pattern on the passivation protective layer, performing dry etching on the passivation protective layer and the gate insulating layer by using a first etching gas with the photoresist pattern as a shielding layer, wherein in the etching process, the first etching gas cuts through the passivation protective layer and the gate insulating layer above the gate metal layer to expose the surface of the first etching barrier layer, so as to form a first primary via hole, and simultaneously the first etching gas cuts through the passivation protective layer above the source drain metal layer to expose the surface of the second etching barrier layer, so as to form a second primary via hole, and stopping the dry etching;
step S5, performing dry etching on the first etching barrier layer and the second etching barrier layer by using a second etching gas, wherein in the etching process, the second etching gas etches the first etching barrier layer below the first primary via hole to expose the surface of the gate metal layer, so as to form a first via hole penetrating through the passivation protective layer, the gate insulating layer and the first etching barrier layer, and simultaneously the second etching gas etches the second etching barrier layer below the second primary via hole to expose the surface of the source drain metal layer, so as to form a second via hole penetrating through the passivation protective layer and the second etching barrier layer;
and step S6, depositing and patterning a transparent conducting layer on the passivation protective layer, wherein the transparent conducting layer is connected with the grid metal layer through the first via hole, and the transparent conducting layer is connected with the source drain metal layer through the second via hole.
The first insulating oxide layer and the second insulating oxide layer are both made of Al2O3。
The first insulating oxide layer and the second insulating oxide layer are formed by deposition through a physical vapor deposition method or an atomic layer deposition method.
The first insulating oxide layer deposited in step S1 has a thickness of
The step S4 of forming the photoresist pattern on the passivation layer is to coat a photoresist film on the passivation layer, expose and develop the photoresist film, and thereby form the photoresist pattern.
The gate metal layer patterned in the step S1 includes a gate and a gate terminal; the active layer formed in the step S2 is correspondingly located above the gate; the source and drain metal layer formed by patterning in the step S3 includes a source, a drain, and a source and drain terminal; the transparent conductive layer patterned in the step S6 includes pixel electrodes and peripheral circuit connection lines;
the first through hole is correspondingly positioned above the grid connecting terminal, and the peripheral line connecting line is connected with the grid connecting terminal through the first through hole;
the second via hole comprises a second internal connection via hole correspondingly positioned above the drain electrode and a second external connection via hole correspondingly positioned above the source-drain electrode wiring terminal; the pixel electrode is connected with the drain electrode through the second internal connection through hole, and the peripheral line connecting line is connected with the source-drain electrode connecting terminal through the second external connection through hole.
In steps S1 and S3, the patterning process includes sequentially performing a photoresist coating process, an exposure process, a developing process, an etching process, and a photoresist stripping process, wherein the etching process is a wet etching process;
the step S3 further includes performing dry etching on the surface of the active layer exposed by the source/drain metal layer to form a channel region of the active layer.
The first metal layer and the second metal layer are formed by deposition through a physical vapor deposition method, and the materials of the first metal layer and the second metal layer are one or more of molybdenum, titanium, aluminum and tantalum in a stacked combination mode.
The grid electrode insulating layer and the passivation protective layer are formed by deposition through a chemical vapor deposition method, and the grid electrode insulating layer and the passivation protective layer are made of silicon nitride or silicon oxide.
The active layer is made of amorphous silicon, indium gallium zinc oxide or indium gallium zinc tin oxide.
The invention has the beneficial effects that: the invention relates to a method for manufacturing a bottom gate type TFT substrate, which comprises the steps of forming a first etching barrier layer on a gate metal layer, forming a second etching barrier layer on a source drain metal layer, etching the first etching barrier layer and the second etching barrier layer by using first etching gas when via holes are respectively formed above the gate metal layer and the source drain metal layer, respectively forming a first primary via hole and a second primary via hole above the gate metal layer and above the source drain metal layer, simultaneously etching the first etching barrier layer below the first primary via hole and the second etching barrier layer below the second primary via hole by using second etching gas, and simultaneously etching the first etching barrier layer and the second etching barrier layer by using the same material and thickness so as to synchronously form the first via hole above the gate metal layer and the second via hole above the source drain metal layer, the source and drain contact resistance and the circuit connection are prevented from being influenced by serious over-etching of the source and drain metal layer.
Drawings
For a better understanding of the nature and technical aspects of the present invention, reference should be made to the following detailed description of the invention, taken in conjunction with the accompanying drawings, which are provided for purposes of illustration and description and are not intended to limit the invention.
In the drawings, there is shown in the drawings,
FIG. 1 is a schematic diagram of a via hole formed above a gate metal layer and a source/drain electrode in a conventional method for manufacturing a bottom gate TFT substrate;
FIG. 2 is a schematic flow chart of a method for fabricating a bottom gate type TFT substrate according to the present invention;
fig. 3-4 are schematic views of step S1 of the method for fabricating a bottom-gate TFT substrate according to the present invention;
FIGS. 5 to 7 are schematic views of step S2 of the method for fabricating a bottom-gate TFT substrate according to the present invention;
fig. 8 to 9 are schematic views of step S3 of the method for fabricating a bottom gate type TFT substrate according to the present invention;
fig. 10 to 11 are schematic views of step S4 of the method for fabricating a bottom-gate TFT substrate according to the present invention;
fig. 12 is a schematic view of step S5 of the method for fabricating a bottom-gate TFT substrate according to the present invention;
fig. 13 is a schematic view of step S6 of the method for fabricating a bottom-gate TFT substrate according to the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Referring to fig. 2, the present invention provides a method for fabricating a bottom gate TFT substrate, including the following steps:
step S1, as shown in fig. 3-4, provides a substrate 1, sequentially deposits a first metal layer 20 on the substrate 1 by a Physical Vapor Deposition (PVD) method, deposits a first insulating oxide layer 30 by a Physical Vapor Deposition (PVD) method or an Atomic Layer Deposition (ALD) method, then performs a patterning process on the first insulating oxide layer 30 and the first metal layer 20 to obtain a gate metal layer 2 from the first metal layer 20, and obtains a first etching stop layer 3 with the same pattern shape as the gate metal layer 2 from the first insulating oxide layer 30.
Specifically, the first insulating oxide layer 30 deposited in step S1 has a thickness of
Specifically, the material of the first metal layer 20 is molybdenum (Mo), titanium (Ti), aluminum (Al), tantalum (Ta), or a stacked combination thereof.
Specifically, the gate metal layer 2 patterned in the step S1 includes a gate 21 and a gate terminal 22 for connecting to peripheral circuits.
Specifically, in step S1, the patterning of the first insulating oxide layer 30 and the first metal layer 20 includes sequentially performing a photoresist coating process, an exposure process, a developing process, an etching process, and a photoresist stripping process, wherein the etching process is a wet etching process.
Step S2, as shown in fig. 5-7, a gate insulating layer 4 is deposited on the first etch stop layer 3 and the substrate 1 by Chemical Vapor Deposition (CVD), and an active layer 5 corresponding to the upper portion of the gate electrode 21 is deposited and patterned on the gate insulating layer 4.
Specifically, the process of forming the active layer 5 in step S2 is to deposit a semiconductor film amorphous silicon (a-Si) layer 50 and an N-type ion doped layer (N + -Si)51 on the gate insulating layer 4, wherein the N-type ions doped in the N-type ion doped layer 51 may be pentavalent ions such as phosphorus ions. Here, the N-type ion doped layer 51 forms an ohmic contact with the subsequent source/drain metal layer 60. Then, the amorphous silicon (a-Si) layer 50 and the N-type ion doped layer (N + -Si)51 are patterned to obtain the active layer 5.
Specifically, the material of the gate insulating layer 4 is silicon nitride (SiNx) or silicon oxide (SiO)2)。
Step S3, as shown in fig. 8 to 9, sequentially depositing a second metal layer 60 on the active layer 5 and the gate insulating layer 4 by a physical vapor deposition method, depositing a second insulating oxide layer 70 with the same material and thickness as the first insulating oxide layer 30 by a physical vapor deposition method or an atomic layer deposition method, patterning the second insulating oxide layer 70 and the second metal layer 60, obtaining a source/drain metal layer 6 from the second metal layer 60, and obtaining a second etching stop layer 7 with the same pattern shape as the source/drain metal layer 6 from the second insulating oxide layer 70.
Specifically, the source-drain metal layer 6 patterned in the step S3 includes a source 61, a drain 62, and a source-drain connection terminal 63 for connecting to peripheral circuits.
Specifically, in step S3, the patterning of the second insulating oxide layer 70 and the second metal layer 60 includes sequentially performing a photoresist coating process, an exposure process, a developing process, an etching process, and a photoresist stripping process, wherein the etching process is a wet etching process;
specifically, the step S3 further includes performing dry etching on the surface of the active layer 5 exposed by the source/drain metal layer 6 to form a channel region of the active layer 5.
Specifically, the material of the second metal layer 60 is molybdenum, titanium, aluminum, tantalum, or a stack combination thereof.
Step S4, as shown in fig. 10-11, depositing a passivation protection layer 8 on the second etching barrier layer 7 and the gate insulating layer 4 by a chemical vapor deposition method, forming a photoresist pattern on the passivation protection layer 8, and performing dry etching on the passivation protection layer 8 and the gate insulating layer 4 by using a first etching gas with the photoresist pattern as a shielding layer, wherein in the etching process, the first etching gas etches the passivation protection layer 8 and the gate insulating layer 4 above the gate metal layer 2 to expose the surface of the first etching barrier layer 3, so as to form a first primary via hole 85 ', and simultaneously the first etching gas etches the passivation protection layer 8 above the source/drain metal layer 6 to expose the surface of the second etching barrier layer 7, so as to form a second primary via hole 86', and stop the dry etching.
Specifically, the process of forming the photoresist pattern on the passivation protection layer 8 in step S4 is to coat a photoresist film on the passivation protection layer 8, expose and develop the photoresist film, and thereby form the photoresist pattern.
Specifically, the passivation protection layer 8 is made of silicon nitride or silicon oxide.
In particular, of the first insulating oxide layer 30 and the second insulating oxide layer 70The materials may all be Al2O3Or may be another insulating metal oxide that is soluble in acid and has a larger dry etching selectivity with respect to the gate insulating layer 4 and the passivation layer 8.
Specifically, the etching rate of the first etching gas used in step S4 on the first etching stop layer 3 and the second etching stop layer 7 is very slow, which is much lower than the etching rate on the gate insulating layer 4 and the passivation layer 8, so that the dry etching stops on the first etching stop layer 3 and the second etching stop layer 7 when the first etching gas etches the first etching stop layer 3 and the second etching stop layer 7.
Step S5, as shown in fig. 12, dry etching is performed on the first etching barrier layer 3 and the second etching barrier layer 7 by using a second etching gas, during the etching process, the second etching gas etches the first etching barrier layer 3 under the first primary via hole 85 'to expose the surface of the gate metal layer 2, so as to form a first via hole 85 penetrating through the passivation protective layer 8, the gate insulating layer 4, and the first etching barrier layer 3, and simultaneously the second etching gas etches the second etching barrier layer 7 under the second primary via hole 86' to expose the surface of the source/drain metal layer 6, so as to form a second via hole 86 penetrating through the passivation protective layer 8 and the second etching barrier layer 7.
Specifically, in the step S5, a second etching gas having a different composition from the first etching gas is used, and since the first etching barrier layer 3 and the second etching barrier layer 7 are made of the same material and have the same thickness, and the thicknesses are both very thin, they can be etched through at the same time, so that the first via hole 85 can be formed above the gate metal layer 2, and the second via hole 86 can be formed above the source/drain metal layer 6, thereby preventing the source/drain metal layer 6 from being etched seriously to affect the source/drain contact resistance and the line connection.
Step S6, as shown in fig. 13, depositing and patterning a transparent conductive layer 9 on the passivation protection layer 8, where the transparent conductive layer 9 is connected to the gate metal layer 2 through the first via hole 85, and the transparent conductive layer 9 is connected to the source/drain metal layer 6 through the second via hole 86.
Specifically, the transparent conductive layer 9 patterned in the step S6 includes the pixel electrode 91 and the peripheral wiring connection line 92.
Specifically, the first via 85 is correspondingly located above the gate terminal 22, and the peripheral line connection line 92 is connected to the gate terminal 22 through the first via 85.
Specifically, the second via hole 86 includes a second inner via hole 861 correspondingly located above the drain electrode 62, and a second outer via hole 862 correspondingly located above the source-drain connection terminal 63; the pixel electrode 91 is connected to the drain electrode 62 through the second internal via 861, and the peripheral line connection line 92 is connected to the source/drain connection terminal 63 through the second external via 862.
In summary, in the method for fabricating the bottom gate TFT substrate of the present invention, a first etching stop layer is formed on a gate metal layer, a second etching stop layer is formed on a source/drain metal layer, and then when vias are formed above the gate metal layer and above the source/drain metal layer, a first etching gas is first used to etch the first etching stop layer and the second etching stop layer, a first primary via and a second primary via are formed above the gate metal layer and above the source/drain metal layer, respectively, and then a second etching gas is used to simultaneously etch the first etching stop layer below the first primary via and the second etching stop layer below the second primary via And a second through hole is formed above the source and drain metal layer, so that the source and drain metal layer is prevented from being seriously etched to influence the source and drain contact resistance and the line connection.
As described above, it will be apparent to those skilled in the art that various other changes and modifications can be made based on the technical solution and the technical idea of the present invention, and all such changes and modifications should fall within the protective scope of the appended claims.
Claims (10)
1. A method for manufacturing a bottom gate type TFT substrate is characterized by comprising the following steps:
step S1, providing a substrate (1), sequentially depositing a first metal layer (20) and a first insulating oxide layer (30) on the substrate (1), patterning the first insulating oxide layer (30) and the first metal layer (20), obtaining a gate metal layer (2) from the first metal layer (20), and obtaining a first etching barrier layer (3) with the same pattern shape as the gate metal layer (2) from the first insulating oxide layer (30);
step S2, depositing a gate insulating layer (4) on the first etching barrier layer (3) and the substrate (1), and depositing and patterning an active layer (5) on the gate insulating layer (4);
step S3, sequentially depositing a second metal layer (60) and a second insulating oxide layer (70) with the same material and thickness as the first insulating oxide layer (30) on the active layer (5) and the gate insulating layer (4), patterning the second insulating oxide layer (70) and the second metal layer (60), obtaining a source and drain metal layer (6) from the second metal layer (60), and obtaining a second etching barrier layer (7) with the same pattern shape as the source and drain metal layer (6) from the second insulating oxide layer (70);
step S4, depositing a passivation protection layer (8) on the second etching barrier layer (7) and the gate insulation layer (4), forming a light resistance pattern on the passivation protection layer (8), using the light resistance pattern as a shielding layer, and performing dry etching on the passivation protection layer (8) and the gate insulation layer (4) by using first etching gas, wherein in the etching process, the first etching gas penetrates through the passivation protection layer (8) and the gate insulation layer (4) above the gate metal layer (2) to expose the surface of the first etching barrier layer (3) to form a first primary via hole (85 '), and simultaneously the first etching gas penetrates through the passivation protection layer (8) above the source drain metal layer (6) to expose the surface of the second etching barrier layer (7) to form a second primary via hole (86'), and stopping the dry etching;
step S5, performing dry etching on the first etching barrier layer (3) and the second etching barrier layer (7) by using a second etching gas, wherein in the etching process, the second etching gas etches the first etching barrier layer (3) below the first primary via hole (85 ') to expose the surface of the gate metal layer (2) to form a first via hole (85) penetrating through the passivation protective layer (8), the gate insulating layer (4) and the first etching barrier layer (3), and simultaneously the second etching gas etches the second etching barrier layer (7) below the second primary via hole (86') to expose the surface of the source drain metal layer (6) to form a second via hole (86) penetrating through the passivation protective layer (8) and the second etching barrier layer (7);
step S6, depositing and patterning a transparent conducting layer (9) on the passivation protective layer (8), wherein the transparent conducting layer (9) is connected with the grid metal layer (2) through the first via hole (85), and the transparent conducting layer (9) is connected with the source drain metal layer (6) through the second via hole (86);
the etching rate of the first etching barrier layer (3) and the second etching barrier layer (7) by the first etching gas used in the step S4 is smaller than the etching rate of the gate insulating layer (4) and the passivation protective layer (8).
2. The method of manufacturing a bottom gate type TFT substrate according to claim 1, wherein the first insulating oxide layer (30) and the second insulating oxide layer (70) are made of Al2O3。
3. The method of manufacturing a bottom gate type TFT substrate according to claim 1, wherein the first insulating oxide layer (30) and the second insulating oxide layer (70) are formed by deposition using a physical vapor deposition method or an atomic layer deposition method.
4. The method of fabricating a bottom-gate type TFT substrate as set forth in claim 1, wherein the first insulating oxide layer (30) deposited in the step S1 has a thickness of
5. The method of fabricating a bottom-gate TFT substrate as set forth in claim 1, wherein the step of forming the photoresist pattern on the passivation protection layer (8) in the step S4 is to coat a photoresist film on the passivation protection layer (8), expose and develop the photoresist film, thereby forming the photoresist pattern.
6. The method of fabricating a bottom-gate type TFT substrate as claimed in claim 1, wherein the gate metal layer (2) patterned in the step S1 includes a gate electrode (21) and a gate connection terminal (22); the active layer (5) formed in the step S2 is correspondingly positioned above the gate electrode (21); the source and drain metal layer (6) formed by patterning in the step S3 comprises a source (61), a drain (62) and a source and drain wiring terminal (63); the transparent conductive layer (9) patterned in the step S6 comprises a pixel electrode (91) and a peripheral circuit connecting line (92);
the first through hole (85) is correspondingly positioned above the gate connecting terminal (22), and the peripheral line connecting line (92) is connected with the gate connecting terminal (22) through the first through hole (85);
the second via hole (86) comprises a second inner via hole (861) correspondingly positioned above the drain electrode (62) and a second outer via hole (862) correspondingly positioned above the source-drain electrode wiring terminal (63); the pixel electrode (91) is connected with the drain electrode (62) through the second internal connecting through hole (861), and the peripheral circuit connecting wire (92) is connected with the source drain electrode connecting terminal (63) through the second external connecting through hole (862).
7. The method of claim 1, wherein the patterning in steps S1 and S3 comprises performing a photoresist coating process, an exposure process, a developing process, an etching process, and a photoresist stripping process in sequence, wherein the etching process is a wet etching process;
and the step S3 further comprises the step of carrying out dry etching on the surface of the active layer (5) exposed by the source drain metal layer (6) to form a channel region of the active layer (5).
8. The method of claim 1, wherein the first metal layer (20) and the second metal layer (60) are deposited by physical vapor deposition, and the first metal layer (20) and the second metal layer (60) are made of a stacked combination of one or more of molybdenum, titanium, aluminum, and tantalum.
9. The method of manufacturing a bottom gate type TFT substrate according to claim 1, wherein the gate insulating layer (4) and the passivation layer (8) are formed by chemical vapor deposition, and the gate insulating layer (4) and the passivation layer (8) are made of silicon nitride or silicon oxide.
10. The method of fabricating the bottom-gate type TFT substrate according to claim 1, wherein the active layer (5) is made of amorphous silicon, indium gallium zinc oxide, or indium gallium zinc tin oxide.
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| CN101750825A (en) * | 2008-12-18 | 2010-06-23 | 乐金显示有限公司 | Array substrate for display device and method for fabricating the same |
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| CN101750825A (en) * | 2008-12-18 | 2010-06-23 | 乐金显示有限公司 | Array substrate for display device and method for fabricating the same |
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